CN112395233A - Software definition switching system and method based on CPU and SDI chip - Google Patents
Software definition switching system and method based on CPU and SDI chip Download PDFInfo
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- 230000036541 health Effects 0.000 claims abstract description 22
- 238000006243 chemical reaction Methods 0.000 claims description 24
- 230000000903 blocking effect Effects 0.000 claims description 5
- 239000004744 fabric Substances 0.000 claims description 5
- 238000012423 maintenance Methods 0.000 claims description 3
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- 230000004927 fusion Effects 0.000 abstract description 6
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- 238000012938 design process Methods 0.000 description 1
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Abstract
The invention provides a software definition exchange system and method based on a CPU and an SDI chip, comprising the following steps: a CPU unit: configuring a switching unit formed by the SDI chip to realize various software definition switching; a switching unit: realizing the exchange of network data; BMC unit: implementing health management on the CPU unit and the switching unit, reporting the health information of the CPU unit and the switching unit, and implementing according to a set health management strategy; the CPU unit and the switching unit communicate through a PCIE bus to realize software definition switching; the BMC unit is communicated with the CPU unit through a serial port to obtain working states of the CPU unit and the switching unit, and the BMC unit is interconnected with sensors of the CPU unit and the switching unit through I2C to obtain corresponding health information. The invention realizes the fusion interconnection among heterogeneous networks, improves the interconnection efficiency and reduces the reduction of performance and real-time performance during the fusion.
Description
Technical Field
The invention relates to the technical field of software definition, in particular to a software definition switching system and method based on a CPU and an SDI chip.
Background
Currently, information systems architectures are undergoing a change from von neumann to software definition, and with the rapid development of artificial intelligence technology, the demand for new generation software definition architectures is becoming more urgent. The system architecture belongs to basic, general, subversive and asymmetric technologies, is difficult to innovate, and needs to be continuously invested for a long time; the method has wide application range and can be widely applied to various infrastructures, systems, components and chips. Therefore, the system architecture has great research significance and great benefit. The system structure comprises two parts of a processing component and a connection relation, namely interconnection, wherein the interconnection is one of two important determinants of the system structure, and the interconnection technology is becoming the focus and the high point of future competition of the information field.
The future information system pays more attention to the intellectualization of human-computer interaction and the automation of control operation, the future network is an intelligent network and is a complex system, and the required interconnection technology is a flexible and changeable interconnection network which has various protocols, developed connection, dynamic triggering, networking on demand and low safety and consumption.
However, the current switch interconnect technology is far behind the need for development, and is embodied in the following aspects:
1. the existing interconnection is based on a specific protocol, and a solution of a bridge chip is adopted in a large quantity aiming at interconnection requirements among different protocols;
2. the interconnection bandwidth of each port of the existing interconnection is also fixedly distributed, so that the networking of the system is inflexible and the expansion is inconvenient;
3. the existing interconnected internal exchange topological structure is also fixed, is usually constructed according to a specific communication model, and cannot be suitable for more application scenes;
4. the internal working modes of the existing interconnections are usually fixed, either circuit switching or packet switching, and flexible switching between various working modes cannot be realized;
5. protocol conversion of the existing interconnection is usually completed by a special bridge chip, and a flexible protocol conversion mode of each port cannot be supported.
Therefore, the current information system is still a rigid structure of fixed protocol interconnection essentially, and in order to implement flexibility and diversity of support services, a plurality of technologies such as Software Defined Network (SDN), software defined Storage (SDM), software defined data center (SDC) and the like are provided, but all of them are software definitions based on standardized components implemented in a high-level protocol, the underlying hardware structure (especially physical layer and link layer) is still rigid, and software definition of functions and performance needs to be implemented through software virtualization, which has the outstanding problems of low efficiency, impaired performance, reduced real-time performance and the like. Meanwhile, software-defined hardware is a software definition at a physical level, which is not only a base and a kernel of the software definition, but also the most difficult and challenging technology in the software definition.
The software definition exchange based on the autonomous controllable domestic processor and the SDI chip is developed based on the software definition interconnection technology, and the technical connotation specifically comprises the following steps: 1) the protocol type may be software defined: SRIO protocol, Ethernet protocol and FC protocol can be defined respectively; 2) the protocol conversion may be software defined: the interconversion between any supported heterogeneous protocols can be realized on each interconnection port; 3) interconnect bandwidth can be software defined: the rate supported by each interconnection port and the whole interconnection bandwidth can be defined, including partial utilization degree, full utilization degree, different scheduling strategies, service quality and the like; 4) the interconnect port may be software defined: the binding mode of each interconnection port can be arbitrarily defined from modes of 1x, 2x, 4x and the like, and the type of the port and the flow control mode of the port can also be defined; 5) the exchange pattern may be software defined: not only point-to-point unicast, point-to-multipoint multicast, point-to-all-point broadcast, but also circuit switched, packet switched, hybrid switched, and the like can be supported. 6) The software defined interconnection technology naturally supports isomerism, redundancy and dynamics, and belongs to an endogenous safe mimicry architecture.
The existing interconnection is based on a specific protocol, and a solution of a bridge chip is largely adopted according to the interconnection requirements among different protocols, and the software-defined switching module only adopts one piece of software-defined switching module to realize the interconnection among different protocols.
The interconnection bandwidth for interconnecting each port in the prior art is also fixedly allocated, which causes inflexibility of system networking and inconvenience of capacity expansion, while the software-defined switching module can define the rate and bandwidth of the port according to actual requirements, which can define the rates of 1.25, 2.125, 2.5, 3.125, 4.25, 5, 6.25, 8.5 and 10.3125Gbaud, etc., and the SRIO port supports three port binding modes: 1x, 2x, 4 x;
the existing interconnected internal switching topological structure is also fixed, is usually constructed according to a specific communication model and cannot be suitable for more application scenes, and the software defined switching module can convert the switching topological structure according to the definition that the actual application supports three network protocol flexibilities, namely FC, Ethernet and SRIO;
the internal working modes of the existing interconnection are usually fixed, either circuit switching or packet switching, and flexible switching among various working modes cannot be realized, and the software-defined switching module can support point-to-point unicast, point-to-multipoint multicast, point-to-all point broadcast, circuit switching mode, packet switching mode, hybrid switching mode and the like;
the protocol conversion of the existing interconnection is usually completed by a special bridge chip, which cannot support the flexible protocol conversion mode of each port, and the software-defined switching module can support the flexible protocol conversion mode of each port by flexibly defining three network protocols of FC, ethernet and SRIO.
SRIO: serial Rapid I/O, a high speed Serial interface; SEDES: SERIALIZER/DESERIALIZE, SERIAL deserializer; 1000 BASE-X: gigabit ethernet over fiber; MDI: a media dependent interface; PCIe: peripheral Component Interconnect Express, Peripheral Component Interconnect standard; SGMII: serial Gigabit Media Interface Independent Interface of Serial Media; SDI: software defined interconnection; SDN: a software defined network; and (3) SDM: software definition storage; SDC: a software defined data center; FC: a light pipe protocol.
Patent document CN106454183A (application number: CN201610796893.4) discloses a configurable multi-channel video switching device with multiple control interfaces, which can dynamically configure logic functions and set interfaces according to field requirements, implement bidirectional data flow of the interfaces, and implement multiple mappings and topologies among different interfaces. The apparatus comprises: the system comprises an FPGA, a CPU, a control interface and at least two video interfaces; the FPGA is connected with the video interface, the CPU interacts with an external main control device through the control interface, receives an external control request, correspondingly initializes and sets the video interface according to the request content, and simultaneously configures the FPGA as required to complete the mapping and topology requirements among various video interfaces requested by the external device.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a software definition switching system and method based on a CPU and an SDI chip.
The software definition switching system based on the CPU and the SDI chip provided by the invention comprises:
a CPU unit: configuring a switching unit formed by the SDI chip to realize various software definition switching;
a switching unit: realizing the exchange of network data;
BMC unit: implementing health management on the CPU unit and the switching unit, reporting the health information of the CPU unit and the switching unit, and implementing according to a set health management strategy;
the CPU unit and the switching unit communicate through a PCIE bus to realize software definition switching;
the BMC unit is communicated with the CPU unit through a serial port to obtain working states of the CPU unit and the switching unit, and the BMC unit is interconnected with sensors of the CPU unit and the switching unit through I2C to obtain corresponding health information.
Preferably, the CPU unit includes: the system comprises a CPU processor, a Flash plug-in, a memory, a serial port and a debugging network port;
the Flash plug-in is used for storing a starting code and a system kernel of the CPU, is hung on a CPU bus of the CPU processor and realizes address latching through the address latch;
the clock frequency of the memory is more than or equal to 200MHz, and a dynamic random access memory is selected to complete the running of a CPU program;
the serial port is hung on the transceiver through a UART interface of the CPU processor and then is output through the VPX connector;
the debugging network port is connected with the VPX connector by converting an SGMII interface of the CPU processor into an MDI interface through the PHY.
Preferably, the switching unit includes: all ports are interconnected by an open switch fabric.
Preferably, the SDI chip includes a plurality of channels, each channel configures the channel into a corresponding protocol type in a software-defined manner according to the protocol type of the connected endpoint device, and after data enters the chip, determines whether protocol conversion is required according to a destination address of the data: if the protocol conversion is not needed, the network directly enters an internal non-blocking switching network; if necessary, the protocol conversion is completed and then the data enters the exchange network to be transmitted to the corresponding output port.
Preferably, the CPU unit accesses and configures the SDI chip through the PCIE, I2C, and JTAG interface.
Preferably, the SDI chip is defined as an FC switching chip for use, and is connected to an existing FC switching network;
defining the SDI chip as a RapidIO exchange chip for use, and connecting the SDI chip to the existing RapidIO exchange network;
the SDI chip is defined as an Ethernet exchange chip for use and is connected to an existing Ethernet exchange network;
when configured for use with a RapidIO switch chip, supporting the RapidIO protocol defined maintenance packet access functionality.
Preferably, the SDI chip is connected to endpoint devices or networks of multiple protocols, and for heterogeneous network scenarios:
-when there is no transition scenario for the hybrid protocol, the SDI chip replaces multiple different switch chips;
and when the mixed protocol is converted, the SDI chip is connected with each protocol to carry out protocol conversion and exchange.
The software definition exchange method based on the CPU and the SDI chip provided by the invention comprises the following steps:
step 1: determining a protocol type, a port mode and a port rate;
step 2: configuring an interface according to requirements through a serial port or a network port of the CPU;
and step 3: configuring a required protocol, port rate and port mode through application software running on an operating system;
and 4, step 4: and after receiving the configuration command, the CPU configures a corresponding register of the SDI chip through the PCIE bus, completes corresponding configuration and stores the configuration.
Compared with the prior art, the invention has the following beneficial effects: the CPU, the SDI chip and the operating system form a basic layer of the software definition switching system, application software runs on the basic layer, a user configures the basic layer through the application software to realize various application switching, and the CPU serves as a main control to configure the SDI chip through an interface between the CPU and the SDI chip. The software definition switching system breaks through a rigid system structure of the existing network, and realizes a full-dimensional software defined network system from a physical layer, a data link layer, a network layer to a service layer, so that the rigid network is changed into a flexible network, a definable, reconfigurable and reconstructable software defined system structure is constructed, the fusion and interconnection among heterogeneous networks are realized, the interconnection efficiency is improved, and the performance and real-time performance reduction during the fusion is reduced. The software defined switching system is a flexible interconnected switching system, and realizes single protocol switching application of three networks of SRIO, Ethernet and FC, mixed protocol switching application of the three networks and mixed protocol switching application with protocol conversion of the three networks.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a block diagram of software defined switching modules;
FIG. 2 is a block diagram of CSP2020 CPU architecture;
FIG. 3 is a basic block diagram of the NMS 3210;
FIG. 4 is a basic block diagram of A2F 500;
FIG. 5 is a diagram of a FC application scenario;
FIG. 6 is a diagram of an SRIO application scenario;
FIG. 7 is a diagram of an application scenario of Ethernet;
FIG. 8 is a diagram of a three hybrid protocol no-conversion application scenario;
fig. 9 is a diagram of three hybrid protocol conversion application scenarios.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Example (b):
the software defined switching module based on the autonomous controllable domestic processor and the SDI chip is composed of a CPU unit, a switching unit, a BMC unit and the like, and provides the maximum switching capacity of 320Gbps to the outside. The whole exchange module provides 4 paths of 2xRapidIO, 3 paths of 1xRapidIO, 6 paths of 1000BASE-X, 3 paths of FC and 6 paths of gigabit MDI exchange ports and 2 paths of IPMB health management interfaces. And providing 1 path of RS-232 serial ports and one path of gigabit network ports as configuration management ports, providing 1 path of RS-232 serial ports as configuration management of a BMC health management unit, using 1 path of JTAG ports as software updating and debugging interfaces of the health management unit, and reporting 1 path of RS485 as a BMC health state.
An RS232 interface is reserved between the BMC and the CPU and used for communication between the two units, and the BMC acquires information such as the state of the exchange port. The CPU unit is responsible for configuration management and software definition strategies of the software definition switching module, the BMC unit is responsible for health information management and reporting, and the switching unit completes data switching. The software defined switching module based on the autonomous controllable domestic processor and the SDI chip is a network switching module for transmitting data, and the structure of the software defined switching module is that each port is directly connected with a host and generally works in a full duplex mode. The software defined switching module can be communicated with a plurality of pairs of ports at the same time to transmit data without conflict. FIG. 1 is a block diagram of software defined switching modules.
The CPU unit configures the exchange unit formed by the SDI chip to realize various software definition exchanges, the exchange unit realizes network data exchange, the BMC unit implements health management on the CPU unit and the exchange unit, reports the health information of the two units to a user, and implements a health management strategy set by the user. The CPU unit and the switching unit communicate through a PCIE bus to realize software definition switching. The BMC is communicated with the CPU through a serial port to obtain working states of the CPU and the switching unit and the like, and is interconnected with sensors of the CPU and the switching unit through I2C to obtain corresponding health information.
The design of the CPU unit comprises: the method comprises the following steps of CPU model selection design, FLASH design, memory design, serial port design and debugging network port design. The CPU unit is mainly used for configuration management and software defined strategy of the exchange chip.
(1) CPU model selection design
The processor selects a CSP2020 which is an autonomous controllable domestic processor owned by 58 of China electronic department, has double e500 kernels, works at 800MHz master frequency, integrates three kilomega Ethernet controllers, two UARTs, two I2C and a 64bit DDR3 controller with ECC and enhanced LocalBus on a chip, has four 3.125GHz SerDes interfaces, and can be configured as PCIE, SRIO and SGMII as shown in figure 2:
(2) memory design
The memory clock frequency is more than or equal to 200MHz, the capacity is 2GB by adopting 4 DDR3 chips, the capacity is realized by selecting domestic SM41J256M16M, and the running of a CPU program is mainly completed.
(3) Flash design
Flash selects a chip S29GS01GP and a single chip of 128 MB. FLASH can store the starting code of CPU and the kernel of system. The Flash is hung on a Local Bus of the processor, and the address latch is realized through the address latch.
(4) Serial port design
The serial port is connected with the RS232 transceiver through the UART interface of the processor in a hanging way and then is output through the VPX connector, and the USB interface has the functions of debugging and configuration management.
(5) Debugging network interface design
The debugging network port is converted from SGMII of the CSP2020 processor to an MDI interface through PHY and connected with a VPX connector, and has the functions of network configuration management, software upgrading and software definition policy.
Designing a switching unit:
in order to meet the requirements of functional technical indexes of a software defined switching module for providing 4-path 2X RapidIO, 3-path 1X RapidIO, 6-path 1000BASE-X, 3-path FC and 6-path gigabit MDI switching ports and the like, the switching unit adopts an NMS3210 software chip to realize the design of a hardware circuit, and the functional performance indexes of the NMS3210 chip can meet the requirements of the software defined switching module. Meanwhile, the traditional mature high-speed circuit design and PCB high-speed signal design technology are used for reference, and simulation is carried out in the PCB design process, so that the quality of high-speed signals meets the design requirements, and the high-speed signals in the board are ensured not to have crosstalk. Meanwhile, the design and optimization of the exchange software are carried out to ensure that all functions and performances are complete and reach the technical index requirements. The functional performance indexes of the exchange chip are as follows:
the switching chip adopts an autonomous controllable domestic software definition chip NMS3210 developed by NDSC Tianjin center, the total switching capacity is 320Gbps, as shown in FIG. 3, which is a basic block diagram of NMS 3210.
NMS3210 consists of eight banks (numbered 0 through 7) each containing a 4-way channel (lane). For FC and Ethernet protocols, each channel is a port; for the RapidIO protocol, port widths support 1x, 2x and 4x modes. All ports are interconnected by an open switch fabric.
(1) Support 32-way high-speed serial SerDes lanes:
the channel supports multiple rates: 1.25, 2.125, 2.5, 3.125, 4.25, 5, 6.25, 8.5, and 10.3125 Gbaud;
(2) four protocols are supported: RapidIO3.1, FC-AE-ASM, 10G Base-KR, 1000 BASE-X;
(3) the RapidIO port supports three port binding modes: 1x, 2x, 4 x;
(4) a single exchange of four protocols is supported:
-support for 32-way FC-AE-ASM single protocol exchange (version 1.2);
-support 32-way 1000BASE-X single protocol exchanges;
-support for 32-way 10GBASE-KR single protocol exchange;
(5) support the mixed protocol exchange between the four protocols;
(6) switch Fabric employs a protocol-independent switching Fabric:
-320Gbps switching capability;
-support for non-blocking unicast and multicast switching;
(7) configuring a management interface: providing a configuration management channel of a chip for an external main control module:
-a PCIe interface: compatible PCI
2.0Base Specification (resolution 0.9), 1x mode;
-I2C interface:
(a) two modes of operation are supported: standard mode and fast mode (100KHz/400KHz)
(b) Supporting master and slave modes
(c) Support for automatically entering temporary host mode upon power-up and for entering command master mode by configuration register
-JTAG interface: conforming to the IEEE 1149.1 standard and the IEEE 1149.6 standard
BMC unit design:
the BMC unit is powered by 3.3V, the controller adopts A2F500, FIG. 4 is a basic block diagram of A2F500, and the basic block diagram of the BMC unit is provided with 500000System Gates, 11520Tiles, 24 4608bits RAM Blocks, 512Kbytes Flash, 64Kbytes SRAM, built-in Cortex-M3 processor with MPU and 10/100Ethernet MAC, 8-channel DMA, 2-way I2C, 2-way SPI, 2-way UART, 2-way 32bit timer, 2-way 12bit ADC, 2-way 24bit DAC and the like. The memory is 128MB, the memory adopts SPI Flash, provides one path of serial RS232 to the outside, and also provides 1 path of JTAG interface as the software upgrade and debug port of the module, the 1 path of RS485 health status is reported, the BMC is responsible for the health management of the whole module, and acquires and reports the exchange port status, the key chip temperature and the key voltage.
The above-described 4-way 2X RapidIO, 3-way 1X RapidIO, 6-way 1000BASE-X, 3-way FC, and 6-way gigabit MDI switch ports are only typical application scenarios for hybrid switching that does not require communication between three networks, SRIO, ethernet, and FC. The module serving as the software definition exchange module has the flexible network characteristic, can realize the exchange of various application scenes of single-protocol and multi-protocol networks, constructs a definable, reconfigurable and reconstructable software definition system structure, realizes the fusion and interconnection of heterogeneous networks, improves the interconnection efficiency, and reduces the reduction of performance and real-time performance during fusion.
NMS3210 is a protocol conversion programmable exchange chip supporting multiple protocols (RapidIO3.1, FC-AE-SAM, 10G Base-KR and 1000BASE-X), the protocol of each high-speed serial data interface can be defined into any one of the four protocols by software, and the four heterogeneous protocols can be interconnected and intercommunicated without blocking, with low time delay and high reliability. The NMS3210 supports a single protocol exchange mode and a mixed protocol exchange mode.
Each channel can be configured into a corresponding protocol type in a software defined mode according to the protocol type of the connected endpoint equipment, and after data enters the chip, whether protocol conversion is needed or not is judged according to the destination address of the data: if the protocol conversion is not needed, the network directly enters an internal non-blocking switching network; if necessary, the protocol conversion is completed and then the data enters the exchange network to be transmitted to the corresponding output port.
The CPU may access and configure the NMS3210 in a variety of ways, such as PCIE, I2C, and JTAG interfaces. When configured as a RapidIO port, the port supports the maintenance packet access functionality defined by the RapidIO protocol.
For a single network scenario, the NMS3210 may be configured as a single protocol switching chip, such as FC, SRIO, or Ethernet, and used as a single protocol switching module, as shown in fig. 5, 6, and 7:
(a) the NMS3210 software is defined as an FC switching chip for use and is connected to the existing FC switching network;
(b) for defining NMS3210 software as RapidIO exchange chip to use, connect to the existing RapidIO exchange network;
(c) to define the NMS3210 software as the Ethernet exchange chip, it is connected to the existing Ethernet exchange network.
The NMS3210 may be connected to endpoint devices or networks of multiple protocols, and may be generally divided into two types for heterogeneous network scenarios, where one type is a scenario where there is no communication requirement between networks of different protocols, that is, a scenario where there is no conversion of a mixed protocol, as shown in fig. 8, at this time, the NMS3210 chip is equivalent to replacing multiple different switch chips.
The NMS3210 is used for a mixed protocol network and when communication is required between endpoint devices of different protocols, an NMS3210 chip is required to implement a protocol conversion function and an exchange function, i.e., a mixed protocol conversion scenario. Fig. 9 is a schematic diagram of a hybrid protocol networking.
Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (8)
1. A software defined switching system based on a CPU and an SDI chip is characterized by comprising:
a CPU unit: configuring a switching unit formed by the SDI chip to realize various software definition switching;
a switching unit: realizing the exchange of network data;
BMC unit: implementing health management on the CPU unit and the switching unit, reporting the health information of the CPU unit and the switching unit, and implementing according to a set health management strategy;
the CPU unit and the switching unit communicate through a PCIE bus to realize software definition switching;
the BMC unit is communicated with the CPU unit through a serial port to obtain working states of the CPU unit and the switching unit, and the BMC unit is interconnected with sensors of the CPU unit and the switching unit through I2C to obtain corresponding health information.
2. The CPU and SDI chip based software defined switching system of claim 1 wherein the CPU unit comprises: the system comprises a CPU processor, a Flash plug-in, a memory, a serial port and a debugging network port;
the Flash plug-in is used for storing a starting code and a system kernel of the CPU, is hung on a CPU bus of the CPU processor and realizes address latching through the address latch;
the clock frequency of the memory is more than or equal to 200MHz, and a dynamic random access memory is selected to complete the running of a CPU program;
the serial port is hung on the transceiver through a UART interface of the CPU processor and then is output through the VPX connector;
the debugging network port is connected with the VPX connector by converting an SGMII interface of the CPU processor into an MDI interface through the PHY.
3. The CPU and SDI chip based software defined switching system of claim 1 wherein the switching unit comprises: all ports are interconnected by an open switch fabric.
4. The software defined switching system based on the CPU and the SDI chip according to claim 1, wherein the SDI chip comprises a plurality of channels, each channel configures the channel into a corresponding protocol type in a software defined manner according to the protocol type of the connected endpoint device, and after data enters the chip, determines whether protocol conversion is required according to its destination address: if the protocol conversion is not needed, the network directly enters an internal non-blocking switching network; if necessary, the protocol conversion is completed and then the data enters the exchange network to be transmitted to the corresponding output port.
5. The CPU and SDI chip based software defined switching system of claim 1 wherein the CPU unit accesses and configures the SDI chip via PCIE, I2C and JTAG interfaces.
6. The CPU and SDI chip based software defined switching system of claim 1 wherein the SDI chip is defined for use as an FC switch chip, connected to an existing FC switch network;
defining the SDI chip as a RapidIO exchange chip for use, and connecting the SDI chip to the existing RapidIO exchange network;
the SDI chip is defined as an Ethernet exchange chip for use and is connected to an existing Ethernet exchange network;
when configured for use with a RapidIO switch chip, supporting the RapidIO protocol defined maintenance packet access functionality.
7. The software defined switching system based on the CPU and the SDI chip of claim 1, wherein the SDI chip is connected to endpoint devices or networks of multiple protocols, and for heterogeneous network scenarios:
-when there is no transition scenario for the hybrid protocol, the SDI chip replaces multiple different switch chips;
and when the mixed protocol is converted, the SDI chip is connected with each protocol to carry out protocol conversion and exchange.
8. A software definition switching method based on a CPU and an SDI chip, which is characterized in that the software definition switching system based on the CPU and the SDI chip of any one of claims 1 to 7 is adopted, and comprises:
step 1: determining a protocol type, a port mode and a port rate;
step 2: configuring an interface according to requirements through a serial port or a network port of the CPU;
and step 3: configuring a required protocol, port rate and port mode through application software running on an operating system;
and 4, step 4: and after receiving the configuration command, the CPU configures a corresponding register of the SDI chip through the PCIE bus, completes corresponding configuration and stores the configuration.
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