CN112379617B - Anti-interlocking circuit for preventing channel of fault-tolerant system from being locked and redundancy fault-tolerant system - Google Patents

Anti-interlocking circuit for preventing channel of fault-tolerant system from being locked and redundancy fault-tolerant system Download PDF

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CN112379617B
CN112379617B CN202011226852.4A CN202011226852A CN112379617B CN 112379617 B CN112379617 B CN 112379617B CN 202011226852 A CN202011226852 A CN 202011226852A CN 112379617 B CN112379617 B CN 112379617B
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resistor
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CN112379617A (en
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安书董
郑久寿
李亚锋
康晓东
李明
白晨
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Xian Aeronautics Computing Technique Research Institute of AVIC
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0421—Multiprocessor system
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/24—Pc safety
    • G05B2219/24182—Redundancy

Abstract

The invention discloses an anti-interlocking circuit for preventing a fault-tolerant system channel from being locked and a redundancy fault-tolerant system, wherein the anti-interlocking circuit comprises: a monitoring result decision sub-circuit, a delay sub-circuit and an anti-noise sub-circuit. The circuit design carries out three-layer processing of judgment, time delay and noise resistance on the effective signal of the power supply; in the judging part, the monitoring result is judged through a comparison circuit; in the time delay part, the purpose of signal delay is achieved by charging the capacitor, and the influence of other channels on the channel is eliminated; in the anti-noise part, through the design of a hysteresis circuit, noise interference is inhibited, false overturning caused by level jitter is effectively prevented, and finally processed signals are introduced into channel fault logic, so that a system can correctly acquire the working state of each channel so as to switch and close the channels. The phenomenon of locking among channels caused by asynchrony among channels, power characteristic difference and the like in the conventional fault-tolerant system is solved.

Description

Anti-interlocking circuit for preventing channel of fault-tolerant system from being locked and redundancy fault-tolerant system
Technical Field
The invention relates to the technical field of design of an on-board computer of a fault-tolerant system, in particular to an anti-interlocking circuit and a redundancy fault-tolerant system which have high reliability and high stability and can prevent a fault-tolerant system channel from being locked.
Background
The fault tolerant system is used as a key technology for the reliability design of an on-board computer and is widely applied to the field of aerospace. In the design of a redundancy fault-tolerant system, each redundancy, namely each channel has independent communication capacity, and the system manages the state of each channel according to different control strategies. A monitoring circuit is introduced, and aims to realize the positioning, isolation and channel switching of the fault after the fault is found.
In practical application, it is found that due to the reasons of asynchrony between channels and differences in power supply characteristics, when a signal monitored by one channel is not completely valid, the channel outputs a fault state and informs the other channel, so that the other channel finally outputs the fault state and the channels are locked with each other, thereby seriously affecting the reliability and stability of the fault-tolerant system.
Disclosure of Invention
The purpose of the invention is:
the embodiment of the invention provides an anti-interlocking circuit for preventing channels of a fault-tolerant system from being locked and a redundancy fault-tolerant system, which aim to solve the problem of locking among the channels caused by the reasons of asynchrony among the channels, power supply characteristic difference and the like in the conventional fault-tolerant system.
The technical scheme of the invention is as follows:
the embodiment of the invention provides an anti-interlocking circuit for preventing locking between channels of a redundancy fault-tolerant system, which is characterized by comprising the following steps: a monitoring result decision sub-circuit, a delay sub-circuit and an anti-noise sub-circuit;
the monitoring result judging sub-circuit comprises a signal synthesis module and a first comparator, wherein the signal synthesis module is used for performing synthesis judgment on a plurality of paths of monitoring signals input by the monitoring module and then outputting a judgment signal to the first comparator, so that the first comparator outputs a judgment result according to a reference source and the input judgment signal;
and the delay sub-circuit is used for carrying out delay processing on the judgment result output by the first comparator so as to output a delay judgment signal to the anti-noise sub-circuit.
Optionally, in the interlock prevention circuit for preventing deadlock between channels of the redundancy fault tolerant system as described above, the interlock prevention circuit further includes: a reference source for the first comparator, comprising: a third resistor R3 and a fourth resistor R4 which are connected in series, wherein the third resistor R3 is connected to a reference source, and the fourth resistor R4 is grounded.
Optionally, in the interlock prevention circuit for preventing deadlock among channels of a redundancy fault tolerant system as described above, the delay sub-circuit includes: a first resistor R1 connected with the output end of the first comparator, and a first capacitor C1 and a second resistor R2 connected to the other end of the first resistor R1, the other end of the second resistor R2 is connected to the reference source, and the other end of the first capacitor C1 is grounded.
Alternatively, in the interlock prevention circuit for preventing the deadlock between the channels of the redundancy fault-tolerant system as described above,
the delay time of the delay sub-circuit to the decision signal is:
Figure GDA0003241789890000021
wherein, Tr is the delay time from the decision signal to the delayed decision signal;
voh is the maximum voltage value that the first capacitor C1 can charge;
vol is the initial voltage value on the first capacitor C1;
Vt+to delay the flipped voltage value of the decision signal.
Optionally, in the interlock prevention circuit for preventing deadlock between channels of a redundancy fault tolerant system as described above, the anti-noise sub-circuit is a reverse hysteresis comparison circuit, and includes: a fifth resistor R5, a second comparator and a feedback resistor R6;
one end of a fifth resistor R5 is connected between the third resistor R3 and the fourth resistor R4, the other end is connected to the positive input end of the second comparator and one end of a feedback resistor R6, the reverse input end of the second comparator is connected to the other end of the first resistor R1, and the other end of the feedback resistor R6 is connected to the output end of the second comparator.
Optionally, in the anti-interlock circuit for preventing deadlock between channels of a redundancy fault tolerant system as described above, an output of the anti-noise sub-circuit includes a power supply delay decision signal PSV _ DLY, and the anti-interlock circuit further includes: a channel failure logic module;
and the channel fault logic module is used for outputting an effective signal LCHV of the channel finally according to a power supply effective signal PSV and a power supply delay judgment signal PSV _ DL which are input by the channel, a watchdog monitoring signal WDV, a self-monitoring signal CPUV of the channel and an effective signal CHV _ FX of the other channel.
An embodiment of the present invention further provides an interlocking redundancy prevention fault-tolerant system, including: two channels, each channel having an anti-interlock circuit provided therein for preventing deadlock between channels of a redundancy fault tolerant system as claimed in any one of claims 1 to 6;
the anti-interlocking circuit in each channel is used for outputting an effective signal LCHV of the channel finally according to a power supply effective signal PSV, a power supply delay judgment signal PSV _ DL, a watchdog monitoring signal WDV, a self-monitoring signal CPUV of the channel and an effective signal CHV _ FX of the other channel which are input by the channel; wherein the other channel valid signal CHV _ FX is output by the anti-interlock circuit in the other channel.
Optionally, in the above-described interlock-prevention redundancy fault-tolerant system, each channel further includes: a channel fault logic reset module;
and the channel fault logic reset module is used for resetting the output valid signal LCHV of the channel according to the input power supply delay judgment signal PSV _ DL or the channel fault logic reset signal CFL _ RES.
The invention has the advantages that:
the anti-interlocking circuit and the redundancy fault-tolerant system for preventing the channel of the fault-tolerant system from being locked provided by the embodiment of the invention have the following advantages:
1. the invention realizes three-stage processing of the state indication signal in terms of functions, introduces the final result into the channel fault logic and obtains the state of each channel from hardware.
2. The invention introduces a certain time delay logically, transmits the delayed indication signal among the redundancies, ensures that the system correctly obtains the working state of each channel and avoids the locking among the channels.
3. According to the invention, a hysteresis comparison circuit is introduced in the circuit structure, so that the error turnover caused by level jitter can be effectively prevented, and the system stability is improved.
4. In the design, the programmable logic is adopted to design the channel fault logic, and the fault is latched, so that the system reliability is improved.
By adopting the anti-interlocking circuit and the redundancy fault-tolerant system for preventing the channel of the fault-tolerant system from being locked, firstly, the channel interlocking phenomenon possibly existing under the condition that the channels are asynchronous or the power supply characteristics are different can be effectively eliminated; secondly, by the design of the delay hysteresis circuit, the error turnover caused by level jitter can be effectively prevented, and the normal work of the circuit is protected; and thirdly, the monitoring signals are processed by combining hardware design with channel fault logic, and the logic is independent from other interface modules of the system so as to improve the portability of the design.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a block diagram of a channel fault logic in an anti-interlock redundancy fault-tolerant system according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an interlock prevention circuit for preventing deadlock among channels of a redundancy fault-tolerant system according to an embodiment of the present invention;
fig. 3 is a schematic waveform diagram of an output processed by the anti-interlock circuit for preventing deadlock between channels of the fault-tolerant system according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The embodiment of the invention provides an anti-interlocking circuit and a redundancy fault-tolerant system for preventing a channel of a fault-tolerant system from being locked, wherein the anti-interlocking circuit and the redundancy fault-tolerant system have high reliability and high stability; in addition, the method is used for processing the monitoring result by designing a special channel fault logic independent of other hardware.
The following specific embodiments of the present invention may be combined, and the same or similar concepts or processes may not be described in detail in some embodiments.
The channel fault logic is mainly used for synthesizing effective information of each channel monitoring signal into a TTL level signal and transmitting the TTL level signal to another channel to inform whether the channel is effective or not so as to facilitate switching and closing of a system. Due to the difference of the power supply characteristics of the channels, when the power supply monitoring signal of one channel is not effective, the output final indication signal is in a fault state, so that the other channel is influenced to output the fault state, and the channels are locked mutually.
The anti-interlocking circuit and the redundancy fault-tolerant system for preventing the channel of the fault-tolerant system from being locked provided by the embodiment of the invention are based on the optimized improved design on the redundancy fault-tolerant system. Through the circuit design of the embodiment of the invention, the power supply monitoring signal PSV is subjected to three layers of processing of judgment, delay and noise resistance, and the power-on initial state fault caused by the characteristic difference of each power supply can be effectively avoided by combining the channel fault logic, so that the locking between channels is prevented, and the reliability and the stability of the system are improved.
Fig. 1 is a schematic diagram of a channel fault logic in an interlock-proof redundancy fault-tolerant system according to an embodiment of the present invention. Referring to fig. 1, the architecture of the fault tolerant system channel fault logic will be described in detail. The input sources of the channel fault logic mainly comprise: a power supply valid signal (PSV), a watchdog monitor signal (WDV), a present channel self-monitor signal (CPUV), and another channel valid signal (CHV _ FX), and a final output signal of the channel fault logic is the present channel valid signal (LCHV). When any input source of the input monitoring signals fails, the LCHV finally outputs the channel failure. Because of the difference of power supply characteristics of the channels or the asynchronous communication among the channels, in the power-on initial state, when the power supply of one channel is not valid, the input CHV _ FX is in a fault state for the other channel, so that the other channel finally outputs the fault state, and the channels are locked mutually.
Fig. 2 is a schematic structural diagram of an interlock prevention circuit for preventing deadlock between channels of a redundancy fault-tolerant system according to an embodiment of the present invention. As shown in fig. 2, the interlock prevention circuit includes: a monitoring result decision sub-circuit, a delay sub-circuit and an anti-noise sub-circuit.
The monitoring result judging sub-circuit comprises a signal synthesis module and a first comparator, wherein the signal synthesis module is used for performing synthesis judgment on a plurality of paths of monitoring signals input by the monitoring module and then outputting a judgment signal to the first comparator, so that the first comparator outputs a judgment result according to a reference source and the input judgment signal; in practical application of the embodiment of the invention, the signal synthesis module is, for example, an and gate.
And the delay sub-circuit is used for carrying out delay processing on the judgment result output by the first comparator so as to output a delay judgment signal to the anti-noise sub-circuit.
The interlock prevention circuit provided by the embodiment of the invention can further comprise: a reference source of the first comparator, the reference source specifically comprising: a third resistor R3 and a fourth resistor R4 which are connected in series, wherein the third resistor R3 is connected to a reference source, and the fourth resistor R4 is grounded.
As shown in fig. 2, the delay sub-circuit in the embodiment of the present invention may include: a first resistor R1 connected with the output end of the first comparator, and a first capacitor C1 and a second resistor R2 connected to the other end of the first resistor R1, the other end of the second resistor R2 is connected to the reference source, and the other end of the first capacitor C1 is grounded.
In a specific implementation manner of the embodiment of the present invention, the anti-noise sub-circuit may be configured as a reverse hysteresis comparison circuit, and specifically includes: a fifth resistor R5, a second comparator and a feedback resistor R6.
One end of the fifth resistor R5 is connected between the third resistor R3 and the fourth resistor R4, the other end is connected to the positive input end of the second comparator and one end of the feedback resistor R6, the negative input end of the second comparator is connected to the other end of the first resistor R1, and the other end of the feedback resistor R6 is connected to the output end of the second comparator.
It should be noted that the output signal of the interlock prevention circuit including the monitoring result decision sub-circuit, the delay sub-circuit and the anti-noise sub-circuit is the power supply delay decision signal PSV _ DLY.
Optionally, the interlock prevention circuit provided in the embodiment of the present invention further includes: a channel failure logic module.
The channel fault logic module in the embodiment of the invention is used for outputting the valid signal LCHV of the channel finally according to the power supply valid signal PSV and the power supply delay decision signal PSV _ DL input by the channel, the watchdog monitoring signal WDV, the self-monitoring signal CPUV of the channel and the other channel valid signal CHV _ FX.
The following embodiment takes a failure of a PSV signal as an example, and illustrates a manner in which the embodiment of the present invention optimizes the PSV signal in each channel input source, and a circuit structure of the interlock prevention circuit is shown in fig. 2. Firstly, a PSV signal is judged by a monitoring result judging sub-circuit, the state of the PSV is judged by a first comparator, the PSV is '0' to indicate power failure, and '1' to indicate that the power is effective; secondly, the delay sub-circuit performs a delay process according to the decision result of the PSV, specifically, when the PSV is high, the PSV is delayed by charging a capacitor in the delay sub-circuit, and the fault tolerant system finally outputs a PSV _ DLY signal, wherein a specific delay time Tr of the delay sub-circuit is determined by parameters of an RC circuit (i.e., the first resistor R1 and the first capacitor C1), and the delay time Tr is given by the following formula:
Figure GDA0003241789890000051
wherein:
tr is the delay time from the decision signal to the delayed decision signal;
voh is the voltage value that the first capacitor C1 can eventually reach;
vol is the initial voltage value on the first capacitor C1;
Vt+is the reversed voltage value of PSV _ DLY.
Fig. 3 is a schematic waveform diagram of an output processed by the anti-interlock circuit for preventing deadlock between channels of the fault tolerant system according to the embodiment of the present invention, in which waveforms of signals PSV and PSV _ DLY are illustrated. As shown in fig. 3, PSV is the upper waveform in fig. 3, and PSV _ DLY is the lower waveform in fig. 3.
In practice, a delay is required when PSV is high or low, but if PSV is high, PSV _ DLY is in an active state, and if PSV is low, PSV _ DLY is in an inactive state, and LCHV, which is the final output of the interlock prevention circuit, is in an inactive state.
The delayed monitoring result is accessed into the anti-noise circuit, so that the signal can effectively prevent the fault-tolerant system from mistakenly overturning due to level jitter, and the circuit is protected from working normally.
The channel fault logic module provided by the embodiment of the invention integrates PSV, WDV, CPUV and LCHV, simultaneously introduces PSV _ DLY signals, and enables the system to output LCHV to represent the state of the channel after the power-on is stable through logic judgment, thereby effectively eliminating the locking among the channels and improving the stability and reliability of the system.
Based on the anti-interlock circuit for preventing deadlock among channels of the redundancy fault-tolerant system provided by the above embodiment of the present invention, an embodiment of the present invention also provides an anti-interlock redundancy fault-tolerant system, which includes: two channels, each provided with an anti-interlock circuit for preventing deadlock between channels of the redundancy fault-tolerant system as in any of the embodiments. It should be noted that the interlock prevention circuit (such as the circuit shown in fig. 1 and 2) according to the above embodiment of the present invention is only one channel in the interlock prevention redundancy fault tolerant system.
The anti-interlocking circuit in each channel in the embodiment of the invention is used for outputting the effective signal LCHV of the channel finally according to the effective power supply signal PSV, the delayed power supply decision signal PSV _ DL, the watchdog monitoring signal WDV, the self-monitoring signal CPUV of the channel and the effective signal CHV _ FX of the other channel which are input by the channel; wherein the other channel valid signal CHV _ FX is output by the anti-interlock circuit in the other channel.
Further, each channel of the interlock prevention redundancy fault-tolerant system according to the embodiment of the present invention further includes: and a channel fault logic reset module.
The channel fault logic reset module is used for resetting the output valid signal LCHV of the channel according to the input power supply delay decision signal PSV _ DL or the channel fault logic reset signal CFL _ RES.
The method is mainly applied to management among the channels of the redundancy fault-tolerant system, and solves the problem of mutual locking among the channels caused by the power supply characteristic difference of each channel and the like. The circuit design processes three layers of judgment, time delay and noise resistance on the effective signal of the power supply. In the judging part, the monitoring result is judged through a comparison circuit; in the time delay part, the purpose of signal delay is achieved by charging the capacitor, and the influence of other channels on the channel is eliminated; in the anti-noise part, through the design of a hysteresis circuit, noise interference is inhibited, false overturning caused by level jitter is effectively prevented, and finally processed signals are introduced into channel fault logic, so that a system can correctly acquire the working state of each channel so as to switch and close the channels.
The invention is characterized in that the occurrence of the locking phenomenon among the channels of the redundancy fault-tolerant system can be effectively eliminated, and the channel error switching is avoided when the redundancy system is managed. The circuit is simple in design, high in stability and strong in transportability, and reliability and stability of management among channels of the redundancy fault-tolerant system are enhanced.
The embodiment of the invention provides an anti-interlocking circuit for preventing locking between channels of a redundancy fault-tolerant system and the redundancy fault-tolerant system, and particularly relates to an optimized improved design based on the redundancy fault-tolerant system. Through the circuit design of the embodiment of the invention, the power supply monitoring signal PSV is subjected to three layers of processing of judgment, delay and noise resistance, and the power-on initial state fault caused by the characteristic difference of each power supply can be effectively avoided by combining the channel fault logic, so that the locking between channels is prevented, and the reliability and the stability of the system are improved.
Wherein, the implementation stage of signal processing:
the first stage, through the comparison circuit, judge the working condition of the system;
in the second stage, the judged state indicating signals are delayed through a charging circuit, so that the inconsistency of characteristics among channels is avoided;
and in the third stage, noise resistance processing is carried out on the state indication signal through a hysteresis circuit.
The implementation method of the channel fault logic comprises the following steps:
the latch (RS) latching function is implemented by programmable logic, which latches the state in the event of a failure. Only upon reset can the fault be cleared.
The anti-interlocking circuit and the redundancy fault-tolerant system for preventing the channel of the fault-tolerant system from being locked, provided by the embodiment of the invention, realize three-stage processing of the state indication signal functionally, introduce the final result into channel fault logic and obtain the state of each channel from hardware; logically, a delay of a certain time is introduced, and the delayed indication signals are transmitted among redundancies, so that the system is ensured to correctly obtain the working state of each channel, and the locking among the channels is avoided; in the circuit structure, a hysteresis comparison circuit is introduced, so that the error turnover caused by level jitter can be effectively prevented, and the system stability is improved; in design, programmable logic is adopted to design channel fault logic, and faults are latched, so that the reliability of the system is improved. By adopting the anti-interlocking circuit and the redundancy fault-tolerant system for preventing the channel of the fault-tolerant system from being locked, firstly, the channel interlocking phenomenon possibly existing under the condition that the channels are asynchronous or the power supply characteristics are different can be effectively eliminated; secondly, by the design of the delay hysteresis circuit, the error turnover caused by level jitter can be effectively prevented, and the normal work of the circuit is protected; and thirdly, the monitoring signals are processed by combining hardware design with channel fault logic, and the logic is independent from other interface modules of the system so as to improve the portability of the design.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (6)

1. An interlock prevention circuit for preventing deadlock between channels of a redundancy fault tolerant system, comprising: a monitoring result decision sub-circuit, a delay sub-circuit and an anti-noise sub-circuit;
the monitoring result judging sub-circuit comprises a signal synthesis module and a first comparator, wherein the signal synthesis module is used for performing synthesis judgment on a plurality of paths of monitoring signals input by the monitoring module and then outputting a judgment signal to the first comparator, so that the first comparator outputs a judgment result according to a reference source and the input judgment signal;
the delay sub-circuit is used for carrying out delay processing on the judgment result output by the first comparator so as to output a delay judgment signal to the anti-noise sub-circuit;
wherein the delay sub-circuit comprises: a first resistor R1 connected with the output end of the first comparator, and a first capacitor C1 and a second resistor R2 connected to the other end of the first resistor R1, wherein the other end of the second resistor R2 is connected to a reference source, and the other end of the first capacitor C1 is grounded;
the delay time of the delay sub-circuit to the decision signal is:
Figure FDA0003357269250000011
wherein, Tr is the delay time from the decision signal to the delayed decision signal;
voh is the maximum voltage value that the first capacitor C1 can charge;
vol is the initial voltage value on the first capacitor C1;
Vt+to delay the flipped voltage value of the decision signal.
2. The anti-interlock circuit for preventing deadlock between channels of a redundancy fault tolerant system according to claim 1, further comprising: a reference source for the first comparator, comprising: a third resistor R3 and a fourth resistor R4 which are connected in series, wherein the third resistor R3 is connected to a reference source, and the fourth resistor R4 is grounded.
3. The anti-lock circuit for preventing deadlock among channels of a redundancy fault-tolerant system according to claim 2, wherein the anti-noise sub-circuit is an inverse hysteresis comparison circuit, comprising: a fifth resistor R5, a second comparator and a feedback resistor R6;
one end of a fifth resistor R5 is connected between the third resistor R3 and the fourth resistor R4, the other end is connected to the positive input end of the second comparator and one end of a feedback resistor R6, the reverse input end of the second comparator is connected to the other end of the first resistor R1, and the other end of the feedback resistor R6 is connected to the output end of the second comparator.
4. The anti-interlock circuit for preventing channel-to-channel lock-up in a redundancy fault tolerant system according to any one of claims 1 to 3, wherein the output of the anti-noise sub-circuit comprises a power supply delay decision signal PSV DLY, and the anti-interlock circuit further comprises: a channel failure logic module;
and the channel fault logic module is used for outputting an effective signal LCHV of the channel finally according to a power supply effective signal PSV and a power supply delay judgment signal PSV _ DL which are input by the channel, a watchdog monitoring signal WDV, a self-monitoring signal CPUV of the channel and an effective signal CHV _ FX of the other channel.
5. An interlocking redundancy prevention fault tolerant system, comprising: two channels, each channel having an anti-interlock circuit provided therein for preventing deadlock between channels of a redundancy fault tolerant system as claimed in any one of claims 1 to 4;
the anti-interlocking circuit in each channel is used for outputting an effective signal LCHV of the channel finally according to a power supply effective signal PSV, a power supply delay judgment signal PSV _ DL, a watchdog monitoring signal WDV, a self-monitoring signal CPUV of the channel and an effective signal CHV _ FX of the other channel which are input by the channel; wherein the other channel valid signal CHV _ FX is output by the anti-interlock circuit in the other channel.
6. The interlock avoidance redundancy fault tolerant system of claim 5 further comprising in each channel: a channel fault logic reset module;
and the channel fault logic reset module is used for resetting the output valid signal LCHV of the channel according to the input power supply delay judgment signal PSV _ DL or the channel fault logic reset signal CFL _ RES.
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