CN112347033A - Multi-unit server implementation method based on VPX architecture - Google Patents
Multi-unit server implementation method based on VPX architecture Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7803—System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
Abstract
The invention discloses a multi-unit server implementation method based on a VPX architecture, which relates to the technical field of computers, and is based on the VPX architecture and comprises a computing unit, an exchange unit, a switching and management unit and a power supply unit; wherein: the computing unit is integrated with a processor, a memory and a network controller, has network communication capacity and is used for data computing and network communication requirements; the exchange unit provides a data transmission link for the calculation unit to realize data exchange; the switching and management unit realizes sharing of the VGA + USB interface and monitors and manages the computing unit, the switching unit and the power supply unit; the power supply unit provides power supply support for the operation of the multi-unit server; the computing unit, the switching unit, the power supply unit and the switching and managing unit are respectively connected with a back plate of the multi-unit server through a VPX bus. The invention can avoid single point of failure and improve the reliability and the availability of the system.
Description
Technical Field
The invention relates to the technical field of servers, in particular to a multi-unit server implementation method based on a VPX framework.
Background
With the increasing requirements of the industry on the transmission bandwidth of the bus technology, the conventional bus architecture gradually shows disadvantages, and the VPX bus comes into being.
The VPX bus is a new generation of high-speed serial bus standard developed by VITA in 2007, which introduces the latest serial bus technologies at present, such as: RapidlO, PCIe, and gigabit ethernet, among others, support higher backplane bandwidth. Each pair of differential pairs can theoretically provide 10Gbps of data exchange capability, and the data throughput capability is strong.
Based on the method, a multi-unit server implementation method based on a VPX framework is designed and developed to realize data exchange, avoid single-point faults and improve the reliability and the availability of the system.
Disclosure of Invention
Aiming at the requirements and the defects of the prior art development, the invention provides a multi-unit server implementation method based on a VPX framework.
The invention discloses a multi-unit server implementation method based on VPX architecture, which adopts the following technical scheme for solving the technical problems:
a multi-unit server implementation method based on VPX architecture is based on VPX architecture and comprises a computing unit, an exchange unit, a switching and management unit and a power supply unit;
the computing unit is integrated with a processor, a memory and a network controller, has network communication capacity and is used for data computing and network communication requirements;
the exchange unit provides a data transmission link for the calculation unit to realize data exchange;
the switching and management unit realizes sharing of the VGA + USB interface and monitors and manages the computing unit, the switching unit and the power supply unit;
the power supply unit provides power supply support for the operation of the multi-unit server;
the computing unit, the switching unit, the power supply unit and the switching and managing unit are respectively connected with a back plate of the multi-unit server through a VPX bus.
Optionally, there are multiple computing units, and the multiple computing units are physically and logically independent of each other.
Preferably, the number of the computing units connected with the multi-unit server backplane through the VPX bus is not more than 4.
Preferably, the number of the switching units connected with the multi-unit server backplane through the VPX bus is not more than 2.
Preferably, the number of the switching and management units connected to the multi-unit server backplane through the VPX bus is 1.
Preferably, the number of power supply units connected to the back plane of the multi-unit server through the VPX bus is 4.
Optionally, the processors are Intel Xeon E52600 series v4 processors, so as to provide high-performance processing capability for the computing motherboard;
the processor adopts DIMM memory to carry out mainboard design, the mainboard provides 4 DDR4 DIMM memory slots, the maximum capacity of a single DDR4 DIMM memory is 64GB, and the maximum support of the single mainboard memory can be extended to 256 GB; 2 groups of gigabit networks and 2 groups of gigabit networks are externally led out of the main board, and data transmission links among a plurality of computing units are constructed through the switching units to realize data transmission.
Further optionally, when the related main board externally leads out 2 groups of tera networks, the control chip of the tera network adopts an Intel 82599ES chip, and the 1-path PCIE × 8 signal connection 82599ES chip of the processor collectively outputs 2 tera interfaces, so as to provide sufficient network bandwidth for the plurality of computing units.
Further optionally, when the related motherboard externally leads out 2 groups of gigabit networks, the control chip of the gigabit network uses an Intel I350 chip, at this time, the PCIE × 4 signal of the matched bridge C612 is used to connect the control chip Intel I350 of the gigabit network and convert out 2 channels of gigabit interfaces, and the USB2.0 and SATA3.0 interfaces are extended, one channel of PCIE × 1 signal and LPC signal of the bridge C612 are connected to the BMC management chip AST2400 of the motherboard, so that the state management of the motherboard is realized, and the operating state of the motherboard is monitored through the I2C bus.
Further optionally, an RGMII port of the BMC management chip AST2400 on the motherboard is connected to a transceiver of a gigabit network, and a gigabit network port of an RJ45 interface is externally led out to implement network management on the motherboard;
VGA signals of the BMC management chip AST2400 on the mainboard are led out externally and transmitted to the switching and management unit through the VPX bus of the backboard, and sharing of the VGA + USB interface is achieved.
Compared with the prior art, the multi-unit server implementation method based on the VPX architecture has the following beneficial effects:
1) the invention realizes data calculation and network communication through the calculation unit, realizes data exchange through the exchange unit, realizes sharing of a VGA + USB interface through the switching and management unit, and monitors and manages a plurality of calculation modules, network exchange modules and power supply modules, and has good high-performance calculation capacity, large-capacity data storage capacity and high-bandwidth communication capacity;
2) the multi-unit server is based on a VPX architecture, integrates calculation, exchange and management, can elastically expand the calculation scale, meets the application requirements of different spaces and scales, and has intelligent unified management.
Drawings
FIG. 1 is a block diagram of an implementation architecture of the present invention;
FIG. 2 is a block diagram showing the detailed connections of the computing unit, the switching and managing unit, and the power supply unit according to the present invention;
fig. 3 is an architecture diagram of a computing unit in the present invention.
Detailed Description
In order to make the technical scheme, the technical problems to be solved and the technical effects of the present invention more clearly apparent, the following technical scheme of the present invention is clearly and completely described with reference to the specific embodiments.
The first embodiment is as follows:
with reference to fig. 1, 2, and 3, this embodiment provides a method for implementing a multi-element server based on a VPX architecture, where the method is based on the VPX architecture and includes a computing unit, a switching and managing unit, and a power supply unit.
The number of the computing units is 4, and the 4 computing units are physically and logically independent from each other. Each computing unit is integrated with a processor, a memory and a network controller, has network communication capacity and is used for data computing and network communication requirements. The Intel Xeon E52600 series v4 processor is selected as the processor, and high-performance processing capacity is provided for the computing mainboard.
The number of the switching units is 2, and the switching units provide data transmission links for the computing units to realize data exchange.
The number of the switching and management units is 1, the switching and management units share VGA + USB interfaces, and monitor and manage the computing unit, the switching unit and the power supply unit.
There are 4 power supply units, and 4 power supply units provide power supply support for the operation of the multi-unit server.
4 computing units, 2 switching units, 4 power supply units and 1 switching and management unit are respectively connected with the back plate of the multi-unit server through a VPX bus.
In the embodiment, the processor adopts a DIMM memory to design the main board, the main board provides 4 DDR4 DIMM memory slots, the maximum capacity of a single DDR4 DIMM memory is 64GB, and the maximum support of the single main board memory can be extended to 256 GB; 2 groups of gigabit networks and 2 groups of gigabit networks are externally led out of the main board, and data transmission links among a plurality of computing units are constructed through the switching units to realize data transmission.
When 2 groups of gigabit networks are externally led out of the main board, the control chip of the gigabit network adopts an Intel 82599ES chip, and 2 gigabit interfaces are jointly converted by 1 path of PCIE multiplied by 8 signal connection 82599ES chip of the processor, so that sufficient network bandwidth is provided for a plurality of computing units.
When the mainboard is externally led out of 2 groups of gigabit networks, the control chip of the gigabit network adopts an Intel I350 chip, at the moment, the PCIE x 4 signal of the matched bridge chip C612 is connected with the control chip Intel I350 of the gigabit network to convert out 2 paths of gigabit interfaces, the USB2.0 and SATA3.0 interfaces are expanded, one path of PCIE x 1 signal and LPC signal of the bridge chip C612 are connected with the BMC management chip AST2400 of the mainboard, the state management of the mainboard is realized, and the working state of the mainboard is monitored through an I2C bus.
In this embodiment, an RGMII port of the AST2400 based on a BMC management chip on the motherboard is connected to a transceiver of a gigabit network, and a gigabit network port of an RJ45 interface is externally led out to implement network management on the motherboard;
VGA signals of the BMC management chip AST2400 on the mainboard are led out externally and transmitted to the switching and management unit through the VPX bus of the backboard, and sharing of the VGA + USB interface is achieved.
Example two:
referring to fig. 1, 2, and 3, the present embodiment provides a method for implementing a multi-element server based on a VPX architecture, where the method is based on the VPX architecture and includes a computing unit, a switching and managing unit, and a power supply unit.
In this embodiment, there is one computing unit, one switching and managing unit, and one power supply unit.
The computing unit is integrated with a processor, a memory and a network controller, has network communication capacity and is used for data computing and network communication requirements. The Intel Xeon E52600 series v4 processor is selected as the processor, and high-performance processing capacity is provided for the computing mainboard.
The exchange unit provides a data transmission link for the calculation unit to realize data exchange.
The switching and management unit realizes sharing of the VGA + USB interface and monitors and manages the computing unit, the switching unit and the power supply unit.
The power supply unit provides power supply support for the operation of the multi-unit server.
The computing unit, the switching unit, the power supply unit and the switching and managing unit are respectively connected with a back plate of the multi-unit server through a VPX bus.
In the embodiment, the processor adopts a DIMM memory to design the main board, the main board provides 4 DDR4 DIMM memory slots, the maximum capacity of a single DDR4 DIMM memory is 64GB, and the maximum support of the single main board memory can be extended to 256 GB; 2 groups of gigabit networks and 2 groups of gigabit networks are externally led out of the main board, and data transmission links among a plurality of computing units are constructed through the switching units to realize data transmission.
When 2 groups of gigabit networks are externally led out of the main board, the control chip of the gigabit network adopts an Intel 82599ES chip, and 2 gigabit interfaces are jointly converted by 1 path of PCIE multiplied by 8 signal connection 82599ES chip of the processor, so that sufficient network bandwidth is provided for a plurality of computing units.
When the mainboard is externally led out of 2 groups of gigabit networks, the control chip of the gigabit network adopts an Intel I350 chip, at the moment, the PCIE x 4 signal of the matched bridge chip C612 is connected with the control chip Intel I350 of the gigabit network to convert out 2 paths of gigabit interfaces, the USB2.0 and SATA3.0 interfaces are expanded, one path of PCIE x 1 signal and LPC signal of the bridge chip C612 are connected with the BMC management chip AST2400 of the mainboard, the state management of the mainboard is realized, and the working state of the mainboard is monitored through an I2C bus.
In this embodiment, an RGMII port of the AST2400 based on a BMC management chip on the motherboard is connected to a transceiver of a gigabit network, and a gigabit network port of an RJ45 interface is externally led out to implement network management on the motherboard;
VGA signals of the BMC management chip AST2400 on the mainboard are led out externally and transmitted to the switching and management unit through the VPX bus of the backboard, and sharing of the VGA + USB interface is achieved.
In summary, the multi-unit server implementation method based on the VPX framework of the present invention can implement data exchange, avoid single point of failure, and improve the reliability and availability of the system.
The principles and embodiments of the present invention have been described in detail using specific examples, which are provided only to aid in understanding the core technical content of the present invention. Based on the above embodiments of the present invention, those skilled in the art should make any improvements and modifications to the present invention without departing from the principle of the present invention, and therefore, the present invention should fall into the protection scope of the present invention.
Claims (10)
1. A multi-unit server implementation method based on VPX architecture is characterized in that the method is based on VPX architecture and comprises a computing unit, an exchange unit, a switching and management unit and a power supply unit;
the computing unit is integrated with a processor, a memory and a network controller, has network communication capacity and is used for data computing and network communication requirements;
the exchange unit provides a data transmission link for the calculation unit to realize data exchange;
the switching and management unit realizes sharing of the VGA + USB interface and monitors and manages the computing unit, the switching unit and the power supply unit;
the power supply unit provides power supply support for the operation of the multi-unit server;
the computing unit, the switching unit, the power supply unit and the switching and managing unit are respectively connected with a back plate of the multi-unit server through a VPX bus.
2. The VPX architecture-based multi-unit server implementation method of claim 1, wherein the computing units are multiple and physically and logically independent of each other.
3. The VPX architecture-based multi-cell server implementation method of claim 2, wherein the number of computing units connected to the multi-cell server backplane through the VPX bus is not more than 4.
4. The VPX architecture-based multi-cell server implementation method of claim 3, wherein the number of switching cells connected to the multi-cell server backplane through the VPX bus is no more than 2.
5. The VPX architecture-based multi-cell server implementation method of claim 4, wherein the number of switching and management units connected to the multi-cell server backplane through the VPX bus is 1.
6. The VPX architecture-based multi-cell server implementation method of claim 5, wherein the number of power supply units connected to the multi-cell server backplane through the VPX bus is 4.
7. The method of claim 1, wherein the Intel Xeon E52600 series v4 processors are selected as the processors to provide high-performance processing capability for a computing motherboard;
the processor adopts DIMM memory to carry out mainboard design, the mainboard provides 4 DDR4 DIMM memory slots, the maximum capacity of a single DDR4 DIMM memory is 64GB, and the maximum support of the single mainboard memory can be extended to 256 GB; 2 groups of gigabit networks and 2 groups of gigabit networks are externally led out of the main board, and data transmission links among a plurality of computing units are constructed through the switching units to realize data transmission.
8. The method as claimed in claim 7, wherein when 2 sets of tera networks are externally connected to the motherboard, an Intel 82599ES chip is used as a control chip of the tera network, and 2 tera interfaces are shared by 1 PCIE x 8 signal interface 82599ES chips of the processor, so as to provide sufficient network bandwidth for the plurality of computing units.
9. The method as claimed in claim 8, wherein when 2 gigabit networks are externally connected to the motherboard, the control chip of the gigabit network uses an Intel I350 chip, and at this time, PCIE × 4 signal of the bridge C612 is used to connect the control chip Intel I350 of the gigabit network to convert 2 gigabit interfaces, and USB2.0 and SATA3.0 interfaces are extended, and one PCIE × 1 signal and LPC signal of the bridge C612 are connected to the BMC management chip AST2400 of the motherboard, so as to implement state management of the motherboard and monitor the operating state of the motherboard through I2C bus.
10. The VPX architecture-based multi-element server implementation method of claim 9, wherein a RGMII port of the BMC management chip AST2400 on the motherboard is connected to a transceiver of a gigabit network, and a gigabit network port of an RJ45 interface is externally led out to implement network management on the motherboard;
VGA signals of the BMC management chip AST2400 on the mainboard are led out externally and transmitted to the switching and management unit through the VPX bus of the backboard, and sharing of the VGA + USB interface is achieved.
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