CN112332843A - Capacitor array, SAR (synthetic aperture radar) type analog-digital converter and capacitor calibration method - Google Patents
Capacitor array, SAR (synthetic aperture radar) type analog-digital converter and capacitor calibration method Download PDFInfo
- Publication number
- CN112332843A CN112332843A CN202011164059.6A CN202011164059A CN112332843A CN 112332843 A CN112332843 A CN 112332843A CN 202011164059 A CN202011164059 A CN 202011164059A CN 112332843 A CN112332843 A CN 112332843A
- Authority
- CN
- China
- Prior art keywords
- capacitor
- capacitor array
- array
- auxiliary
- capacitance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention belongs to the technical field of integrated circuits, and provides a capacitor array, an SAR type analog-digital converter and a capacitor calibration method, wherein the capacitor array comprises a low-section capacitor array, a high-section capacitor array, a scaling capacitor and an auxiliary capacitor array; one end of each capacitor in the low-section capacitor array is connected with one end of a scaling capacitor, and one end of each capacitor in the high-section capacitor array is connected with the other end of the scaling capacitor; the other end of each capacitor in the low-section capacitor array and the high-section capacitor array is selectively connected with a reference voltage or grounded through a first multi-path selection switch corresponding to the capacitor; one end of each capacitor in the auxiliary capacitor array is selectively connected with reference voltage or grounded through a second multi-way selection switch corresponding to the capacitor. According to the invention, the auxiliary capacitor array is added, and disturbance is added to the main capacitor array randomly in the calibration process, so that the error of the low-order capacitor is prevented from being gradually accumulated to the high-order capacitor, and the calibration precision of the capacitor is improved.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a capacitor array, an SAR analog-to-digital converter and a capacitor calibration method.
Background
The Successive Approximation type analog-to-digital conversion circuit comprises a Successive Approximation Register (SAR for short), a digital-to-analog conversion circuit and a comparator, wherein the digital-to-analog conversion circuit comprises capacitor arrays with capacitors connected in parallel, and corresponding analog quantity is output according to the current access state of each capacitor in the capacitor arrays. The capacitor array has two main functions: firstly, according to a designed switching time sequence, sequentially carrying out binary search according to an output result of a comparator and successive approximation logic to obtain an analog input quantized digital code; the second is to hold the input level sampled by the bootstrap switch as part of a sample-and-hold circuit. The successive approximation register controls the access state of each capacitor in the capacitor array, the comparator compares the analog quantity output by the digital-to-analog conversion circuit with the input signal obtained by sampling, and the digital quantity is output according to the comparison result. Generally, the capacitors in the capacitor array are sequentially connected into the circuit from high to low, and the combination of all obtained digital quantities is the output result/output signal of the successive approximation type analog-to-digital conversion circuit. The performance of the successive approximation type analog-to-digital conversion circuit cannot be reduced due to the deviation of the low-order capacitor in the capacitor array, but the high-order capacitor needs to be calibrated.
The conventional capacitance calibration method is as follows: and starting calibration from the lowest capacitor in the high capacitors, and then sequentially calibrating the high capacitors according to the calibration result of the low capacitors. Taking calibration of the high-order capacitors C9-C12 as an example, the capacitor C9 is calibrated according to the low-order capacitors C1-C8, then the capacitor C10 is calibrated according to the capacitors C1-C9, and so on until the capacitor C12 is calibrated. It can be seen that the calibration value of the high-order capacitor is only related to the capacitance value/capacitance weight of the lower-order capacitor, once an error is introduced during calibration of a certain capacitor, the error of the lower-order capacitor is gradually accumulated to the high-order capacitor, so that a large error occurs during calibration of the high-order capacitor, and the calibration result is inaccurate.
Disclosure of Invention
In view of the above, the present invention is directed to a capacitor array, a SAR type analog-to-digital converter and a capacitor calibration method, which can calibrate the capacitors in the capacitor array more accurately.
To achieve the above object, one aspect of the present invention provides a capacitor array, including: the low-section capacitor array, the high-section capacitor array and the scaling capacitor; the capacitors in the low-stage capacitor array are sequentially arranged in an nth power mode of 2 according to the weight of the capacitors; wherein n is a non-negative integer; one end of each capacitor in the low-section capacitor array is connected with one end of the scaling capacitor, and one end of each capacitor in the high-section capacitor array is connected with the other end of the scaling capacitor; the other end of each capacitor in the low-section capacitor array and the high-section capacitor array is selectively connected with a reference voltage or grounded through a first multi-path selection switch corresponding to the capacitor; further comprising: an auxiliary capacitor array;
one end of each capacitor in the auxiliary capacitor array is selectively connected with the reference voltage or grounded through a second multi-path selection switch corresponding to the capacitor, and the other end of each capacitor in the auxiliary capacitor array is connected with the other end of the scaling capacitor.
Preferably, the capacitors in the auxiliary capacitor array are sequentially arranged in a manner of m-th power of 2 according to the capacitance weight; wherein m is a non-negative integer.
Further, the auxiliary capacitor array further comprises a complementary capacitor; the weight of the bit-filling capacitor is equal to that of the lowest bit capacitor in the auxiliary capacitor array; the complementary capacitor is connected in parallel with the lower end of the lowest capacitor in the auxiliary capacitor array.
Furthermore, each bit of capacitor in the high-section capacitor array is composed of two parallel sub-capacitors with equal weights, and the sum of the weights of the two sub-capacitors is equal to the weight of the bit of capacitor.
Preferably, the capacitance value of the lowest-order capacitor in the low-stage capacitor array is 4-8 times that of the lowest-order capacitor in the auxiliary capacitor array.
Further, still include:
and the switch control module is used for controlling the connection state of each second multi-path selection switch so as to enable one end of each capacitor in the auxiliary capacitor array to be connected with the reference voltage or grounded.
Further, still include:
a random number generator for generating a multi-bit binary random number; the number of bits of the binary random number is the same as the number of capacitors in the auxiliary capacitor array;
the switch control module is used for controlling the connection state of each second multi-path selection switch according to the binary random number so as to enable one end of each capacitor in the auxiliary capacitor array to be connected with the reference voltage or grounded.
According to the capacitor array, the auxiliary capacitor array is added, so that disturbance can be added to the main capacitor array (the low-stage capacitor array and the high-stage capacitor array) randomly in the process of calibrating the calibrated capacitor, the calibration value of the calibrated capacitor is not only dependent on the weight of the capacitor at the lower position, the error of the capacitor at the lower position is prevented from being accumulated to the higher position gradually, and the calibration precision of the capacitor is improved.
Another aspect of the present invention provides a SAR analog-to-digital converter, comprising: a SAR, a comparator, and a capacitive array of any of the above;
the SAR is used for controlling the other end of each capacitor in the low-stage capacitor array and the high-stage capacitor array to be connected with the reference voltage or grounded;
the output end of the capacitor array is connected to one input end of the comparator, and the other input end of the comparator is connected with a preset common mode voltage; the comparator is used for comparing the output result of the capacitor array with the preset common-mode voltage and outputting a corresponding digital quantity according to the comparison result.
The invention also provides a capacitance calibration method, which is applied to the SAR analog-to-digital converter, and the method comprises the following steps:
the method comprises the following steps: acquiring all random capacitance values which can be provided by the auxiliary capacitor array, calculating the average value of all the random capacitance values, and taking the capacitor corresponding to the average value as the sampling capacitor of the auxiliary capacitor array;
step two: in the sampling stage of the SAR analog-digital converter, one end of a sampling capacitor of the auxiliary capacitor array and the other end of a calibrated capacitor in the high-stage capacitor array are connected with the reference voltage, and the rest capacitors in the capacitor array are grounded; the output end of the capacitor array is also connected to the other input end of the comparator;
step three: in the conversion phase of the SAR analog-to-digital converter, disconnecting the output end of the capacitor array from the other input end of the comparator; grounding the other end of the calibrated capacitor, and randomly connecting one or more capacitors in the auxiliary capacitor array with the reference voltage; the other end of each capacitor with the lower digit than the calibration capacitor is connected with the reference voltage by the SAR successive control so as to execute a successive approximation algorithm and obtain a successive approximation result of the time;
step four: calculating the current weight of the calibrated capacitor according to the current successive approximation result;
circularly executing the second step to the fourth step to obtain the weights of the plurality of calibrated capacitors; wherein, in step three, the capacitance in the auxiliary capacitor array randomly connected with the reference voltage is different during each cycle; the number of times of cycle execution is N times of the number of different random capacitance values which can be generated by the auxiliary capacitor array; wherein N is a natural number;
step five: and calculating the average value of the weights of the plurality of calibrated capacitances to obtain the calibration value of the calibrated capacitances.
Preferably, the number of times of execution of the cycle is equal to the number of different random capacitance values that can be generated by the auxiliary capacitance array.
Based on the capacitor array, in each calibration process of the calibrated capacitor, one or more capacitors in the auxiliary capacitor array are randomly accessed to serve as disturbance to a main capacitor array (namely a high-stage capacitor array and a low-stage capacitor array), the steps are executed for multiple times on the calibrated capacitor, the weights of the plurality of calibrated capacitors are obtained, the average value of the obtained weights of the plurality of calibrated capacitors is calculated, and then the calibration value of the calibrated capacitor is obtained. Because random disturbance is added in each calibration process, and the final calibration value is obtained by means of averaging in multiple calibrations, the calibration value of the calibrated capacitor is no longer only dependent on the weight of the capacitor at the lower position, the error of the capacitor at the lower position is prevented from being gradually accumulated to the higher position, and the calibration precision of the capacitor is improved.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic structural diagram of a capacitor array according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an SAR analog-to-digital converter according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method of calibrating a capacitor according to an embodiment of the present invention;
fig. 4 is a distribution diagram of results obtained after a plurality of times of calibration is performed on a calibrated capacitor by using the capacitor calibration method according to the embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
An embodiment of the present invention provides a capacitor array, as shown in fig. 1, the capacitor array includes: the low-stage capacitor array C1-C8, the high-stage capacitor array C9-C12 and the scaling capacitor Cc. The capacitors C1-C8 in the low-stage capacitor array are sequentially arranged in an nth power mode of 2 according to the weight of the capacitors; wherein n is a non-negative integer. In this embodiment, n starts to take a value from 0, that is, the capacitance weights of C1 to C8 are 1, 2, 4, 8, 16, 32, 64, and 128 in sequence. One end of each capacitor C1-C8 in the low-stage capacitor array is connected with one end of the scaling capacitor Cc, and one end of each capacitor C9-C12 in the high-stage capacitor array is connected with the other end of the scaling capacitor Cc; the other end of each capacitor C1-C12 in the low-stage capacitor array and the high-stage capacitor array is selectively connected with a reference voltage VREF or grounded GND through a first multi-way selection switch corresponding to the capacitor.
Different from the existing capacitor array, the capacitor array provided by the embodiment of the invention further comprises: and one end of each capacitor in the auxiliary capacitor array is selectively connected with the reference voltage VREF or the ground GND through a second multi-way selection switch corresponding to the capacitor, and the other end of each capacitor in the auxiliary capacitor array is connected with the other end of the scaling capacitor Cc.
By adding the auxiliary capacitor array, disturbance can be added to the main capacitor array (the low-stage capacitor array and the high-stage capacitor array) randomly in the process of calibrating the calibrated capacitor, so that the calibration value of the calibrated capacitor does not depend on the weight of the capacitor at a lower position, the error of the low-stage capacitor is prevented from being accumulated to a higher position step by step, and the calibration precision of the capacitor is improved.
In order to improve convenience of operation and calculation, in this embodiment, the capacitors in the auxiliary capacitor array are sequentially arranged in a manner of m-th power of 2 according to the capacitance weight; wherein m is a non-negative integer. Further, the auxiliary capacitor array further comprises a complementary capacitor; the weight of the bit-filling capacitor is equal to that of the lowest bit capacitor in the auxiliary capacitor array; the complementary capacitor is connected in parallel with the lower end of the lowest capacitor in the auxiliary capacitor array.
As shown in fig. 1, the auxiliary capacitor array includes capacitors Cx 2Cx, 4Cx, and 8Cx arranged in sequence from the lower level to the upper level, and the auxiliary capacitor array also includes a complementary capacitor Cx. Wherein, the relation between Cx and the capacitance C1 in the low-stage capacitor array is as follows: the capacitance of the capacitor C1 is 4-8 times the capacitance of the capacitor Cx, i.e. the capacitance of the lowest capacitor C1 in the low-stage capacitor array is 4-8 times the capacitance of the lowest capacitor Cx in the auxiliary capacitor array. Preferably, the capacitance value of the lowest capacitance C1 in the low-stage capacitor array is 4 times the capacitance value of the lowest capacitance Cx in the auxiliary capacitor array.
In order to calibrate each capacitor in the high-stage capacitor array more accurately so as to further improve the calibration accuracy, in this embodiment, each capacitor in the high-stage capacitor array is split into two capacitors with equal weights connected in parallel, that is, each capacitor in the high-stage capacitor array is composed of two sub-capacitors connected in parallel and with equal weights, and the sum of the weights of the two sub-capacitors is equal to the weight of the capacitor. For example, the capacitor C9 is split into a capacitor C9_1 and a capacitor C9_2, and the weights thereof satisfy the relation W9＝W9_1+W9_2(ii) a The capacitor C10 is split into a capacitor C10_1 and a capacitor C10_2, andwhose weight satisfies the relation W10＝W10_1+W10_2(ii) a The capacitor C11 is split into a capacitor C11_1 and a capacitor C11_2, and the weights thereof satisfy the relation W11＝W11_1+W11_2(ii) a The capacitor C12 is split into a capacitor C12_1 and a capacitor C12_2, and the weights thereof satisfy the relation W12＝W12_1+W12_2。
The splitting operation of the high-section capacitor is completed when the capacitor array leaves a factory, but due to capacitance value deviation caused in the production and manufacturing process, each split capacitor needs to be calibrated bit by bit in actual working. After the calibration of the capacitor, the split capacitor is operated simultaneously as an integral capacitor in the normal operation stage of the digital-to-analog conversion circuit, for example, in the normal operation stage of the digital-to-analog conversion circuit, the capacitor C9_1 and the capacitor C9_2 are used as an integral capacitor C9 to perform successive approximation operation.
In order to further improve the convenience of operation and the automation degree of the whole system, the capacitor array further includes: and a switch control module (not shown in the figure) for controlling the connection state of each second multi-way selection switch, so that one end of each capacitor in the auxiliary capacitor array is connected to the reference voltage VREF or the ground GND.
Further, the capacitor array of this embodiment further includes:
a random number generator for generating a multi-bit binary random number; the number of bits of the binary random number is the same as the number of capacitors in the auxiliary capacitor array; then, the switch control module is configured to control a connection state of each second multi-way selector switch according to the binary random number, so that one end of each capacitor in the auxiliary capacitor array is connected to the reference voltage or ground.
For example, when the binary random number generated by the random number generator is 00001, the switch control module controls the rightmost complement capacitor Cx in fig. 1 to be connected to the reference voltage VREF, and the rest 4-bit capacitors are grounded; when the binary random number generated by the random number generator is 11000, the switch control module controls the highest-order capacitor 8Cx and the second highest-order capacitor 4Cx in the auxiliary capacitor array to be connected with the reference voltage VREF, and the rest 3-order capacitors are grounded. If the highest bit capacitance 8Cx and the second highest bit capacitance 4Cx are connected with the reference voltage VREF at the same time, the capacitance equivalent to 12Cx is connected into the circuit. In the capacitance calibration process, random capacitance generated by the method is connected into the main capacitor array, random disturbance is generated on the main capacitor array, and successive accumulation of certain capacitance weight error is avoided.
Based on the above embodiment of the capacitor array, the present invention further provides a SAR type analog-to-digital converter, as shown in fig. 2, including: SAR, comparator, and capacitor array as described in the above embodiments. The SAR is used for controlling the other end of each capacitor C12-C1 in the low-stage capacitor array and the high-stage capacitor array to be connected with the reference voltage VREF or grounded. The output end of the capacitor array is connected to one input end of the comparator, and the other input end of the comparator is connected with a preset common-mode voltage VCM; the comparator is used for comparing the output result of the capacitor array with the preset common-mode voltage VCM and outputting a corresponding digital quantity according to the comparison result.
In particular, during normal operation, SAR provides the logic function that implements the analog-to-digital conversion process. After the SAR analog-digital converter finishes sampling, SAR firstly follows the highest-order capacitor C of the capacitor arrayNStart comparison, adjust CNThe state of the circuit is accessed, then the output value (0 or 1) of the highest bit of the output code of the SAR analog-digital converter is judged according to the output result of the comparator, and the highest bit capacitor C is adjustedNThe state of the access circuit. After the highest bit comparison is completed, SAR adjusts the secondary high-bit capacitance CN-1The state of the circuit is switched in, then the output value (0 or 1) of the second highest bit of the output code of the SAR analog-digital converter is judged according to the output result of the comparator, and the second highest bit capacitor C is adjustedN-1The state of the access circuit. And so on until the lowest position C1The comparison of N bits is completed, and the output of N-bit digital code is completed.
In fig. 1, the other end of the scaling capacitor Cc is used as the output of the whole capacitor array, VOUT in fig. 1 is the output voltage of the capacitor array, and the VOUT signal is connected to one input end of the comparator and compared with the common-mode voltage VCM, so that the comparator outputs a digital quantity of 0 or 1 according to the comparison result.
Based on the above embodiments of the capacitor array and the SAR-type analog-to-digital converter, the present invention further provides a capacitance calibration method, as shown in fig. 3, applied to the SAR-type analog-to-digital converter, where the method includes:
the method comprises the following steps: and acquiring all random capacitance values which can be provided by the auxiliary capacitor array, calculating the average value of all the random capacitance values, and taking the capacitor corresponding to the average value as the sampling capacitor of the auxiliary capacitor array.
Based on the auxiliary capacitor array described in this embodiment, the average value of the random capacitance values provided by the auxiliary capacitor array is:
(0+Cx+2Cx+3Cx+…+15Cx+16Cx)/17＝8Cx
that is, in the present embodiment, the highest-order capacitance 8Cx in the auxiliary capacitance array is used as the sampling capacitance of the auxiliary capacitance array.
Step two: in the sampling stage of the SAR analog-digital converter, one end of a sampling capacitor of the auxiliary capacitor array and the other end of a calibrated capacitor in the high-stage capacitor array are connected with the reference voltage, and the rest capacitors in the capacitor array are grounded; the output end of the capacitor array is also connected to the other input end of the comparator.
Taking the capacitor C9_1 in the calibrated high-stage capacitor array as an example, in the sampling stage of the SAR analog-to-digital converter, only the capacitor 8Cx in the auxiliary capacitor array is connected to the circuit, that is, the upper plate of the capacitor 8Cx is connected to the reference voltage VREF, and the rest capacitors are grounded; in the main capacitor array, only the lower plate of the calibrated capacitor C9_1 is connected with the reference voltage VREF, and the rest capacitors are grounded. Meanwhile, the output terminal VOUT of the capacitor array is also connected to the other input terminal of the comparator, that is, the output terminal VOUT is also connected to the VCM terminal in fig. 2, and the two input terminals of the comparator are shorted to complete sampling of the capacitances (the capacitance 8Cx and the calibrated capacitance C9_1) of the access circuit.
Step three: in the conversion phase of the SAR analog-to-digital converter, disconnecting the output end of the capacitor array from the other input end of the comparator; grounding the other end of the calibrated capacitor, and randomly connecting one or more capacitors in the auxiliary capacitor array with the reference voltage; the other end of each capacitor with the lower digit than the calibration capacitor is connected with the reference voltage by the SAR successive control so as to execute a successive approximation algorithm and obtain a successive approximation result of the time;
in this embodiment, in the conversion stage of the SAR analog-to-digital converter, the output terminal VOUT of the capacitor array is first disconnected from the VCM terminal in fig. 2, so that the successive approximation algorithm is normally executed in the following stage. A binary random number is randomly generated through a random number generator, the switch control module controls the corresponding auxiliary capacitor access circuit according to the binary random number, and the rest auxiliary capacitors are grounded; in the main capacitor array, the lower plate of the calibrated capacitor C9_1 is grounded, and then the lower plates of the capacitors C8-C1 are controlled by SAR in a successive approximation mode to be connected with a reference voltage VREF so as to execute a successive approximation algorithm and obtain a successive approximation result of the time.
For example, when the lower plate of the capacitor C8 is connected to the reference voltage VREF, the output result of the comparator is 0; when the lower plate of the capacitor C7 is connected with the reference voltage VREF, the output result of the comparator is 1; when the lower plate of the capacitor C6 is connected to the reference voltage VREF, the output result of the comparator is 1, and so on, and finally 8 digital quantities are obtained, the combination of the 8 digital quantities is the successive approximation result of this time, and it is assumed that the successive approximation result is 01100110.
It should be noted that, if the calibrated capacitor is the capacitor C9_2, in the process of executing the successive approximation algorithm by the SAR, the calibration is still performed only for the capacitors C8 to C1; if the calibrated capacitor is the capacitor C10_1, in the process of executing the successive approximation algorithm by the SAR, the successive approximation algorithm is executed for the capacitors C9 to C1, wherein C9 is no longer considered as two capacitors C9_1 and C9_2, but the successive approximation algorithm is executed as a whole. And the calibration of other high-order capacitors is carried out in the same way.
Step four: calculating the current weight of the calibrated capacitor according to the current successive approximation result;
in this embodiment, the weight of the calibrated capacitor C9_1 is calculated by the following formula:
wherein, WC9_1To be calibrated capacitor C9_Weight of 1, diThe output result of the comparator is when the lower plates of the capacitors C8-C1 are sequentially connected with the reference voltage VREF. According to the successive approximation result 01100110 obtained in the third step, the calibrated capacitor C9 can be obtained_1, this weight.
Circularly executing the second step to the fourth step to obtain the weights of the plurality of calibrated capacitors; in step three, the capacitors in the auxiliary capacitor array randomly connected to the reference voltage are different in each cycle, that is, the auxiliary capacitance value of the circuit is different in each time of connection, or the binary random number is changed once in each cycle of execution. The number of times of cycle execution is N times of the number of different random capacitance values which can be generated by the auxiliary capacitor array; wherein N is a natural number. Preferably, the number of times of executing the loop is equal to the number of different random capacitance values that can be generated by the auxiliary capacitor array, namely, the value of N is 1.
In this embodiment, since the number of different random capacitance values generated by the auxiliary capacitor array is 17 (0, Cx, 2Cx, 3Cx, …, 15Cx, 16Cx), the steps two to four are performed in a loop 17 times to obtain the weights of the 17 calibrated capacitors C9_ 1. Of course, the loop can be executed 34 times or more times according to actual conditions.
During the loop execution, the capacitance in the auxiliary capacitor array randomly connected to the reference voltage VREF at each loop execution is determined by a binary random number generated by a random number generator, which will equally place 0Cx to 16Cx into the circuit during each calibration.
Step five: and calculating the average value of the weights of the plurality of calibrated capacitances to obtain the calibration value of the calibrated capacitances.
In this embodiment, the average value of the weights of the 17 calibrated capacitors C9_1 is calculated to obtain the average weight of the calibrated capacitor C9_1, i.e., the average weight after 17 "perturbations" are added, and the average weight is used as the actual weight of C9_1 during normal operation, and the average weight is also referred to as the calibration value of the capacitor C9_ 1.
The above method can be summarized by the following formula:
because the capacitance of the access circuit (i.e. the capacitance of the access reference voltage VREF) is: cdut+8Cx, wherein CdutIs a calibrated capacitance. In order to calibrate the calibrated capacitor, the calibrated capacitor needs to be represented by using a low-order capacitor, that is, the capacitor in the conversion phase is used to represent the capacitor in the sampling phase, and therefore, the following formula can be obtained:
wherein the right side of the equation represents averaging a plurality of weights of the calculated calibrated capacitance; n is the number of times of circularly executing the step two to the step four; the Caux (i) is a capacitance value added by the auxiliary capacitor array in the step two to the step four (namely in the ith calibration conversion process) executed in the ith cycle; dout (i) represents the output value of the comparator corresponding to successive approximation of the low-order capacitor in the ith calibration conversion process, for example, when the capacitor C9_1 is calibrated and converted, the low-order capacitors C8-C1 are successively approximated to obtain a binary result 10000001, and the value of dout (i) corresponding to this calibration conversion is decimal 129.
Since the random capacitances 0Cx to 16Cx that can be generated by the auxiliary capacitance array can be accessed into the circuit at an equal chance each time the calibration is switched, and the average value of the random capacitances 0Cx to 16Cx is 8Cx, when 8Cx is eliminated on both the left and right sides of the above equation (2), the equation (2) can be switched:
equation (3) above represents the calibrated capacitance C by the weight of the capacitance C1dutI.e. the weight through C1 and the successive approximation junctionIf so, the calibrated capacitance C can be calculateddutThe weight of (C), that is, the calibrated capacitance CdutThe actual weights after calibration.
The embodiment of the invention adopts the mode of averaging by multiple times of calibration, and can improve the calibration precision of the capacitor. The access of the auxiliary capacitor controlled by the binary random number can avoid the same number of conversion results every time, thereby avoiding the failure of the averaging method.
The principle that the method can calibrate the calibrated capacitor C9_1 is as follows:
in the sampling phase, the calibrated capacitor C9_1 is sampled. The purpose of sampling is to switch the calibrated capacitor C9_1 once, thereby sampling its weight, followed by transform quantization.
During the sampling phase, the calibrated capacitor C9_1 is connected to the reference voltage VREF, and this connection samples the charge of VREF × C on the calibrated capacitor C9_ 1. At a subsequent transition, the calibrated capacitor C9_1 switches from VREF to 0, which results in a change in the output VOUT of the capacitor array. Then starting from C8, the lower plate is switched to VREF by successive trials, if VOUT has not recovered to the state before the change of C9_1, the bit keeps VREF, i.e. d8 is 1, and the trial of the next bit continues; if the change in VOUT has exceeded the state before the change in C9_1, then the bit is restored to 0, i.e., d8 is 0; the trial of the next bit continues. The action of each of the latter bits is the same as the logic of d8 until C1 completes the heuristic. Such successive approximation operation makes the states of C1 to C8 equivalent to the effect of C9_1 switching, so that the calibrated capacitance is represented by the lower capacitance and the upper weight is represented by the lower weight.
In the above embodiment, 8Cx is the middle value of the whole calibration array, and is connected to the reference voltage VREF when sampling, and when disturbance is added in the subsequent conversion period, since the average value of the added 17 disturbances is 8Cx, the disturbance array does not affect the performance of the whole SAR type analog-to-digital converter. The lower plate of the calibrated capacitor C9_1 is switched once compared with the sampling phase, and the subsequent C8-C1 sequentially try to switch to VREF until the C8-C1 can produce the same effect as the C9_ 1.
Fig. 4 is a schematic diagram showing distribution of results obtained by performing multiple calibrations on a calibrated capacitor by using the capacitor calibration method according to the embodiment of the present invention, in fig. 4, multiple results obtained by performing multiple calibrations on a calibrated capacitor are normally distributed, and a value in the diagram represents a calibrated capacitor CdutIs weighted by more or less times the weight of the capacitor C1. Averaging the results can result in a decimal fraction close to 11.4, whereas when not averaged, only integer results of 11 or 12 can be obtained. That is, the calibrated capacitance C is not averaged multiple timesdutThe actual weight of (C) would be expressed as an integer multiple of the capacitance C1; and if the averaging mode is adopted for multiple times, the calibrated capacitor CdutMay be expressed as a fractional multiple of the capacitance C1. Therefore, the calibration precision of each bit of capacitor is improved by a method of converting for many times and adding random numbers.
According to the capacitor array, the SAR type analog-to-digital converter and the capacitor calibration method, the auxiliary capacitor array is added in the capacitor array, in each calibration process of the calibrated capacitor, one or more capacitors in the auxiliary capacitor array are randomly accessed to serve as disturbance to a main capacitor array (namely a high-stage capacitor array and a low-stage capacitor array), the steps are carried out on the calibrated capacitor for multiple times, the weights of a plurality of calibrated capacitors are obtained, the average value of the obtained weights of the plurality of calibrated capacitors is calculated, and then the calibration value of the calibrated capacitor is obtained. Because random disturbance is added in each calibration process, and the final calibration value is obtained by means of averaging in multiple calibrations, the calibration value of the calibrated capacitor is no longer only dependent on the weight of the capacitor at the lower position, the error of the capacitor at the lower position is prevented from being gradually accumulated to the higher position, and the calibration precision of the capacitor is improved.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention do not describe every possible combination.
Those skilled in the art will understand that all or part of the steps in the method according to the above embodiments may be implemented by a program, which is stored in a storage medium and includes several instructions to enable a single chip, a chip, or a processor (processor) to execute all or part of the steps in the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In addition, any combination of different implementation manners of the embodiments of the present invention can be performed, and the embodiments of the present invention should be considered as disclosed in the embodiments of the present invention as long as the combination does not depart from the idea of the embodiments of the present invention.
Claims (10)
1. A capacitive array, comprising: the low-section capacitor array, the high-section capacitor array and the scaling capacitor; the capacitors in the low-stage capacitor array are sequentially arranged in an nth power mode of 2 according to the weight of the capacitors; wherein n is a non-negative integer; one end of each capacitor in the low-section capacitor array is connected with one end of the scaling capacitor, and one end of each capacitor in the high-section capacitor array is connected with the other end of the scaling capacitor; the other end of each capacitor in the low-section capacitor array and the high-section capacitor array is selectively connected with a reference voltage or grounded through a first multi-path selection switch corresponding to the capacitor; it is characterized by also comprising: an auxiliary capacitor array;
one end of each capacitor in the auxiliary capacitor array is selectively connected with the reference voltage or grounded through a second multi-path selection switch corresponding to the capacitor, and the other end of each capacitor in the auxiliary capacitor array is connected with the other end of the scaling capacitor.
2. The capacitor array according to claim 1, wherein each capacitor in the auxiliary capacitor array is sequentially arranged in a manner of m-th power of 2 according to the capacitance weight; wherein m is a non-negative integer.
3. The capacitive array of claim 2, wherein the auxiliary capacitive array further comprises a complementary capacitance; the weight of the bit-filling capacitor is equal to that of the lowest bit capacitor in the auxiliary capacitor array; the complementary capacitor is connected in parallel with the lower end of the lowest capacitor in the auxiliary capacitor array.
4. The capacitor array of claim 3, wherein each bit of capacitor in the high-end capacitor array is composed of two bit of parallel sub-capacitors with equal weight, and the sum of the weights of the two bit of parallel sub-capacitors is equal to the weight of the bit of capacitor.
5. The capacitor array of claim 3, wherein the capacitance of the lowest capacitor in the low-end capacitor array is 4-8 times the capacitance of the lowest capacitor in the auxiliary capacitor array.
6. The capacitive array of claim 1, further comprising:
and the switch control module is used for controlling the connection state of each second multi-path selection switch so as to enable one end of each capacitor in the auxiliary capacitor array to be connected with the reference voltage or grounded.
7. The capacitive array of claim 6, further comprising:
a random number generator for generating a multi-bit binary random number; the number of bits of the binary random number is the same as the number of capacitors in the auxiliary capacitor array;
the switch control module is used for controlling the connection state of each second multi-path selection switch according to the binary random number so as to enable one end of each capacitor in the auxiliary capacitor array to be connected with the reference voltage or grounded.
8. A SAR analog-to-digital converter, comprising: a SAR, a comparator, and a capacitive array of any one of claims 1 to 7;
the SAR is used for controlling the other end of each capacitor in the low-stage capacitor array and the high-stage capacitor array to be connected with the reference voltage or grounded;
the output end of the capacitor array is connected to one input end of the comparator, and the other input end of the comparator is connected with a preset common mode voltage; the comparator is used for comparing the output result of the capacitor array with the preset common-mode voltage and outputting a corresponding digital quantity according to the comparison result.
9. A capacitance calibration method applied to the SAR type analog-to-digital converter of claim 8, the method comprising:
the method comprises the following steps: acquiring all random capacitance values which can be provided by the auxiliary capacitor array, calculating the average value of all the random capacitance values, and taking the capacitor corresponding to the average value as the sampling capacitor of the auxiliary capacitor array;
step two: in the sampling stage of the SAR analog-digital converter, one end of a sampling capacitor of the auxiliary capacitor array and the other end of a calibrated capacitor in the high-stage capacitor array are connected with the reference voltage, and the rest capacitors in the capacitor array are grounded; the output end of the capacitor array is also connected to the other input end of the comparator;
step three: in the conversion phase of the SAR analog-to-digital converter, disconnecting the output end of the capacitor array from the other input end of the comparator; grounding the other end of the calibrated capacitor, and randomly connecting one or more capacitors in the auxiliary capacitor array with the reference voltage; the other end of each capacitor with the lower digit than the calibration capacitor is connected with the reference voltage by the SAR successive control so as to execute a successive approximation algorithm and obtain a successive approximation result of the time;
step four: calculating the current weight of the calibrated capacitor according to the current successive approximation result;
circularly executing the second step to the fourth step to obtain the weights of the plurality of calibrated capacitors; wherein, in step three, the capacitance in the auxiliary capacitor array randomly connected with the reference voltage is different during each cycle; the number of times of cycle execution is N times of the number of different random capacitance values which can be generated by the auxiliary capacitor array; wherein N is a natural number;
step five: and calculating the average value of the weights of the plurality of calibrated capacitances to obtain the calibration value of the calibrated capacitances.
10. The capacitance calibration method according to claim 9, wherein the number of times of the loop execution is equal to the number of different random capacitance values that can be generated by the auxiliary capacitor array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011164059.6A CN112332843B (en) | 2020-10-27 | 2020-10-27 | Capacitor array, SAR (synthetic aperture radar) type analog-digital converter and capacitor calibration method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011164059.6A CN112332843B (en) | 2020-10-27 | 2020-10-27 | Capacitor array, SAR (synthetic aperture radar) type analog-digital converter and capacitor calibration method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112332843A true CN112332843A (en) | 2021-02-05 |
| CN112332843B CN112332843B (en) | 2022-01-14 |
Family
ID=74296861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011164059.6A Active CN112332843B (en) | 2020-10-27 | 2020-10-27 | Capacitor array, SAR (synthetic aperture radar) type analog-digital converter and capacitor calibration method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112332843B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120001781A1 (en) * | 2010-06-30 | 2012-01-05 | University Of Limerick | Digital Background Calibration System and Method for Successive Approximation (SAR) Analogue to Digital Converter |
| CN105811979A (en) * | 2016-03-03 | 2016-07-27 | 电子科技大学 | Successive approximation analog-to-digital converter and correction method |
| CN107579740A (en) * | 2017-08-25 | 2018-01-12 | 深圳清华大学研究院 | Improve the method and analog-digital converter of production line analog-digital converter output accuracy |
| CN110350918A (en) * | 2019-07-17 | 2019-10-18 | 电子科技大学 | A kind of digital Background calibration method based on least mean square algorithm |
-
2020
- 2020-10-27 CN CN202011164059.6A patent/CN112332843B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120001781A1 (en) * | 2010-06-30 | 2012-01-05 | University Of Limerick | Digital Background Calibration System and Method for Successive Approximation (SAR) Analogue to Digital Converter |
| CN105811979A (en) * | 2016-03-03 | 2016-07-27 | 电子科技大学 | Successive approximation analog-to-digital converter and correction method |
| CN107579740A (en) * | 2017-08-25 | 2018-01-12 | 深圳清华大学研究院 | Improve the method and analog-digital converter of production line analog-digital converter output accuracy |
| CN110350918A (en) * | 2019-07-17 | 2019-10-18 | 电子科技大学 | A kind of digital Background calibration method based on least mean square algorithm |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112332843B (en) | 2022-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8547270B1 (en) | Systems for sub digital-to-analog converter gain trim in successive-approximation-register analog-to-digital converters | |
| CN112202448B (en) | Successive approximation type analog-to-digital converter, calibration method thereof and electronic equipment | |
| US8049654B2 (en) | Digital trimming of SAR ADCs | |
| US10581443B2 (en) | Method and apparatus for offset correction in SAR ADC with reduced capacitor array DAC | |
| US9300312B2 (en) | Analog-digital converter | |
| WO2014039956A1 (en) | Reducing the effect of elements mismatch in an sar adc | |
| US8902092B2 (en) | Analog-digital conversion circuit and method | |
| CN110086468A (en) | A kind of weight calibration method of nonbinary gradual approaching A/D converter | |
| CN110649924B (en) | Digital self-calibration device and method of successive approximation type analog-to-digital converter | |
| CN112803946B (en) | Capacitor mismatch and offset voltage correction method applied to high-precision successive approximation ADC (analog to digital converter) | |
| CN111064468B (en) | Calibration method and calibration system | |
| CN113839672B (en) | Self-calibration successive approximation analog-digital converter utilizing redundant capacitor analog domain | |
| CN111431529A (en) | Successive approximation type analog-to-digital converter with capacitance mismatch correction function | |
| CN114598324A (en) | Redundant calibrated SAR-ADC circuit and analog-to-digital converter | |
| US20200007143A1 (en) | Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with Switchable Reference Voltage | |
| CN110535467B (en) | Capacitor array calibration method and device of stepwise approximation type analog-to-digital conversion device | |
| CN111614354B (en) | Calibration circuit for capacitance weight of analog-to-digital converter | |
| CN112332843B (en) | Capacitor array, SAR (synthetic aperture radar) type analog-digital converter and capacitor calibration method | |
| CN117254806A (en) | Analog-to-digital converter, reference voltage providing circuit thereof and processor | |
| CN217824932U (en) | Redundant calibrated SAR-ADC circuit and analog-to-digital converter | |
| KR100696945B1 (en) | Successive approximation register adc reusing a unit block of adc for implementing high bit resolution | |
| US20120133541A1 (en) | Analog-digital converter | |
| CN115940949B (en) | Split capacitor structure successive approximation analog-to-digital converter calibration circuit and method | |
| EP4366173A1 (en) | Calibration system and method for sar adcs | |
| CN111711449B (en) | Parasitic capacitance digital compensation method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |