CN112311339A - Double-frequency harmonic tuning efficient power amplifier - Google Patents
Double-frequency harmonic tuning efficient power amplifier Download PDFInfo
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- CN112311339A CN112311339A CN202011202465.7A CN202011202465A CN112311339A CN 112311339 A CN112311339 A CN 112311339A CN 202011202465 A CN202011202465 A CN 202011202465A CN 112311339 A CN112311339 A CN 112311339A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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Abstract
The invention discloses a double-frequency harmonic tuning high-efficiency power amplifier, which comprises a circuit input end and a circuit output end; the circuit input end comprises a double-frequency input matching circuit; load impedance RL1One end of the dual-frequency input matching circuit is connected with one end of the dual-frequency input matching circuit; the other end of the dual-frequency input matching circuit is respectively connected with one end of the RC stable circuit and one end of the grid dual-frequency bias circuit; the other end of the RC stable circuit is connected with a grid electrode of the transistor; the output end of the circuit comprises a drain electrode double-frequency bias circuit, a novel harmonic control circuit and a novel double-frequency output matching circuit; one end of the novel harmonic control circuit is connected with the drain electrode of the transistor; the other end of the novel harmonic control circuit is connected with one end of the novel double-frequency output matching circuit; the novel double-frequency output matching circuit is also respectively connected with one end of the drain electrode double-frequency bias circuit and the load impedance RL2One end is connected with. The invention can accurately control the second harmonic impedance of two frequency points and can improve the precision of double-frequency harmonic impedance matching.
Description
Technical Field
The invention relates to the technical field of power amplifiers, in particular to a double-frequency harmonic tuning high-efficiency power amplifier.
Background
Existing communication systems exist for multiple generations of communication networks and a number of communication standards, such as GSM, CDMA, WiMax, etc., are emerging. In order to achieve reception of signals of different frequency bands and different modes, a multi-frequency communication transmitter is developed.
Power amplifiers, the most critical module in a multi-frequency communication transmitter, also need to operate in multiple frequency bands. In addition, the power amplifier is also the most energy-consuming unit in the transmitter, and improving the efficiency of the amplifier is a necessary way to reduce the power consumption of the system. Therefore, multi-frequency high efficiency amplifiers have become a hot issue in the field of radio frequency power amplifiers, and the most basic is the design of dual-frequency high efficiency amplifiers.
The basic design criteria for a high efficiency power amplifier are: and power consumption under harmonic frequency is eliminated, so that the capacity of converting direct current power into output power is improved.
Currently, many design methods are available to realize high efficiency power amplifiers, including class F, class E and harmonic tuned amplifiers.
For the class F power amplifier, the load impedance of the even-order harmonic needs to be adjusted to zero, and the load impedance of the odd-order harmonic needs to be adjusted to infinity. Under ideal conditions, the efficiency of the class F power amplifier can reach 100%. However, due to the influence of the parasitic parameters of the transistor itself, the harmonic impedance cannot be accurately controlled, which results in a decrease in the efficiency of the power amplifier. And the circuit implementation of the class F power amplifier is also relatively complex.
For a class-E power amplifier, the transistors in the class-E power amplifier are switched, no current exists when the switches are opened, no voltage exists when the switches are closed, the waveforms of the current and the voltage have a phase difference of 180 degrees, and the maximum efficiency can reach 100 percent theoretically. However, a certain time is required for switching the state of the actual transistor, and the output capacitance of the transistor is larger than that required by the class-E power amplifier, so that the application of the class-E power amplifier in high frequency is greatly limited.
For a harmonically tuned amplifier, the harmonic impedance seen by the transistor is required to be purely reactive. In addition, the reactance values must be optimized to shape the voltage and current waveforms in the transistor in order to obtain the highest efficiency by reducing the overlap between the voltage and current waveforms. The harmonic impedance of the amplifier has a large tunable range, and high efficiency can be realized at high frequency by a simple circuit. The harmonic tuned amplifier can be combined with a dual frequency amplifier design to meet the design requirements of a dual frequency high efficiency power amplifier.
However, the existing dual-frequency harmonic tuned amplifier mainly has three problems: firstly, it is difficult to control the second harmonic and the third harmonic of two frequency points simultaneously, resulting in a large performance difference between the two frequencies; secondly, fundamental wave impedance matching of two frequency points lacks an analytic solution (namely, a solution obtained by a strict formula), and mostly depends on continuous debugging; finally, the circuit structure is complex and the harmonic control circuit needs to be further simplified.
Disclosure of Invention
The invention aims to provide a double-frequency harmonic tuning high-efficiency power amplifier aiming at the technical defects in the prior art.
Therefore, the invention provides a double-frequency harmonic tuning high-efficiency power amplifier which comprises a load impedance RL1Circuit input terminal, transistor Q, circuit output terminal and load impedance RL2；
Wherein, the circuit input includes: the dual-frequency input circuit comprises a dual-frequency input matching circuit, an RC stabilizing circuit and a grid dual-frequency biasing circuit;
load impedance RL1One end of the dual-frequency input matching circuit is connected with one end of the dual-frequency input matching circuit;
load impedance RL1The other end of the first and second electrodes is grounded;
the other end of the dual-frequency input matching circuit is respectively connected with one end of the RC stable circuit and one end of the grid dual-frequency bias circuit;
the other end of the RC stabilizing circuit is connected with a grid G of the transistor Q;
wherein, the source S of the transistor Q is grounded;
wherein, the circuit output includes: a drain electrode double-frequency bias circuit, a novel harmonic control circuit and a novel double-frequency output matching circuit;
one end of the novel harmonic control circuit is connected with a drain electrode D of the transistor Q;
the other end of the novel harmonic control circuit is connected with one end of the novel double-frequency output matching circuit;
a novel double-frequency output matching circuit, and also connected with one end of the drain electrode double-frequency bias circuit and the load impedance R respectivelyL2One end of the two ends are connected;
load impedance RL2At the other end ofAnd (3) ground.
Preferably, the dual-frequency input matching circuit comprises a series transmission line T12Capacitor C2Series transmission line T13Parallel open circuit transmission line T14And a series transmission line T15；
Series transmission line T12Is connected to a load impedance RL1One end of (a);
series transmission line T12The other end of (1) through a capacitor C2Connecting series transmission lines T13One end of (a);
series transmission line T13The other ends of the transmission lines are respectively connected with the parallel open-circuit transmission lines T14And a series transmission line T15One end of (a);
parallel open circuit transmission line T14The other end of the same is in an open state.
Preferably, the RC stabilizing circuit comprises capacitors C connected in parallel1And a resistance R1；
Capacitor C1And a resistance R1One end of the parallel circuit is connected with the series transmission line T in the double-frequency input matching circuit15The other end of (a);
capacitor C1And a resistance R1The other end of the parallel circuit is connected with a grid G of the transistor Q;
preferably, the gate dual-frequency bias circuit comprises a series transmission line T5Capacitor C4Series transmission line T7Parallel open circuit transmission line T6And a sector open circuit transmission line T8；
Series transmission line T5One end of which is connected to a series transmission line T in a dual-frequency input matching circuit15The other end of (a);
series transmission line T5The other ends of the transmission lines are respectively connected with the parallel open-circuit transmission lines T6And a series transmission line T7One end of (a);
parallel open circuit transmission line T6Is in an open circuit state;
series transmission line T7Respectively connected to a gate bias voltage VGCapacitor C4And a fan-shaped open-circuit transmission line T8One end of (a);
capacitor C4And the other end of the same is grounded.
Preferably, the novel harmonic control circuit comprises a series transmission line T9Parallel open circuit transmission line T10And a parallel open circuit transmission line T11；
Series transmission line T9Is connected to the drain D of transistor Q;
series transmission line T9Respectively connected to the parallel open-circuit transmission line T10And a parallel open-circuit transmission line T11One end of (a);
parallel open circuit transmission line T10And the other end of the parallel open circuit transmission line T11The other ends of the two-way valve are all in an open circuit state;
preferably, the novel dual-frequency output matching circuit comprises a series transmission line T1Series transmission line T3Series transmission line T4And a parallel open circuit transmission line T2；
Wherein the transmission line T is connected in series1Is connected to the series transmission line T9The other end of (a);
series transmission line T1The other ends of the transmission lines are respectively connected with the parallel open-circuit transmission lines T2And a series transmission line T3One end of (a);
series transmission line T3The other end of the capacitor is connected with a DC blocking capacitor C3One end of (a);
blocking capacitor C3Is connected to the series transmission line T4One end of (a);
series transmission line T4The other end of the connecting line is connected with a load impedance RL2。
Preferably, the drain electrode double-frequency bias circuit comprises a series transmission line T16Series transmission line T18Parallel open circuit transmission line T17And a sector open circuit transmission line T19；
Wherein the transmission line T is connected in series16One end of the first and second switches is connected with the series connection in the novel double-frequency output matching circuitTransmission line T1The other end of (a);
series transmission line T16The other ends of the transmission lines are respectively connected with the parallel open-circuit transmission lines T17And a series transmission line T18One end of (a);
parallel open circuit transmission line T17Is in an open circuit state;
series transmission line T18Respectively connected to a drain bias voltage VDCapacitor C5And a fan-shaped open-circuit transmission line T19One end of (a);
capacitor C5And the other end of the same is grounded.
Compared with the prior art, the novel harmonic control circuit provided by the invention has scientific structural design, can accurately control the second harmonic impedance of two frequency points, can improve the precision of double-frequency harmonic impedance matching, and has great practical significance.
In addition, the invention provides the double-frequency fundamental wave impedance matching circuit and provides the matched analytic solution, so that the double-frequency fundamental wave impedance matching circuit has convenient parameter calculation and smaller size, and realizes good matching of fundamental wave impedance;
in addition, the invention can solve the problem of complex circuit of the existing double-frequency amplifier, can realize the high-efficiency purpose only by controlling fundamental wave and second harmonic, and greatly reduces the complexity of the circuit.
Drawings
Fig. 1 is a circuit structure diagram of a dual-frequency harmonic tuning high-efficiency power amplifier provided by the invention;
fig. 2 is a schematic diagram of a novel harmonic control circuit (i.e., a second harmonic impedance matching circuit) in a dual-frequency harmonic tuning high-efficiency power amplifier provided by the present invention;
fig. 3 is a schematic diagram of a novel dual-frequency output matching circuit (i.e., a dual-frequency fundamental impedance matching circuit) in a dual-frequency harmonic tuning high-efficiency power amplifier provided by the present invention;
fig. 4 is a graphical illustration of the power amplifier PAE, gain and output power of the present invention as a function of frequency;
fig. 5 is a graph illustrating the variation of the input power with respect to the gain and the output power of the power amplifier PAE according to the present invention.
Detailed Description
In order to make the technical means for realizing the invention easier to understand, the following detailed description of the present application is made in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the present application are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Referring to fig. 1 to 5, the present invention provides a dual-frequency harmonic tuning high-efficiency power amplifier, which comprises a load impedance RL1Circuit input terminal, transistor Q, circuit output terminal and load impedance RL2；
Wherein, the circuit input includes: a dual-frequency input matching circuit 101, an RC stabilizing circuit 102 and a grid dual-frequency bias circuit 103;
load impedance RL1One end of (specifically, a 50 Ω load) is connected to one end of the dual-frequency input matching circuit 101;
load impedance RL1The other end of the first and second electrodes is grounded;
the other end of the dual-frequency input matching circuit 101 is respectively connected with one end of the RC stable circuit 102 and one end of the grid dual-frequency bias circuit 103;
the other end of the RC stabilizing circuit 102 is connected with a grid G of the transistor Q;
wherein, the source S of the transistor Q is grounded;
the dual-frequency input matching circuit 101 is located at the load impedance RL1And an RC stabilizing circuit, wherein the RC stabilizing circuit 102 is positioned between the grid double-frequency bias circuit 103 and the transistor Q; gridThe polar dual-frequency bias circuit 103 is positioned between the dual-frequency input matching circuit 101 and the RC stable circuit 102;
it should be further noted that the dual-frequency input matching circuit 101 functions as: the optimal source impedance of transistor Q is matched to a 50 Ω load. The RC stabilizing circuit 102, which functions to ensure the amplifier operates in a steady state gate dual frequency bias circuit 103, functions to provide the proper gate bias for the amplifier while ensuring an open circuit at both operating frequencies to prevent rf signal leakage.
Wherein, the circuit output includes: a drain double-frequency bias circuit 201, a novel harmonic control circuit 202 and a novel double-frequency output matching circuit 203;
one end of the novel harmonic control circuit 202 is connected with a drain D of the transistor Q;
the other end of the novel harmonic control circuit 202 is connected with one end of the novel double-frequency output matching circuit 203;
a novel dual-frequency output matching circuit 203, which is also respectively connected with one end of the drain dual-frequency bias circuit 201 and the load impedance RL2One end of (specifically 50 Ω load) is connected;
load impedance RL2And the other end of the same is grounded.
It should be noted that the drain dual-frequency bias circuit 201 is used to provide a proper drain bias voltage for the amplifier.
In the present invention, a gallium nitride high electron mobility transistor 40010F manufactured by cree corporation is used as the transistor Q.
In the present invention, for the specific implementation, see fig. 1, wherein the dual-frequency input matching circuit 101 comprises a series transmission line T12Capacitor C2Series transmission line T13Parallel open circuit transmission line T14And a series transmission line T15；
Series transmission line T12Is connected to a load impedance RL1(specifically 50 Ω load);
series transmission line T12The other end of (1) through a capacitor C2Connecting series transmission lines T13One end of (a);
series transmission line T13The other ends of the transmission lines are respectively connected with the parallel open-circuit transmission lines T14And a series transmission line T15One end of (a);
parallel open circuit transmission line T14Is in an open circuit state;
wherein the RC stabilizing circuit 102 comprises capacitors C connected in parallel1And a resistance R1；
Capacitor C1And a resistance R1One end of the parallel circuit is connected to the series transmission line T in the dual-frequency input matching circuit 10115The other end of (a);
capacitor C1And a resistance R1The other end of the parallel circuit is connected with a grid G of the transistor Q;
wherein the gate dual-frequency bias circuit 103 comprises a series transmission line T5Capacitor C4Series transmission line T7Parallel open circuit transmission line T6And a sector open circuit transmission line T8；
Series transmission line T5Is connected to the series transmission line T in the dual-frequency input matching circuit 10115The other end of (a);
series transmission line T5The other ends of the transmission lines are respectively connected with the parallel open-circuit transmission lines T6And a series transmission line T7One end of (a);
parallel open circuit transmission line T6Is in an open circuit state;
series transmission line T7Respectively connected to a gate bias voltage VG(voltage is-2.8V) and a capacitor C4And a fan-shaped open-circuit transmission line T8One end of (a);
capacitor C4And the other end of the same is grounded.
In the present invention, referring to fig. 2, a novel harmonic control circuit 202, including a series transmission line T, is provided9Parallel open circuit transmission line T10And a parallel open circuit transmission line T11；
Series transmission line T9Is connected to the drain D of transistor Q;
series transmission line T9Respectively connected to the parallel open-circuit transmission line T10And a parallel open-circuit transmission line T11One end of (a);
parallel open circuit transmission line T10And the other end of the parallel open circuit transmission line T11The other ends of the two-way valve are all in an open circuit state;
referring to fig. 3, the novel dual-frequency output matching circuit 203 comprises a series transmission line T1Series transmission line T3Series transmission line T4And a parallel open circuit transmission line T2；
Wherein the transmission line T is connected in series1Is connected to the series transmission line T in the novel harmonic control circuit 2029The other end of (a);
series transmission line T1The other ends of the transmission lines are respectively connected with the parallel open-circuit transmission lines T2And a series transmission line T3One end of (a);
series transmission line T3The other end of the capacitor is connected with a DC blocking capacitor C3One end of (a);
blocking capacitor C3Is connected to the series transmission line T4One end of (a);
series transmission line T4The other end of the connecting line is connected with a load impedance RL2。
In particular, referring to fig. 1, the drain dual-frequency bias circuit 201 includes a series transmission line T16Series transmission line T18Parallel open circuit transmission line T17And a sector open circuit transmission line T19；
Wherein the transmission line T is connected in series16Is connected to the series transmission line T in the novel dual-frequency output matching circuit 2031The other end of (a);
series transmission line T16The other ends of the transmission lines are respectively connected with the parallel open-circuit transmission lines T17And a series transmission line T18One end of (a);
parallel open circuit transmission line T17Is in an open circuit state;
series transmission line T18Respectively connected to a drain bias voltage VD(voltage is 28V) and a capacitor C5And a fan-shaped open-circuit transmission line T19One end of (a);
capacitor C5And the other end of the same is grounded.
It should be noted that, for the novel harmonic control circuit 202, the parallel open-circuit transmission line T is connected10Has an electrical length of 2f1At a frequency of 90 deg., so as to be at node a (i.e. series transmission line T)9And a parallel open circuit transmission line T10Parallel open circuit transmission line T11The connecting node of the three) to form 2f1And (4) short-circuiting. Parallel open circuit transmission line T11Has an electrical length of 2f2At a frequency of 90 deg., to form 2f at point A2And (4) short-circuiting.
Thus, for the novel harmonic control circuit 202, by adjusting T10Characteristic impedance and electrical length of and transmission line T10、T11Can be adjusted to 2f at point A1And 2f2Is matched to the optimum second harmonic impedance load of transistor Q.
It should be noted that, for the novel dual-frequency output matching circuit 203, the transmission line T is connected in series1Responsible for connecting the node A point (i.e. the series transmission line T)9And a parallel open circuit transmission line T10Parallel open circuit transmission line T11The connection node of the three) is connected with the first and second frequency sensors; parallel open circuit transmission line T2Connected in series transmission line T1And T3To cancel reactance at two frequencies;
series transmission line T3And T4The functions of the method are as follows: connecting node B point (i.e. series transmission line T)1And a parallel open circuit transmission line T2Series transmission line T3The connection node of the three) to a 50 omega load.
In the present invention, for specific implementation, referring to fig. 2, fig. 2 is a schematic diagram of a second harmonic impedance matching circuit (i.e. a novel harmonic control circuit 202) proposed by the present invention;
wherein the transmission line T is connected in series9One end of the transistor is connected with the drain electrode of the transistor, and the other end is connected with the parallel open-circuit transmission line T10And T11. Parallel open circuit transmission line T10One end is connected with T11And the other end is in an open circuit state. Parallel open circuit transmission line T11One end is connected with T10And the other end is in an open circuit state. The specific operation of the novel harmonic control circuit 202 is as follows:
one, parallel open circuit transmission line T10Has an electrical length of 2f1At a frequency of 90 deg., thereby forming a short circuit at node a.
Two, parallel open circuit transmission line T11Has an electrical length of 2f2At a frequency of 90 deg., thereby forming a short circuit at node a.
Three, series transmission line T9Has a characteristic impedance of Z0Electrical length of theta1(at f)1At frequency). The function of the impedance matching circuit is to match the short circuit state of the node A point sum to the optimal second harmonic impedance of the transistor, and the matching principle is shown in the following formulas (1) and (2):
ZL(2f1)＝jZ0tan(2θ1) Formula (1);
ZL(2f2)＝jZ0tan(2mθ1) Equation (2);
wherein m ═ f2/f1And Z isL(2f1)、ZL(2f2) The optimal second harmonic impedance of the transistor at two frequencies is shown, and in practical design, the optimal second harmonic impedance is obtained by carrying out harmonic load traction on the transistor Q. Solving the above formula to obtain the series transmission line T9Characteristic impedance and electrical length. At this point, the harmonic impedance matching is completed.
In the present invention, referring to fig. 3 for specific implementation, fig. 3 is a schematic diagram of a dual-frequency fundamental impedance matching circuit (i.e. a novel dual-frequency output matching circuit 203) according to the present invention, and a series transmission line T is connected to the dual-frequency fundamental impedance matching circuit1One end is connected with a series transmission line T9The other end is connected with a series transmission line T3. Series transmission line T3One end and a series transmission line T1Connected with another end of the DC blocking capacitor C3And (4) connecting. Series transmission line T4One end and a DC blocking capacitor C3And the other end is connected with a 50 omega load. Parallel open circuit transmission line T2Connected in series transmission line T1And T3In the meantime. The specific working mode is as follows:
one, series transmission line T1Optimum fundamental impedance at two frequencies at node A point
Into a pair of conjugate complex impedances.
As shown in FIG. 3, the impedance seen at the BB' surface is denoted by ZBAnd then:
in the above formula, ZB(f1)、ZB(f2) Represents the impedance seen at two frequencies of the BB' plane; z1Is a series transmission line T1Characteristic impedance of (Z)A(f1)、ZA(f2) Represents the optimum fundamental impedance at two frequencies at point A, θ1Is a series transmission line T1Electrical length of (c). m ═ f2/f1Refers to the frequency ratio.
The impedance of the two frequency points is complex conjugate, namely: zB(f1)＝ZB(f2)*. Solving the equation to obtain:
in the above-mentioned formula, the first and second,RA1、RA2representing the real part, X, of the optimum fundamental impedance at two frequencies at point AA1、XA2Representing the imaginary parts of the best fundamental impedance at the two frequencies at point a. Z1Is a series transmission line T1Characteristic impedance of theta1Is a series transmission line T1Electrical length of (c). m ═ f2/f1Refers to the frequency ratio. n denotes an integer (0,1,2 … …).
From the above, it can be seen that the admittances of the two frequencies of the BB 'plane (which is merely for convenience of explanation and may be defined as the reference plane BB') are: y isB(f1)＝GB－jBB、YB(f2)＝GB－jBBOpen circuit transmission line T2To cancel susceptance at two frequencies
Its characteristic impedance Z2And electrical length theta2The requirements are as follows:
in the above formula, BBRepresenting the corresponding susceptance at the reference plane of BB'. Z2Is a parallel open circuit transmission line T2Characteristic impedance of theta2Is a parallel open circuit transmission line T2Electrical length of (c). m ═ f2/f1Refers to the frequency ratio.
Solving equations (7) and (8) yields:
impedance of two frequencies via transmission line T2After matching, all real impedances R are at point B.
Three, series transmission line T3And T4Is used for matching the real impedance R at the point B to the load
This section adopts the reference [6 ]]Of the transmission line T3And T4The characteristic impedance and the electrical length of (a) are required to satisfy:
in the above formula, Z3Is a series transmission line T3Characteristic impedance of theta3Is a series transmission line T3Electrical length of (c). Z4Is a series transmission line T4Characteristic impedance of theta4Is a series transmission line T4Electrical length of (c). m ═ f2/f1And refers to the frequency ratio. R refers to the real impedance at point B. RLRefers to the load RL2。
For the present invention, a dual-frequency power amplifier operating at 1.9/2.6GHz is designed according to the above embodiment, and the PAE, output power and gain variation curve with frequency is shown in fig. 4, and the PAE, output power and gain variation curve with input power is shown in fig. 5. It can be seen that the designed double-frequency harmonic tuning high-efficiency power amplifier shows obvious double-frequency characteristics. When the amplifier works at 1.9GHz, the maximum PAE which can be realized is 72.9 percent, and the maximum output power is 39.8 dBm; when the amplifier works at 2.6GHz, the maximum PAE which can be realized is 71.4 percent, and the maximum output power is 41.4 dBm.
It should be noted that, for the novel dual-frequency harmonic tuning high-efficiency power amplifier provided by the present invention, the efficiency of the power amplifier is improved by using the novel harmonic control circuit 202 and the novel dual-frequency fundamental wave matching circuit (i.e., the novel dual-frequency output matching circuit 203). Based on the structural design, the efficiency of the double-frequency amplifier working at 1.9GHz/2.6GHz can reach 72.9%/71.4%, the gains of the two frequency bands are both larger than 10dB, the output power is about 40dBm, and the performance is balanced, so that the double-frequency amplifier can accurately realize double-frequency matching and has great reference significance for the subsequent design of a double-frequency high-efficiency amplifier.
Compared with the prior art, the novel harmonic control circuit provided by the invention has scientific structural design, accurately controls the second harmonic impedance of two frequency points, can improve the precision of double-frequency harmonic impedance matching, and has great practical significance.
In addition, the invention provides the double-frequency fundamental wave impedance matching circuit and provides the matched analytic solution, so that the double-frequency fundamental wave impedance matching circuit has convenient parameter calculation and smaller size, and realizes good matching of fundamental wave impedance;
in addition, the invention can solve the problem of complex circuit of the existing double-frequency amplifier, can realize the high-efficiency purpose only by controlling fundamental wave and second harmonic, and greatly reduces the complexity of the circuit.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (7)
1. A double-frequency harmonic tuning high-efficiency power amplifier is characterized by comprising a load impedance RL1Circuit input terminal, transistor Q, circuit output terminal and load impedance RL2；
Wherein, the circuit input includes: the circuit comprises a dual-frequency input matching circuit (101), an RC (resistance capacitance) stabilizing circuit (102) and a grid dual-frequency biasing circuit (103);
load impedance RL1One end of the dual-frequency input matching circuit (101) is connected with one end of the dual-frequency input matching circuit;
load impedance RL1The other end of the first and second electrodes is grounded;
the other end of the dual-frequency input matching circuit (101) is respectively connected with one end of the RC stabilizing circuit (102) and one end of the grid dual-frequency bias circuit (103);
the other end of the RC stabilizing circuit (102) is connected with a grid G of the transistor Q;
wherein, the source S of the transistor Q is grounded;
wherein, the circuit output includes: a drain double-frequency bias circuit (201), a novel harmonic control circuit (202) and a novel double-frequency output matching circuit (203);
one end of the novel harmonic control circuit (202) is connected with a drain D of the transistor Q;
the other end of the novel harmonic control circuit (202) is connected with one end of a novel double-frequency output matching circuit (203);
a novel dual-frequency output matching circuit (203) which is also respectively connected with one end of the drain dual-frequency bias circuit (201) and the load impedance RL2One end of the two ends are connected;
load impedance RL2And the other end of the same is grounded.
2. The dual-frequency harmonically-tuned high-efficiency power amplifier of claim 1, wherein the dual-frequency input matching circuit (101) comprises a series transmission line T12Capacitor C2Series transmission line T13Parallel open circuit transmission line T14And a series transmission line T15；
Series transmission line T12Is connected to a load impedance RL1One end of (a);
series transmission line T12The other end of (1) through a capacitor C2Connecting series transmission lines T13One end of (a);
series transmission line T13The other ends of the transmission lines are respectively connected with the parallel open-circuit transmission lines T14And is connected in series toTransmission line T15One end of (a);
parallel open circuit transmission line T14The other end of the same is in an open state.
3. The dual-frequency harmonically-tuned high-efficiency power amplifier of claim 2, wherein the RC stabilization circuit (102) comprises capacitors C connected in parallel with each other1And a resistance R1；
Capacitor C1And a resistance R1One end of the parallel circuit is connected with a series transmission line T in the dual-frequency input matching circuit (101)15The other end of (a);
capacitor C1And a resistance R1The other end of the parallel circuit is connected with a grid G of the transistor Q;
4. the dual-frequency harmonically-tuned high-efficiency power amplifier of claim 2, wherein the gate dual-frequency bias circuit (103) comprises a series transmission line T5Capacitor C4Series transmission line T7Parallel open circuit transmission line T6And a sector open circuit transmission line T8；
Series transmission line T5Is connected to the series transmission line T in the dual-frequency input matching circuit (101)15The other end of (a);
series transmission line T5The other ends of the transmission lines are respectively connected with the parallel open-circuit transmission lines T6And a series transmission line T7One end of (a);
parallel open circuit transmission line T6Is in an open circuit state;
series transmission line T7Respectively connected to a gate bias voltage VGCapacitor C4And a fan-shaped open-circuit transmission line T8One end of (a);
capacitor C4And the other end of the same is grounded.
5. The dual-frequency harmonically tuned high efficiency power amplifier of claim 1, wherein the novel harmonic control circuit (202) comprises a series transmission line T9Parallel open circuit transmission line T10And a parallel open circuit transmission line T11；
Series transmission line T9Is connected to the drain D of transistor Q;
series transmission line T9Respectively connected to the parallel open-circuit transmission line T10And a parallel open-circuit transmission line T11One end of (a);
parallel open circuit transmission line T10And the other end of the parallel open circuit transmission line T11The other ends of the two-way valve are all in an open circuit state;
6. the dual-frequency harmonically tuned high efficiency power amplifier of claim 5, wherein the novel dual-frequency output matching circuit (203) comprises a series transmission line T1Series transmission line T3Series transmission line T4And a parallel open circuit transmission line T2；
Wherein the transmission line T is connected in series1Is connected to the series transmission line T9The other end of (a);
series transmission line T1The other ends of the transmission lines are respectively connected with the parallel open-circuit transmission lines T2And a series transmission line T3One end of (a);
series transmission line T3The other end of the capacitor is connected with a DC blocking capacitor C3One end of (a);
blocking capacitor C3Is connected to the series transmission line T4One end of (a);
series transmission line T4The other end of the connecting line is connected with a load impedance RL2。
7. The dual-frequency harmonically tuned high efficiency power amplifier of claim 6, wherein the drain dual-frequency bias circuit (201) comprises a series transmission line T16Series transmission line T18Parallel open circuit transmission line T17And a sector open circuit transmission line T19；
Wherein the transmission line T is connected in series16One end of the novel dual-frequency output matching circuit (203) is connected with a series transmission line T in the novel dual-frequency output matching circuit (203)1To another one ofA terminal;
series transmission line T16The other ends of the transmission lines are respectively connected with the parallel open-circuit transmission lines T17And a series transmission line T18One end of (a);
parallel open circuit transmission line T17Is in an open circuit state;
series transmission line T18Respectively connected to a drain bias voltage VDCapacitor C5And a fan-shaped open-circuit transmission line T19One end of (a);
capacitor C5And the other end of the same is grounded.
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|---|---|---|---|---|
| CN113346844A (en) * | 2021-05-25 | 2021-09-03 | 天津大学 | class-F efficient Doherty power amplifier |
| CN113794448A (en) * | 2021-08-18 | 2021-12-14 | 华南理工大学 | Tuned double-frequency matching power amplifier |
| CN115694380A (en) * | 2022-10-30 | 2023-02-03 | 北京航空航天大学 | Double-frequency broadband power amplifier and matching branch design method thereof |
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| CN109194297A (en) * | 2018-09-20 | 2019-01-11 | 天津大学 | A kind of double frequency-band high-efficient E type power amplifier |
| CN109525208A (en) * | 2018-10-18 | 2019-03-26 | 天津大学 | A kind of novel double-frequency band high efficiency power amplifier based on harmonic controling |
| CN109546977A (en) * | 2018-10-18 | 2019-03-29 | 天津大学 | A kind of double frequency-band efficient reverse F power-like amplifier |
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| CN109525208A (en) * | 2018-10-18 | 2019-03-26 | 天津大学 | A kind of novel double-frequency band high efficiency power amplifier based on harmonic controling |
| CN109546977A (en) * | 2018-10-18 | 2019-03-29 | 天津大学 | A kind of double frequency-band efficient reverse F power-like amplifier |
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