CN112309866A - Semiconductor device and preparation method thereof - Google Patents

Semiconductor device and preparation method thereof Download PDF

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Publication number
CN112309866A
CN112309866A CN201910710352.9A CN201910710352A CN112309866A CN 112309866 A CN112309866 A CN 112309866A CN 201910710352 A CN201910710352 A CN 201910710352A CN 112309866 A CN112309866 A CN 112309866A
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source
drain
semiconductor device
ion implantation
semiconductor substrate
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刘佑铭
贾超超
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SiEn Qingdao Integrated Circuits Co Ltd
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SiEn Qingdao Integrated Circuits Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a semiconductor device and a preparation method thereof, wherein the method comprises the following steps: forming a semiconductor device on a semiconductor substrate, the semiconductor device including a source and a drain; performing ion implantation on the source electrode and the drain electrode, wherein the ion implantation is inclination angle ion implantation; and performing a fusion laser anneal on the semiconductor device to induce stress in the semiconductor device. The method and the MOSFET prepared by the method can introduce stress into the MOSFET without preparing a stress memory layer, so that the preparation process is simple and convenient, and the cost is low. In the ion implantation process, the silicon in the source/drain region is amorphized to form amorphous silicon; and the melting laser annealing can repair the damage of the semiconductor substrate caused by the ion implantation, and can form a perfect grain boundary between the source/drain region and the semiconductor substrate, thereby forming stress between the bag-shaped source/drain region and the semiconductor substrate.

Description

Semiconductor device and preparation method thereof
Technical Field
The invention relates to the field of semiconductor devices, in particular to a MOSFET and a preparation method thereof.
Background
With the development of integrated circuit technology, the size of chips and components, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), therein is getting smaller. However, as the size of the MOSFET decreases, the performance of the semiconductor material and the device performance of the MOSFET may both deteriorate.
To reduce on-resistance in a MOSFET and increase the switching speed of the device, a suitable stress may be applied to the channel region of the MOSFET to increase the mobility of carriers. In the case of an n-type mosfet (nmos), applying tensile stress to a channel region in a longitudinal direction of the channel region may improve mobility of electrons as carriers; in the case of a p-type mosfet (pmos), applying a compressive stress to a channel region in a longitudinal direction of a channel may improve mobility of holes as carriers.
Therefore, how to simply and conveniently increase the stress of the channel region and to recrystallize the amorphous silicon formed by ion implantation into perfect crystalline silicon is a technical problem to be solved in the art.
Disclosure of Invention
The embodiment of the invention provides a MOSFET and a preparation method thereof, which aim to solve the technical problems in the prior art.
According to a first aspect, embodiments of the present invention provide a method for manufacturing a semiconductor device, the method including the steps of:
forming a semiconductor device on a semiconductor substrate, the semiconductor device including a source and a drain;
performing ion implantation on the source electrode and the drain electrode, wherein the ion implantation is inclination angle ion implantation; and
performing a fusion laser anneal on the semiconductor device to induce stress in the semiconductor device.
Optionally, the semiconductor device comprises a MOSFET.
Optionally, the semiconductor device comprises NMOS and/or PMOS.
Optionally, the performing ion implantation on the source and the drain includes implanting one or more of Ge, Sn, and Sb into the source and the drain of the PMOS.
Optionally, the performing ion implantation on the source and the drain includes performing ion implantation C on the source and the drain of the NMOS.
Optionally, the source and the drain are ion-implanted to form a rectangular or bag-shaped ion-implanted region.
Optionally, the dose range of the ion implantation performed on the source and the drain is 1 × 1014/cm3To 1X 1017/cm3In the meantime.
Optionally, the energy range for ion implantation of the source and drain is 2keV to 100 keV.
Optionally, the tilt angle of the tilt angle ion implantation is an included angle between an implantation direction of the ion beam and a vertical direction, and the angle range of the tilt angle is 5 to 60 °.
Optionally, the angle of inclination is in the range 30-45 °.
Optionally, the PMOS is masked with a mask and the exposed NMOS is subjected to the ion implantation.
Optionally, SiC is formed at the source and drain of the NMOS.
Optionally, the NMOS is masked with a mask and the ion implantation is performed on the exposed PMOS.
Optionally, one or more of SiSn, SiGe and SiSb are formed on the source and drain of the PMOS.
Optionally, the melting laser annealing comprises laser spike annealing LSA.
Optionally, the power range of the laser in the melting laser annealing is 0.1J/cm2To 10J/cm2。
Optionally, the duration of the laser in the melting laser annealing is 10ns to 1000 ns.
The invention also provides a semiconductor device prepared by any one of the methods.
Optionally, the semiconductor device further includes: a device isolation region and a gate stack formed on the semiconductor substrate; and a sidewall disposed around the gate stack.
Optionally, the semiconductor device further includes a gate reoxidation layer disposed between the gate stack and the sidewall.
The method and the MOSFET prepared by the method can introduce stress into the MOSFET without preparing a stress memory layer, so that the preparation process is simple and convenient, and the cost is low. In the ion implantation process, the silicon in the source/drain region is amorphized to form amorphous silicon, and the doped ions can form a hypersolid solution; and the melting laser annealing can repair the damage of the semiconductor substrate caused by ion implantation, can form perfect ion implantation crystalline silicon on the source/drain region, and can also form a perfect grain boundary between the source/drain region and the semiconductor substrate, thereby forming stress between the bag-shaped source/drain region and the semiconductor substrate.
Drawings
The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and not to be construed as limiting the invention in any way, and in which:
fig. 1 shows a schematic diagram of a stress formation method used for a 40nm process.
Fig. 2 shows a schematic diagram of a stress formation method used for a 28nm process.
Fig. 3 is a schematic diagram of the fabrication of a MOSFET according to the present invention.
Fig. 4 is a flow chart showing a method of manufacturing a MOSFET according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1-2 show a schematic diagram of a stress forming method used in a conventional 40nm process and a conventional 28nm process. Fig. 1 shows a schematic diagram of a stress forming method used in a 40nm process, and as shown in fig. 1(a), a shallow trench isolation 102 is first formed on a semiconductor substrate 101, a gate stack composed of a gate dielectric 105 and a gate conductor 103 is formed on the semiconductor substrate 101, and a sidewall 104 is further formed on the periphery of the gate stack. Etching the semiconductor substrate 101 by taking the shallow trench isolation 102, the gate conductor 103 and the side walls 104 as hard masks, so as to form openings 106 at positions of the semiconductor substrate 101 corresponding to the source region and the drain region; in addition, source/drain extensions 107 are also formed in the semiconductor substrate 101 below the gate dielectric 105. After the opening 106 is formed, as shown in fig. 1(b), a semiconductor layer 109 is epitaxially grown on the exposed surface of the semiconductor substrate 101 within the opening to form a source/drain region. The material of the semiconductor substrate 101 may be Si, and the commonly used material of the source/drain regions 109 is SiGe. After forming the source/drain regions, silicidation is performed on the surface of the semiconductor layer 109 to form a metal silicide layer 110 to reduce the contact resistance of the source/drain regions, as shown in fig. 1 (c). The silicidation process may include the following steps: depositing a Ni layer with the thickness of 5-20nm, then carrying out heat treatment at the temperature of 300-500 ℃ to form NiSi on the surface part of the semiconductor layer 109, and finally removing the unreacted Ni by wet etching.
Fig. 2 shows a schematic diagram of a stress formation method used for a 28nm process. As shown in fig. 2, a shallow trench isolation 202 is formed on a semiconductor substrate 201, an NFET region and a PFET region are formed on the semiconductor substrate 201 by the shallow trench isolation 202, and a gate structure 203 composed of a gate stack and a sidewall is formed on the semiconductor substrate 201. Then, a buffer layer 204 and a stress memorization thin film layer 205 are formed on the gate structure 203 in the NFET region, the NFET is masked with photoresist and the photoresist is patterned to expose the PFET, the buffer layer 204 and the stress memorization thin film layer 205 in the PFET region are etched, and the semiconductor substrate 201 in the PFET region is etched to a certain depth to form a trench. The etching is generally an anisotropic wet etching, and the epitaxial growth layer 206 is formed in the trench formed by the etching. The material of the epitaxial layer 206 may be SiGe. The above-described embedded SiGe epitaxial growth layers 206 are disposed in the source and drain regions of the PFET device, which is subjected to compressive strain, thereby improving hole mobility in the PFET device, increasing switching speed of the PFET device, and the like. Masking of the NFET during the growth process of the SiGe epitaxial growth layer 206 is necessary to ensure that the SiGe does not affect the device performance of the NFET, as compressive strain in the NFET source and drain regions can degrade electron mobility and thus degrade the performance of the NFET.
However, the above two processes are not satisfactory for manufacturing MOS devices with a thickness of 28nm or less, and have problems of complicated manufacturing process, high cost due to excessive thin film materials used, and the like.
Fig. 3 is a schematic diagram of a MOSFET manufactured according to the present invention, and fig. 4 is a flowchart of a MOSFET manufacturing method according to the present invention. The method of fabricating the MOSFET is described in detail below with reference to fig. 3-4.
The invention provides a MOSFET preparation method, which comprises the following steps:
and S1, forming a gate stack.
In this step, as shown in fig. 3(a), a device isolation region 304 and a gate stack are formed on a semiconductor substrate 301. Wherein the semiconductor substrate 301 comprises bulk silicon or other suitable material, such as silicon-on-insulator (SOI), the semiconductor substrate 301 may be lightly doped. The device isolation region 304 may be, for example, a Shallow Trench Isolation (STI) structure. Forming the gate stack further includes forming a gate dielectric layer (not shown) on the semiconductor substrate 301. The gate dielectric layer can be made of dielectric materials such as silicon oxide and silicon oxynitride; taking silicon oxide as an example, it can be formed by a thermal oxidation method.
The gate stack includes a gate dielectric layer 303, a gate electrode layer 305, and a gate reoxidation layer 306. In addition, spacers 307 are also formed outside the gate stack. The gate stack includes a dummy gate structure that may be removed in a subsequent process and replaced with a metal gate.
The process of forming the gate stack may include the following processes:
step one, a gate electrode layer is formed on the gate dielectric layer 303, and the gate electrode layer can be made of polysilicon. The polysilicon may be formed by a method such as Chemical Vapor Deposition (CVD). Forming a mask layer on the gate electrode layer, wherein the mask layer can be a hard mask, for example, a hard mask made of silicon nitride material; the silicon nitride may be formed by a method such as chemical vapor deposition. After the mask layer is formed, the mask layer is etched to form a mask pattern for defining the shapes of gate electrode layers and gate dielectric layers 303 of subsequently formed NMOS and PMOS devices. With the mask pattern as a mask, the gate electrode layer and the gate dielectric layer 303 are sequentially etched to form gate stacks of the patterned gate electrode layer 305 and the gate dielectric layer 303 of the NMOS device and the PMOS device, respectively. The etching may be a dry etching method. And removing the mask pattern after the etching is finished.
And step two, performing a gate reoxidation process to form a gate reoxidation layer 306 on the surface of the semiconductor substrate 301 and the surfaces of the gate stack structures of the NMOS device and the PMOS device. The oxide layer formed in the reoxidation process is mainly used to repair damage to the gate electrode layer 305 and the gate dielectric layer 303 when the gate electrode layer 305 and the gate dielectric layer 303 are etched. In the gate reoxidation process, dry oxygen oxidation can be adopted, and pure oxygen gas atmosphere without hydrogen is adopted, and the temperature for carrying out the oxidation reaction is also controlled at a lower temperature. In one embodiment, the flow rate of the oxygen in the gate reoxidation process may be 2-15 liters/minute and the temperature may be 650-800 ℃.
And step three, forming a side wall 307 outside the gate stack. The method for forming the sidewall 307 includes: forming a side wall material, etching the side wall material, cleaning by a wet method, removing the residual side wall material, and forming a side wall 307 outside the gate stack. The sidewall 307 includes oxynitride.
And S2, performing ion implantation.
In this step, as shown in fig. 3(b), a photoresist 308 is formed on the semiconductor substrate 301 and the gate stack, the photoresist in the NFET region or the PFET region is removed to expose the gate stack structure and a portion of the gate dielectric layer 303 therein, and a high dose tilt angle ion implantation 309 is performed on the semiconductor substrate 301 under the exposed portion of the gate dielectric layer 303, so as to form a pocket source/drain region 310 in the semiconductor substrate 301, and then the excess photoresist 308 is removed.
To create compressive or tensile stress, C, Sn, Ge and/or Sb ions may be implanted in a step where a high dose of angled ion implantation 309 is performed.
In one particular embodiment, C is selectively implanted into the source and drain regions of the NFET to form SiC. More specifically, carbon is implanted into the Si of the NFET source/drain regions. The SiC in the pocket source/drain region 310 can create a tensile stress in the NFET, thereby increasing the mobility of carriers in the NFET and thus increasing the switching speed, etc., of the NFET. During the carbon implant, a photoresist 308 is applied over the PFET so that the PFET is masked to block the carbon implant to the source and drain regions of the PFET.
In another specific embodiment, one or a combination of Sn, Ge, and Sb is selectively implanted into source and drain regions of the PFET to form SiSn, SiGe, SiSb. More specifically, Sn, Ge, and/or Sb are implanted into the Si of the PFET source/drain regions. The SiSn, SiGe and SiSb in the pocket source/drain region 310 can form compressive stress in the PFET, so that the mobility of carriers in the PFET is improved, and the switching speed and other performances of the PFET are improved. During the implantation of Sn, Ge and/or Sb, a photoresist 308 is applied over the NFET so that the NFET is masked to block the implantation of carbon into the source and drain regions of the NFET.
In another specific embodiment, the semiconductor device comprises a CMOS, i.e., including a PFET and an NFET, respectively, the PFET and NFET are ion implanted by selectively implanting one or a combination of Sn, Ge, and Sb into source and drain regions of the PFET to form SiSn, SiGe, SiSb, and selectively implanting C into source and drain regions of the NFET to form SiC.
The energy level of the ion implantation in the high dose angled ion implantation 309 may be about 2keV to 100keV and the implant dose may be 1 x 1014/cm3And 1X 1017/cm3In the meantime. The inclination angle is an included angle between the implantation direction of the ion beam and the vertical direction, and the angle range of the inclination angle is 5-60 degrees, and is preferably 30-45 degrees.
In the above ion implantation process, silicon in the pocket-shaped source/drain regions 310 is amorphized to form amorphous silicon, and the dopant ions may form a hypersolid solution.
Selecting an appropriate tilt angle for ion implantation may also form rectangular source/drain regions 310.
And S3, melting and laser annealing.
In this step, as shown in fig. 3(c), the MOSFET device is subjected to fusion laser annealing. The fusion laser anneal may be a Laser Spike Anneal (LSA) at temperatures up to 1400 ℃. The power of the laser in the melting laser annealing is adjusted according to the depth of the melting annealing, and the power range can be 0.1J/cm2To 10J/cm2. Different laser durations are selected depending on the optimal diffusion length, which may be 10ns to 1000 ns. In a specific embodiment, the fusion laser anneal is an anneal at about 1300 ℃ to 1400 ℃ for a very short duration, e.g., about one millisecond. The melting laser annealing may melt the pouch-shaped source/drain regions 310; however, the melting laser annealing is not enough to melt the semiconductor substrate 301 of Si having a melting point of about 1410 ℃. In this way, the fusion laser anneal does not damage the device.
The fusion laser annealing may allow the semiconductor substrate 301 to be repaired from damage due to the ion implantation, and may allow the pocket source/drain regions 310 to form perfect ion-implanted crystalline silicon, and may also allow a perfect grain boundary to be formed between the pocket source/drain regions 310 and the semiconductor substrate 301, thereby forming stress between the pocket source/drain regions 310 and the semiconductor substrate 301.
And S4, subsequent processing.
In this step, in order to form a metal gate, a step of removing the gate electrode layer 305 and the gate dielectric layer with a mask formed, and then depositing a high-k gate dielectric layer, a metal gate, and the like is further included. The above steps are well known to those skilled in the art and will not be described herein.
The method and the MOSFET prepared by the method can introduce stress into the MOSFET without preparing a stress memory layer, so that the preparation process is simple and convenient, and the cost is low. In the above ion implantation process, silicon in the source/drain region 310 is amorphized to form amorphous silicon, and the dopant ions may form a hypersolid solution; and the melting laser annealing can repair the damage of the semiconductor substrate 301 due to the ion implantation, and can form perfect ion-implanted crystalline silicon for the source/drain regions 310, and can also form perfect grain boundaries between the source/drain regions 310 and the semiconductor substrate 301, thereby forming stress between the pocket-shaped source/drain regions 310 and the semiconductor substrate 301.
The foregoing embodiments are merely illustrative of the principles of this invention and its efficacy, rather than limiting it, and various modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention, which is defined in the appended claims.

Claims (20)

1. A method of fabricating a semiconductor device, the method comprising the steps of:
forming a semiconductor device on a semiconductor substrate, the semiconductor device including a source and a drain;
performing ion implantation on the source electrode and the drain electrode, wherein the ion implantation is inclination angle ion implantation; and
performing a fusion laser anneal on the semiconductor device to induce stress in the semiconductor device.
2. The method of claim 1, wherein the semiconductor device comprises a MOSFET.
3. The method of claim 2, wherein the semiconductor device comprises an NMOS and/or a PMOS.
4. The method of any one of claims 1-3, wherein the ion implanting the source and drain comprises implanting one or more of Ge, Sn, and Sb into the source and drain of a PMOS.
5. The method of any of claims 1-3, wherein the ion implanting the source and drain comprises implanting C the source and drain of an NMOS.
6. A method according to any of claims 1-3, wherein the source and drain are ion implanted to form rectangular or pocket shaped ion implanted regions.
7. A method according to any of claims 1-3, wherein the source and drain are ion implanted in a dose range of 1 x 1014/cm3To 1X 1017/cm3In the meantime.
8. A method according to any of claims 1-3, characterized in that the energy for the ion implantation of the source and drain is in the range of 2keV to 100 keV.
9. The method according to any of claims 1-3, wherein the tilt angle of the tilt angle ion implantation is an angle between an implantation direction of the ion beam and a vertical direction, and the tilt angle is in a range of 5-60 °.
10. A method according to claim 9, wherein the angle of inclination is in the range 30-45 °.
11. The method of claim 3 wherein the ion implantation is performed on the exposed NMOS using a mask to cover the PMOS.
12. The method of claim 11, wherein SiC is formed at the source and drain of the NMOS.
13. The method of claim 3 wherein the ion implantation is performed on the exposed PMOS by masking the NMOS.
14. The method of claim 13, wherein a combination of one or more of SiSn, SiGe, and SiSb is formed at the source and drain of the PMOS.
15. The method of any of claims 1-3, wherein the melting laser annealing comprises Laser Spike Annealing (LSA).
16. The method of any of claims 1-3, wherein the power of the laser in the fusion laser annealing is in the range of 0.1J/cm2To 10J/cm2。
17. The method of any of claims 1-3, wherein the duration of the laser in the fusion laser anneal is from 10ns to 1000 ns.
18. A semiconductor device, characterized in that it is produced by a method according to any one of claims 1 to 17.
19. The semiconductor device according to claim 18, further comprising: a device isolation region and a gate stack formed on the semiconductor substrate; and a sidewall disposed around the gate stack.
20. The semiconductor device of claim 19, further comprising a gate reoxidation layer disposed between the gate stack and the sidewall spacers.
CN201910710352.9A 2019-08-02 2019-08-02 Semiconductor device and preparation method thereof Pending CN112309866A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241929A (en) * 2007-02-08 2008-08-13 国际商业机器公司 Semiconductor structure and method of forming the structure
CN101359685A (en) * 2007-07-31 2009-02-04 国际商业机器公司 Semiconductor device and method of manufacture
CN101925987A (en) * 2008-01-21 2010-12-22 德克萨斯仪器股份有限公司 Method for forming strained channel PMOS devices and integrated circuits therefrom
CN102157379A (en) * 2010-02-11 2011-08-17 中国科学院微电子研究所 High-performance semiconductor device and manufacturing method thereof
CN103594495A (en) * 2012-08-16 2014-02-19 中国科学院微电子研究所 semiconductor device and making method thereof
CN109427584A (en) * 2017-08-29 2019-03-05 中芯国际集成电路制造(上海)有限公司 A kind of manufacturing method and semiconductor devices of semiconductor devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241929A (en) * 2007-02-08 2008-08-13 国际商业机器公司 Semiconductor structure and method of forming the structure
CN101359685A (en) * 2007-07-31 2009-02-04 国际商业机器公司 Semiconductor device and method of manufacture
CN101925987A (en) * 2008-01-21 2010-12-22 德克萨斯仪器股份有限公司 Method for forming strained channel PMOS devices and integrated circuits therefrom
CN102157379A (en) * 2010-02-11 2011-08-17 中国科学院微电子研究所 High-performance semiconductor device and manufacturing method thereof
CN103594495A (en) * 2012-08-16 2014-02-19 中国科学院微电子研究所 semiconductor device and making method thereof
CN109427584A (en) * 2017-08-29 2019-03-05 中芯国际集成电路制造(上海)有限公司 A kind of manufacturing method and semiconductor devices of semiconductor devices

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