CN112306882A - Chip algorithm module verification method and system based on C algorithm model - Google Patents
Chip algorithm module verification method and system based on C algorithm model Download PDFInfo
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Abstract
The application discloses a chip algorithm module verification method based on a C algorithm model, wherein related functional modules are developed by expanding the existing C algorithm model, and the C algorithm model is properly matched with hardware implementation of an algorithm on the premise of ensuring the functions of the original C algorithm model, so that the C algorithm model is easy to integrate into a verification environment. The transmission between the verification environment and the C model is realized through a DPI-C interface, so that the running of the verification case is completely automatic. Meanwhile, files are not used as transmission media between the C model and the verification environment in the testing process, and storage space is saved. Because the C model is independently compiled, the development and debugging of the C model are independent of a verification platform, the verification efficiency is improved, the C algorithm model source code does not need to be provided for verification personnel, and the confidentiality of the algorithm code is ensured. In addition, the application also provides a chip algorithm module verification system based on the C algorithm model, and the technical effect of the chip algorithm module verification system corresponds to that of the method.
Description
Technical Field
The application relates to the technical field of computers, in particular to a chip algorithm module verification method and system based on a C algorithm model.
Background
The chip verification is an important link in the chip development process, and the complexity of the chip verification is higher and higher along with the larger and larger chip scale. For a chip for realizing the algorithm function, a large amount of data needs to be processed or many complex operations need to be performed, the processed result is greatly different from the original input data, and a corresponding algorithm model is needed to be used as a reference when an algorithm module is verified.
The algorithm model is generally implemented by using a high-level language, and there are several implementation methods in general:
the method 1 is characterized in that a verification language such as System Verilog is used for realizing an algorithm model, the algorithm model is integrated into a verification environment, the output result of a chip algorithm module and the output result of the algorithm model can be compared in real time in the operation process of a verification case, and the correctness of the result is judged.
And 2, realizing an algorithm model by using a non-verification language, processing the input data based on the algorithm model to generate a corresponding result, and respectively storing the input data and the corresponding result into an input data file and a reference result file. And reading data from the input data file as an excitation in the running process of the verification case, injecting the data into the chip algorithm module, storing an output result of the chip algorithm module into an output result file, and judging the correctness of the result by comparing the contents of the output result file and the reference result file after the running of the verification case is finished.
And 3, realizing an algorithm model by using a C language, independently compiling the C algorithm model into an executable file, running the executable file in a System Verilog through a $ System function when a verification case runs, simultaneously transmitting input data into the executable file in a pre-agreed mode, writing a result generated by the executable file into a reference file, storing an output result of the chip algorithm module into a result file, and judging the correctness of the result by comparing the contents of the result file and the reference file after the verification case runs.
And 4, realizing the algorithm model by using C language, importing the C algorithm model into a verification environment through a DPI-C interface of a System Verilog and C, and compiling together with the verification environment. In the operation process of the verification case, besides the input data are injected into the chip algorithm module, the imported C interface function is called at the same time, the input data are input into the C algorithm module, the reference result is calculated, and the correctness of the result is judged by comparing the output result of the chip algorithm module with the reference result output by the C algorithm module.
The method 1 can realize real-time online comparison, but has the obvious defect that the existing algorithm model cannot be reused, and the verification language is required to be used for secondary development, so that the additional cost is increased.
The method 2 has the disadvantages that the generation of the reference result is independent from the operation process of the verification case, and the file is used as a data transmission medium to transmit data, so that the method has the disadvantages that automatic verification is not easy to realize, and the quantity of files to be stored is increased along with the increase of the excitation range, and a large amount of extra storage space is required to be occupied.
Although the above method 3 integrates the operation of the algorithm model into the verification environment, which can be controlled by the verification use case, it still needs to use the file as the medium to transfer the result, and the disadvantage is the same as the above method 2.
The method 4 needs to compile the reference model and the verification environment together, needs to put the algorithm source code into the verification environment, and packages the DPI-C interface on the basis of the algorithm model by a verifier, and has two disadvantages, namely, the algorithm model is integrated into the verification environment, and when the verification case fails to operate and needs to locate problems through the comparison of the algorithm intermediate process, the algorithm model is not easy to debug independently and needs additional auxiliary means; secondly, the confidentiality of the algorithm code cannot be guaranteed when cooperating with a third party.
In summary, in the current verification scheme for the chip algorithm module, the source code of the algorithm model is required to be disclosed, and the confidentiality of the algorithm code cannot be ensured; or the file is used as a data transmission medium, and a large storage space is occupied; or the existing algorithm model cannot be reused, and the development cost is increased.
Disclosure of Invention
The invention aims to provide a chip algorithm module verification method and a chip algorithm module verification system based on a C algorithm model, which are used for multiplexing the existing C algorithm model and realizing the automatic verification of the chip algorithm module under the conditions that a C algorithm model source code is not provided externally and a file is not used as a data transmission medium. The specific scheme is as follows:
in a first aspect, the present application provides a chip algorithm module verification method based on a C algorithm model, including:
the verification case module randomly generates configuration information on line according to the constraint condition, and transmits the configuration information to the excitation generator through the first DPI-C interface;
the stimulus generator generates a stimulus according to the configuration information, transmits the stimulus to the first format conversion module, and transmits the stimulus after format conversion to the verification case module through the first DPI-C interface;
the verification case module transmits the configuration information and the excitation after the format conversion to a chip algorithm module respectively; the chip algorithm module generates an actual result and transmits the actual result to the checker;
capturing the configuration information and the excitation after the format conversion from an input port of a chip algorithm model, transmitting the configuration information to a C algorithm model through a second DPI-C interface, transmitting the excitation after the format conversion to a second format conversion module through the second DPI-C interface, and transmitting the excitation after the format conversion again to the C algorithm model; the C algorithm model generates a reference result, transmits the reference result to a third format conversion module, and transmits the reference result after format conversion to the inspector through a third DPI-C interface;
the checker judges whether the actual result is consistent with the reference result, if so, the operation of the verification case is successful;
wherein the first DPI-C interface, the second DPI-C interface and the third DPI-C interface are transmission interfaces between a C model and a verification environment; the C model is obtained by taking the C algorithm model as a core extension and comprises the C algorithm model, an excitation generator, a first format conversion module, a second format conversion module and a third format conversion module; c, independently compiling the model in advance;
the first format conversion module is used for converting the stimulus into a data format suitable for hardware processing, the second format conversion module is used for converting the stimulus into a data format suitable for C algorithm model processing, and the third format conversion module is used for converting the result into a data format suitable for hardware processing.
Preferably, the method further comprises the following steps:
when the actual result is inconsistent with the reference result, starting a file storage function through a dynamic switch;
storing the excitation after the format conversion into an excitation file; storing the reference result after the format conversion into a reference result file;
storing the actual result into an actual result file;
and reproducing the verification process according to the excitation file, the reference result file and the actual result file, and positioning the problems.
Preferably, the stimulus after the format conversion is saved in a stimulus file; storing the reference result after the format conversion into a reference result file, wherein the method comprises the following steps:
storing the original excitation and the excitation after the format conversion into an original excitation file and an excitation file respectively; storing the original reference result or the reference result after format conversion into an original reference result file and a reference result file respectively;
judging whether the format conversion of the excitation is normal or not according to the original excitation file and the excitation file; and judging whether the format conversion of the reference file is normal or not according to the original reference result file and the reference result file.
Preferably, the online random configuration information generation by the verification use case module according to the constraint condition includes:
the verification use case module randomly generates configuration information on line according to the constraint condition, wherein the configuration information comprises any one or more of the following items: task type, data block number, data block size, random seed.
Preferably, before the verification use case module randomly generates the configuration information online according to the constraint condition, the method further includes:
expanding the C algorithm model into a C model;
compiling the C model;
creating a transmission interface between the C model and the verification environment;
the C model is integrated into the verification environment.
Preferably, the compiling the C model includes:
compiling and linking all source codes except the test routine in the C model into a target file, compiling the codes of the test routine, linking the target file and generating an executable file.
Preferably, the creating a transmission interface between the C model and the verification environment includes:
creating a DPI-C interface for transmitting the configuration information from the verification case module to the stimulus generator and transmitting the stimulus after format conversion from the first format conversion module to the verification case module to obtain a first DPI-C interface;
creating a DPI-C interface for transmitting configuration information from an input port of an algorithm module chip to a C algorithm model and transmitting the excitation after format conversion from the input port of the algorithm module chip to a second format conversion module to obtain a second DPI-C interface;
and creating a DPI-C interface for transmitting the format-converted reference result from the third format conversion module to the inspector to obtain a third DPI-C interface.
Preferably, the integrating the C model into the verification environment includes:
compiling a link C algorithm model to generate a library file; and linking the library file when the verification case is run, and adding a target parameter in the command line parameter.
Preferably, the method further comprises the following steps:
the coverage rate collector performs coverage rate analysis and determines uncovered configuration according to the analysis result; and according to the uncovered configuration, modifying the constraint conditions in the verification case module, or creating a new verification case and sending the new verification case to the verification case module.
In a second aspect, the present application provides a chip algorithm module verification system based on a C algorithm model, including: the system comprises an algorithm model C, a chip algorithm module, a verification case module, a stimulus generator, a first format conversion module, a second format conversion module, a third format conversion module and a checker;
the verification case module is used for randomly generating configuration information on line according to constraint conditions and transmitting the configuration information to the excitation generator through the first DPI-C interface;
the stimulus generator is used for generating stimulus according to the configuration information and transmitting the stimulus to the first format conversion module, and the stimulus after format conversion is transmitted to the verification case module through the first DPI-C interface;
the verification case module is used for respectively transmitting the configuration information and the excitation after the format conversion to the chip algorithm module; the chip algorithm module is used for generating an actual result and transmitting the actual result to the checker;
capturing the configuration information and the excitation after the format conversion from an input port of a chip algorithm model, transmitting the configuration information to a C algorithm model through a second DPI-C interface, transmitting the excitation after the format conversion to a second format conversion module through the second DPI-C interface, and transmitting the excitation after the format conversion again to the C algorithm model; the C algorithm model is used for generating a reference result, transmitting the reference result to a third format conversion module, and transmitting the reference result after format conversion to the inspector through a third DPI-C interface;
the checker is used for judging whether the actual result is consistent with the reference result or not, and if so, the verification case is indicated to be operated successfully;
wherein the first DPI-C interface, the second DPI-C interface and the third DPI-C interface are transmission interfaces between a C model and a verification environment; the C model is obtained by taking the C algorithm model as a core extension and comprises the C algorithm model, an excitation generator, a first format conversion module, a second format conversion module and a third format conversion module; c, independently compiling the model in advance;
the first format conversion module is used for converting the stimulus into a data format suitable for hardware processing, the second format conversion module is used for converting the stimulus into a data format suitable for C algorithm model processing, and the third format conversion module is used for converting the result into a data format suitable for hardware processing.
According to the chip algorithm module verification method based on the C algorithm model, the existing C algorithm model is expanded to develop the related functional module, and the C algorithm model is properly matched with the hardware implementation of the algorithm on the premise of ensuring the functions of the original C algorithm model, so that the C algorithm model is easily integrated into a verification environment. The transmission between the verification environment and the C model is realized through a DPI-C interface, so that the running of the verification case is completely automatic. Meanwhile, files are not used as transmission media between the C model and the verification environment in the testing process, and storage space is saved. Because the C model is independently compiled, the development and debugging of the C model are independent of a verification platform, the verification efficiency is improved, the C algorithm model source code does not need to be provided for verification personnel, and the confidentiality of the algorithm code is ensured.
In addition, the application also provides a chip algorithm module verification system based on the C algorithm model, the technical effect of the chip algorithm module verification system corresponds to that of the method, and the details are not repeated here.
Drawings
For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart of a first embodiment of a chip algorithm module verification method based on a C algorithm model provided in the present application;
fig. 2 is a schematic view of a verification environment of a first embodiment of a chip algorithm module verification method based on a C algorithm model provided in the present application;
FIG. 3 is a flow chart of the overall authentication process provided by the present application;
FIG. 4 is a flow diagram of a file save function provided herein;
figure 5 is a flow chart of a DPI-C interface creation process provided herein;
fig. 6 is a schematic diagram of a C model in a second embodiment of the chip algorithm module verification method based on the C algorithm model provided in the present application;
fig. 7 is a schematic view of a verification environment of a second embodiment of the chip algorithm module verification method based on the C algorithm model provided in the present application.
Detailed Description
The core of the application is to provide a chip algorithm module verification method and system based on a C algorithm model, and the C algorithm model is integrated into a verification environment through function expansion of the C algorithm model. In the verification process, data transmission between the C model and the verification environment is realized through the DPI-C interface, automatic operation of the verification case is realized, a file is not used as a transmission medium between the C model and the verification environment, and the storage space is saved. Moreover, because the C model is independently compiled, the development and debugging of the C model are independent of a verification platform, and the C algorithm model source code does not need to be provided for a verifier.
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The following describes a first embodiment of a chip algorithm module verification method based on a C algorithm model provided in the present application. Referring to fig. 1 and 2, an embodiment includes:
s101, the verification case module randomly generates configuration information on line according to constraint conditions, and transmits the configuration information to an excitation generator through a first DPI-C interface;
the DPI-C interface, the direct programming interface C, is a programming mode for direct interaction between System Verilog (a hardware design and verification language, SV for short) and C.
S102, the stimulus generator generates a stimulus according to the configuration information, transmits the stimulus to the first format conversion module, and transmits the stimulus after format conversion to the verification case module through the first DPI-C interface;
s103, the verification case module transmits the configuration information and the excitation after format conversion to the chip algorithm module respectively; the chip algorithm module generates an actual result and transmits the actual result to the checker;
s104, capturing the configuration information and the excitation after the format conversion from an input port of the chip algorithm model, transmitting the configuration information to the C algorithm model through a second DPI-C interface, transmitting the excitation after the format conversion to a second format conversion module through the second DPI-C interface, and transmitting the excitation after the format conversion to the C algorithm model again; the C algorithm model generates a reference result, transmits the reference result to a third format conversion module, and transmits the reference result after format conversion to the inspector through a third DPI-C interface;
specifically, a monitor is arranged in the verification platform, the monitor is used for monitoring whether the verification case module transmits the configuration information and the excitation after format conversion to the chip algorithm module, and if so, the configuration information and the excitation after format conversion are captured from the input port of the chip algorithm module.
S105, the checker judges whether the actual result is consistent with the reference result, and if so, the running of the verification case is successful; otherwise, the verification case is failed to operate. And when all the verification cases of the chip algorithm module are successfully operated, the chip algorithm module is verified.
Verification is a process for checking whether the function of chip design is correct, and a verification case and a verification environment are two elements of chip verification. In the verification process, an algorithm model is needed, the algorithm model uses a high-level language to realize the function and the algorithm of the circuit, the function is firstly verified in the software algorithm verification, and in the chip verification, the algorithm model is used as a reference standard for detecting whether the chip design is correct or not. In this embodiment, the C algorithm model is used as a reference model in the verification process of the chip algorithm module.
For convenience of distinction, the original C algorithm model is referred to as a C algorithm model in this embodiment, and a model obtained by adding related functional modules to the original C algorithm model and expanding the added related functional modules is referred to as a C model.
Before executing verification, the C algorithm model is taken as a core, related functional modules are developed, matching of the C algorithm model and hardware is realized, and the independent operation function of the C algorithm model is reserved to obtain the C model. Independently compiling the C model into a cmodel.o file, providing the cmodel.o file and a C model API function statement to a verifier, developing a corresponding DPI-C interface function by the verifier based on the C model API, compiling DPI-C interface codes and linking the cmodel.o file of the C model, and generating a library file containing a DPI-C interface. And when the verification case runs, the library file is linked, and the C model and the verification environment are organically combined by calling a related DPI-C interface and using the corresponding function of the C model, so that the automatic verification of the chip algorithm module is realized.
In summary, as shown in fig. 3, the whole verification process includes:
s301, expanding the C algorithm model into a C model;
s302, compiling the C model;
s303, establishing a transmission interface between the C model and a verification environment;
s304, integrating the C model into a verification environment;
s305, executing the verification workflow, namely S101 to S105.
In this embodiment, the first DPI-C interface, the second DPI-C interface, and the third DPI-C interface are transmission interfaces between the C model and the verification environment. The C model obtained based on the C algorithm model expansion specifically comprises: the device comprises a C algorithm model, an excitation generator, a first format conversion module, a second format conversion module and a third format conversion module. Each format conversion module is used for converting data from a data format suitable for hardware processing into a data format suitable for C algorithm model processing, or converting data from a data format suitable for C algorithm model processing into a data format suitable for hardware processing.
For an algorithm, the goal of its processing is either a large amount of arbitrary data, or target data that meets certain rules, or both. The range of the former stimulus is usually large, and the generation rule of the latter stimulus varies greatly depending on the complexity of the algorithm. For the algorithm with a large excitation range, a method for generating the excitation in advance needs to store a large amount of data, and for the algorithm with a complex excitation generation rule, a method for generating the excitation in a verification platform in a simple constraint mode is not easy. In consideration of the particularity of the algorithm excitation, the present embodiment adopts C language to implement the excitation generator, and develops and debugs together with the C algorithm model.
The embodiment can realize the automatic verification of the chip algorithm module without generating an intermediate file. In the regression testing process, if there is a case that the operation of the verification case fails, only the result can be seen, but the corresponding excitation cannot be known, but the excitation in this embodiment is randomly generated under a certain constraint condition, and is difficult to completely reproduce. Therefore, in the present embodiment, a dynamic switch of the file saving function is provided, and in order to save the storage space, the dynamic switch is turned off by default, and when the verification fails, the dynamic switch may be turned on. After the regression test is started, the C model saves the excitation and reference results into a file, and the verification platform also saves the actual results of the chip algorithm module into the file, so that after the regression test is finished, the excitation and results of all verification cases which fail to operate can be saved into the corresponding files, and the problems can be conveniently reproduced and positioned by verification personnel.
Therefore, as shown in fig. 4, as a preferred embodiment, this embodiment further includes:
s401, when the actual result is inconsistent with the reference result, starting a file saving function through a dynamic switch;
s402, storing the excitation after the format conversion into an excitation file, and storing the reference result after the format conversion into a reference result file;
s403, storing the actual result into an actual result file;
s404, reproducing the verification process according to the excitation file, the reference result file and the actual result file, and positioning the problem.
On the basis, it can be considered that the stimulus before and after the format conversion and the result before and after the format conversion are simultaneously saved, so that whether the relevant format conversion module has an error or not can be checked. Therefore, the step S402 may specifically be: respectively storing the original excitation and the excitation after format conversion into an original excitation file and an excitation file; storing the original reference result or the reference result after format conversion into an original reference result file and a reference result file respectively; judging whether the format conversion of the excitation is normal or not according to the original excitation file and the excitation file, namely judging whether the first format conversion module is normal or not; and judging whether the format conversion of the reference file is normal or not according to the original reference result file and the reference result file, namely judging whether the third format conversion module is normal or not.
In some specific embodiments, the compiling the C model specifically includes: compiling and linking all source codes except the test routine in the C model into a target file, compiling the codes of the test routine, linking the target file and generating an executable file.
As shown in fig. 5, in some specific embodiments, the process of creating a transmission interface between the C model and the verification environment specifically includes:
s501, creating a DPI-C interface which is used for transmitting the configuration information from the verification case module to the stimulus generator and transmitting the stimulus after format conversion from the first format conversion module to the verification case module to obtain a first DPI-C interface;
s502, creating a DPI-C interface for transmitting the configuration information from the input port of the algorithm module chip to the C algorithm model and transmitting the excitation after format conversion from the input port of the algorithm module chip to the second format conversion module to obtain a second DPI-C interface;
s503, a DPI-C interface used for transmitting the reference result after the format conversion from the third format conversion module to the inspector is created, and a third DPI-C interface is obtained.
In some specific embodiments, the integrating the C model into the verification environment specifically includes: compiling a link C algorithm model to generate a library file; and linking the library file when the verification case is operated, and adding a target parameter in the command line parameter.
The chip algorithm module verification method based on the C algorithm model provided by the embodiment develops related functional modules by expanding the existing C algorithm model, and appropriately matches the C algorithm model with the hardware implementation of the algorithm on the premise of ensuring the functions of the original C algorithm model, so that the C algorithm model is easily integrated into a verification environment. The transmission between the verification environment and the C model is realized through a DPI-C interface, so that the running of the verification case is completely automatic. Meanwhile, files are not used as transmission media between the C model and the verification environment in the testing process, and storage space is saved. Because the C model is independently compiled, the development and debugging of the C model are independent of a verification platform, the verification efficiency is improved, the C algorithm model source code does not need to be provided for verification personnel, and the confidentiality of the algorithm code is ensured.
The second embodiment of the chip algorithm module verification method based on the C algorithm model provided by the present application is described in detail below. The second embodiment is an example of practical application, and the whole verification process shown in fig. 3 is described in detail, and the second embodiment adds a coverage collector relative to the first embodiment.
The main functions of the coverage collector are: performing coverage analysis, and determining uncovered configuration according to the analysis result; and according to the uncovered configuration, modifying the constraint conditions in the verification case module, or creating a new verification case and sending the new verification case to the verification case module.
The embodiment connects the C model with the verification environment through the DPI-C interface, and realizes the automatic operation of the verification case and the automatic comparison of the result under the condition that a file is not used as a data transmission medium. Referring to fig. 3 and 7, the implementation of the second embodiment is as follows:
s301, expanding the C algorithm model into a C model.
And the C algorithm model is expanded, related functional modules are added, and the matching with hardware is realized while the C algorithm model is ensured to be capable of independently running and easy to debug, so that the C algorithm model is easy to integrate into a verification environment. The C algorithm model extension is shown in fig. 6, where the dashed box and dashed arrow indicate optional functions that can be enabled or disabled by dynamic switching control. The model C specifically comprises:
(1) and the test routine module is used for receiving the input parameters as the configuration information of the algorithm.
(2) And the excitation generator generates corresponding excitation according to the configuration information and the rule required by the algorithm.
(3) And the C algorithm model, namely the existing verified C algorithm model, is used for receiving the configuration information and the excitation, and processing the excitation according to the configuration information and the rule required by the algorithm to obtain a corresponding result as a reference result of the algorithm.
(4) And the format conversion module is used for enabling the excitation generated by the excitation generator to be suitable for the C algorithm model, and hardware needs to perform parallel processing on a plurality of groups of excitation according to a specific mode in order to utilize the advantages of the hardware to the maximum extent so as to improve the performance of the hardware algorithm. The format conversion module is used for realizing conversion between excitation or results of different data formats, and comprises: a format conversion module 1 (i.e., the aforementioned first format conversion module) for converting the excitation format suitable for the C algorithm model into an excitation format suitable for hardware processing; a format conversion module 2 (i.e., the aforementioned second format conversion module) for converting the excitation format suitable for hardware processing into an excitation format suitable for the C algorithm model; and the format conversion module 3 (namely the third format conversion module) is used for converting the result generated by the C algorithm model into a result which is consistent with the actual output format of the hardware.
(5) And the file storage module is used for respectively storing the excitation generated by the excitation generator and the reference result generated by the C algorithm model into an original excitation file and an original result file, and storing the excitation and reference results which are converted by the format conversion module 1 and the format conversion module 3 and are consistent with the hardware processing format in the format conversion module into the corresponding excitation file and result file.
It can be understood that the file saving module is mainly used for developing and verifying the initial debugging stage, and by comparing the excitation or the result before and after the format conversion, whether the excitation is correctly injected into the chip algorithm module can be visually checked, and whether the result output by the chip algorithm module is consistent with the result saved in the file or not can be visually checked. After the verification environment is stable, the file storage module can be forbidden in the process of performing regression testing through a large number of verification cases, so that a large number of files are prevented from being generated, and excessive extra storage space is occupied.
S302, compiling the C model.
Compiling the C model to generate a cmodel.o file for verification and a cmodel _ tool executable file for debugging functions, which are specifically as follows:
(1) all source code in the C model except the test routine is compiled and linked into a cmodel.o file, with the commands exemplified as follows:
gcc$(CFLAGS)-c stimulus.c
gcc$(CFLAGS)-c algo_core.c
gcc$(CFLAGS)-c convert.c
gcc$(CFLAGS)-c file_op.c
ld-r-o cmodel.o stimulus.o algo_core.o convert.o file_op.o
wherein stimulus.c is an excitation generator source code file, algo _ core.c is a C algorithm model source code file, convert.c is a format conversion module source code file, and file _ op.c is a file storage module source code file.
(2) Compiling test routine codes and linking the generated cmodel.o files to generate an executable file, wherein commands are exemplified as follows:
gcc$(CFLAGS)-c test.c
gcc-o cmodel_tool test.o cmodel.o
the test.c is a test routine code file, the cmodel _ tool is an executable file, and the executable file is mainly used for developing a debugging stage at the initial stage of verification and verifying and debugging a verification case with operation failure in a regression testing process at the later stage.
S303, creating a transmission interface between the C model and the verification environment.
Namely, a DPI-C interface is developed, and the specific steps are as follows:
(1) a first DPI-C interface is developed for passing configuration information from the verification environment to the stimulus generator and passing the stimulus converted by the format conversion module 1 back to the DPI-C interface function of the verification environment, as an example:
void dpi_gen_stimulus(const algo_config_t*cfg,svOpenArrayHandle hdata)；
the cfg is a pointer of an algo _ config _ t type of a configuration information structure body, contains configuration information, is transmitted to the C model by the System Verilog, and the hdata is a variable of an open array svOpenArrayHandle type, is filled and excited by the C model, and is transmitted back to the System Verilog.
(2) A second DPI-C interface is developed for the DPI-C interface functions that pass configuration information and stimuli to the C-algorithm model and drive the C-algorithm model into operation, examples of which are as follows:
void dpi_algo_start(const algo_config_t*cfg,const svOpenArrayHandle hdata)；
the cfg is a variable of an algo _ config _ t type of a configuration information structure body, the cfg contains configuration information, the hdata is a variable of an open array svopenarraywandle type, and the two variables are both transmitted to the C model by System Verilog.
(3) A third DPI-C interface is developed for passing the result converted by the format conversion module 3 from the C model to the DPI-C interface of the verification environment, for example as follows:
void dpi_get_ref_result(const algo_config_t*cfg,svOpenArrayHandle hresult)；
the cfg is a variable of an algo _ config _ t type of a configuration information structure body, contains configuration information, is transmitted to the C model by the System Verilog, and hresult is a variable of an open array svOpenArrayHandle type, is filled with a reference result by the C model, and is transmitted back to the System Verilog.
And S304, integrating the C model into a verification environment.
The method comprises the following specific steps:
(1) compiling the link C algorithm model to generate a library file, with the commands exemplified as follows:
gcc$(CFLAGS)-fPIC-c dpi_c_if.c
gcc-fPIC-shared-o dpi_c_lib.so dpi_c_if.o cmodel.o
and the DPI _ C _ if.c is a DPI-C interface source code file, and the DPI _ C _ lib.so is a generated library file.
(2) When the verification case is run, the library file is linked, and the following parameters are added to the command line parameters, for example:
-sv_lib dpi_c_lib
s305, executing a verification workflow.
Fig. 6 shows a structure diagram of a verification environment integrated with a C model, where the verification process is as follows:
(1) generating configuration information: configuration information required by the algorithm is generated through reasonable constraint conditions in the verification environment, and the configuration information comprises information such as task types, data block quantity, data block sizes and random seeds.
(2) Transmitting the configuration information to a stimulus generator, and transmitting the stimulus subjected to format conversion to a verification case module: and packaging the generated configuration information according to a predefined data format to be used as a parameter of the DPI-C interface, transmitting the parameter to the stimulus generator through the DPI-C interface, starting the stimulus generator to generate a stimulus, converting the stimulus through the format conversion module 1, and transmitting the converted stimulus back to the verification case module.
(3) Injecting stimuli into a chip algorithm module: and respectively injecting the configuration information and the excitation into the chip algorithm module through corresponding interfaces to drive the chip algorithm module to start working.
(4) Pass excitation to model C: the monitor captures configuration information and excitation from the input port of the chip algorithm module, transmits the configuration information and the excitation to the C model through the DPI-C interface, and transmits the configuration information and the excitation to the C algorithm model after being converted by the format conversion module 2.
(5) Comparing the reference result with an actual result output by the chip algorithm module: the checker acquires the reference result generated by the C algorithm model and converted by the format conversion module 3 through the DPI-C interface, reads data from the reference result in sequence after receiving the actual result output by the chip algorithm module, and compares the actual result output by the chip algorithm module with the reference result one by one. If the verification case is inconsistent, the verification case is indicated to fail to operate; and if all the results of the verification use case are consistent with the reference result, the verification use case is successfully operated. And when all the verification cases of the chip algorithm module are successfully operated, the verification of the chip algorithm module is passed.
(6) Collecting coverage rate information, and creating a corresponding verification case for the uncovered configuration: when the verification use cases are successfully operated, the coverage rate information is recorded, when all the verification use cases are successfully operated, the coverage rate collector analyzes the coverage rate information to check which configurations are not covered, creates corresponding verification use cases or modifies constraint conditions aiming at the configurations which are not covered, then operates again and collects the coverage rate information, and the coverage rate is improved through continuous iteration until all the configurations are covered.
It can be seen that the chip algorithm module verification method based on the C algorithm model provided by this embodiment has at least the following four advantages:
the method has the advantages that 1, the C algorithm model is properly matched with hardware, the C algorithm model is integrated into a UVM (universal verification methodology) verification environment through a DPI-C interface, and the System Verilog calls the related functions of the C model to realize the automatic operation of the verification case and the online comparison of the result.
The method has the advantages that 2, during regression testing, files are not used as data transmission media of the verification case and the C model, namely, excitation files and result files do not need to be generated, when the excitation range and the number of the algorithm are large, the used files often occupy a large amount of extra storage space, and the advantages of the embodiment are obvious.
The method has the advantages that by collecting and analyzing the coverage rate information, the uncovered condition can be found in time, the constraint condition can be modified or a new verification case can be created conveniently aiming at the uncovered condition, the verification coverage rate is improved by continuous iteration, the completeness of verification is ensured, and the method cannot be completed in a verification mode of generating the excitation in advance.
Advantage 4, independently compile the C model into the cmodel.o file, provide the verifier with algorithm API interface together, be used for encapsulating DPI-C interface, therefore the development debugging of C model is independent of the verification platform, and the benefit of bringing has: on one hand, the method has the advantages of layered development, algorithm personnel are dedicated to the development of the algorithm, verification personnel are dedicated to the development of the verification platform and the verification case, and if the output result of the chip algorithm module is inconsistent with the output result of the C algorithm model in the running process of the verification case, the algorithm personnel and the verification personnel can independently debug the respective module based on the same configuration and excitation respectively, so that the problem of the module per se can be rapidly confirmed or eliminated; on the other hand, there is no need to provide the verifier with the C-algorithm model source code, which has a clear advantage in terms of code confidentiality when working with a third party.
The chip algorithm module verification system based on the C algorithm model provided in the embodiments of the present application is introduced below, and a chip algorithm module verification system based on the C algorithm model described below and a chip algorithm module verification method based on the C algorithm model described above may be referred to in correspondence with each other.
As shown in fig. 2, the chip algorithm module verification system based on the C algorithm model of this embodiment includes: the system comprises an algorithm model C, a chip algorithm module, a verification case module, a stimulus generator, a first format conversion module, a second format conversion module, a third format conversion module and a checker.
The verification case module is used for randomly generating configuration information on line according to the constraint condition and transmitting the configuration information to the excitation generator through the first DPI-C interface;
the stimulus generator is used for generating stimulus according to the configuration information and transmitting the stimulus to the first format conversion module, and the stimulus after format conversion is transmitted to the verification case module through the first DPI-C interface;
the verification case module is used for respectively transmitting the configuration information and the excitation after the format conversion to the chip algorithm module; the chip algorithm module is used for generating an actual result and transmitting the actual result to the checker;
capturing the configuration information and the excitation after the format conversion from an input port of a chip algorithm model, transmitting the configuration information to a C algorithm model through a second DPI-C interface, transmitting the excitation after the format conversion to a second format conversion module through the second DPI-C interface, and transmitting the excitation after the format conversion again to the C algorithm model; the C algorithm model is used for generating a reference result, transmitting the reference result to a third format conversion module, and transmitting the reference result after format conversion to the inspector through a third DPI-C interface;
the checker is used for judging whether the actual result is consistent with the reference result or not, and if so, the verification case is successfully operated;
the first DPI-C interface, the second DPI-C interface and the third DPI-C interface are transmission interfaces between a C model and a verification environment; the C model is a model obtained by taking the C algorithm model as core extension and comprises the C algorithm model, an excitation generator, a first format conversion module, a second format conversion module and a third format conversion module; c, independently compiling the model in advance;
the first format conversion module is used for converting the excitation into a data format suitable for hardware processing, the second format conversion module is used for converting the excitation into a data format suitable for C algorithm model processing, and the third format conversion module is used for converting the result into a data format suitable for hardware processing.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above detailed descriptions of the solutions provided in the present application, and the specific examples applied herein are set forth to explain the principles and implementations of the present application, and the above descriptions of the examples are only used to help understand the method and its core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A chip algorithm module verification method based on a C algorithm model is characterized by comprising the following steps:
the verification case module randomly generates configuration information on line according to the constraint condition, and transmits the configuration information to the excitation generator through the first DPI-C interface;
the stimulus generator generates a stimulus according to the configuration information, transmits the stimulus to the first format conversion module, and transmits the stimulus after format conversion to the verification case module through the first DPI-C interface;
the verification case module transmits the configuration information and the excitation after the format conversion to a chip algorithm module respectively; the chip algorithm module generates an actual result and transmits the actual result to the checker;
capturing the configuration information and the excitation after the format conversion from an input port of a chip algorithm model, transmitting the configuration information to a C algorithm model through a second DPI-C interface, transmitting the excitation after the format conversion to a second format conversion module through the second DPI-C interface, and transmitting the excitation after the format conversion again to the C algorithm model; the C algorithm model generates a reference result, transmits the reference result to a third format conversion module, and transmits the reference result after format conversion to the inspector through a third DPI-C interface;
the checker judges whether the actual result is consistent with the reference result, if so, the operation of the verification case is successful;
wherein the first DPI-C interface, the second DPI-C interface and the third DPI-C interface are transmission interfaces between a C model and a verification environment; the C model is obtained by taking the C algorithm model as a core extension and comprises the C algorithm model, an excitation generator, a first format conversion module, a second format conversion module and a third format conversion module; c, independently compiling the model in advance;
the first format conversion module is used for converting the stimulus into a data format suitable for hardware processing, the second format conversion module is used for converting the stimulus into a data format suitable for C algorithm model processing, and the third format conversion module is used for converting the result into a data format suitable for hardware processing.
2. The method of claim 1, further comprising:
when the actual result is inconsistent with the reference result, starting a file storage function through a dynamic switch;
storing the excitation after the format conversion into an excitation file; storing the reference result after the format conversion into a reference result file;
storing the actual result into an actual result file;
and reproducing the verification process according to the excitation file, the reference result file and the actual result file, and positioning the problems.
3. The method of claim 2, wherein the format-converted stimulus is saved to a stimulus file; storing the reference result after the format conversion into a reference result file, wherein the method comprises the following steps:
storing the original excitation and the excitation after the format conversion into an original excitation file and an excitation file respectively; storing the original reference result or the reference result after format conversion into an original reference result file and a reference result file respectively;
judging whether the format conversion of the excitation is normal or not according to the original excitation file and the excitation file; and judging whether the format conversion of the reference file is normal or not according to the original reference result file and the reference result file.
4. The method of claim 1, wherein the verification use case module randomly generates the configuration information online according to a constraint condition, comprising:
the verification use case module randomly generates configuration information on line according to the constraint condition, wherein the configuration information comprises any one or more of the following items: task type, data block number, data block size, random seed.
5. The method of claim 1, wherein before the verification use case module randomly generates the configuration information online according to the constraint condition, further comprising:
expanding the C algorithm model into a C model;
compiling the C model;
creating a transmission interface between the C model and the verification environment;
the C model is integrated into the verification environment.
6. The method of claim 5, wherein compiling the C model comprises:
compiling and linking all source codes except the test routine in the C model into a target file, compiling the codes of the test routine, linking the target file and generating an executable file.
7. The method of claim 5, wherein creating a transport interface between the C-model and the verification environment comprises:
creating a DPI-C interface for transmitting the configuration information from the verification case module to the stimulus generator and transmitting the stimulus after format conversion from the first format conversion module to the verification case module to obtain a first DPI-C interface;
creating a DPI-C interface for transmitting configuration information from an input port of an algorithm module chip to a C algorithm model and transmitting the excitation after format conversion from the input port of the algorithm module chip to a second format conversion module to obtain a second DPI-C interface;
and creating a DPI-C interface for transmitting the format-converted reference result from the third format conversion module to the inspector to obtain a third DPI-C interface.
8. The method of claim 5, wherein said integrating the C model into the verification environment comprises:
compiling a link C algorithm model to generate a library file; and linking the library file when the verification case is run, and adding a target parameter in the command line parameter.
9. The method of any one of claims 1-8, further comprising:
the coverage rate collector performs coverage rate analysis and determines uncovered configuration according to the analysis result; and according to the uncovered configuration, modifying the constraint conditions in the verification case module, or creating a new verification case and sending the new verification case to the verification case module.
10. A chip algorithm module verification system based on a C algorithm model is characterized by comprising: the system comprises an algorithm model C, a chip algorithm module, a verification case module, a stimulus generator, a first format conversion module, a second format conversion module, a third format conversion module and a checker;
the verification case module is used for randomly generating configuration information on line according to constraint conditions and transmitting the configuration information to the excitation generator through the first DPI-C interface;
the stimulus generator is used for generating stimulus according to the configuration information and transmitting the stimulus to the first format conversion module, and the stimulus after format conversion is transmitted to the verification case module through the first DPI-C interface;
the verification case module is used for respectively transmitting the configuration information and the excitation after the format conversion to the chip algorithm module; the chip algorithm module is used for generating an actual result and transmitting the actual result to the checker;
capturing the configuration information and the excitation after the format conversion from an input port of a chip algorithm model, transmitting the configuration information to a C algorithm model through a second DPI-C interface, transmitting the excitation after the format conversion to a second format conversion module through the second DPI-C interface, and transmitting the excitation after the format conversion again to the C algorithm model; the C algorithm model is used for generating a reference result, transmitting the reference result to a third format conversion module, and transmitting the reference result after format conversion to the inspector through a third DPI-C interface;
the checker is used for judging whether the actual result is consistent with the reference result or not, and if so, the verification case is indicated to be operated successfully;
wherein the first DPI-C interface, the second DPI-C interface and the third DPI-C interface are transmission interfaces between a C model and a verification environment; the C model is obtained by taking the C algorithm model as a core extension and comprises the C algorithm model, an excitation generator, a first format conversion module, a second format conversion module and a third format conversion module; c, independently compiling the model in advance;
the first format conversion module is used for converting the stimulus into a data format suitable for hardware processing, the second format conversion module is used for converting the stimulus into a data format suitable for C algorithm model processing, and the third format conversion module is used for converting the result into a data format suitable for hardware processing.
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