CN112305961B - Novel signal detection and acquisition equipment - Google Patents
Novel signal detection and acquisition equipment Download PDFInfo
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Abstract
The invention provides a novel signal detection and acquisition device, which comprises: the system comprises a signal detection and acquisition unit and a management control unit which are in communication connection with each other for data transmission, wherein the management control unit is in communication connection with an upper computer so as to receive control command information sent by the upper computer and further send the control command information to the signal detection and acquisition unit, the signal detection and acquisition unit performs signal detection and data acquisition according to the control command information and sends the acquired data information to the management control unit so as to send the acquired data information to the upper computer. Adopt STM32 chip and FPGA chip architecture design to carry out data transmission through the data bus mode, all kinds of data in the FPGA chip pass through the FSMC interface and transmit to the STM32 chip, realize and carry out data transmission between the host computer by STM32 chip drive net gape again, thereby realize carrying out local save to the original data that surveys the collection, guaranteed the stability of signal detection post-acquisition transmission, realized the high-speed transmission of data.
Description
Technical Field
The invention belongs to the technical field of signal detection, and particularly relates to novel signal detection and acquisition equipment which can realize high-speed data transmission and obviously improve the data detection and acquisition efficiency.
Background
The very low frequency detection is to receive and monitor natural lightning radiation and very low frequency (ELF:300Hz-3kHz) and very low frequency (VLF:3-30kHz) electromagnetic radio wave signals transmitted by foundation stations distributed all over the world. The method is widely applied to the fields of solar activity monitoring, ionosphere detection, marine communication and the like.
The traditional signal detection equipment usually adopts an FPGA as a system control core device, and then is combined with a USB chip to realize the transmission of various data on the FPGA. However, the USB communication mode is unstable when transmitting data, which easily causes data loss, and the conventional signal detection device transmits the collected data to the upper computer through the USB chip, which often results in low data collection efficiency.
Disclosure of Invention
The invention aims to provide novel signal detection and acquisition equipment which can realize high-speed data transmission and obviously improve the data detection and acquisition efficiency aiming at the defects in the prior art.
In order to solve the technical problems, the invention adopts the following technical scheme:
the utility model provides a novel signal detection collection equipment, through with upper computer communication connection in order to realize the detection collection and the data transmission of signal, a serial communication port, include:
the management control unit is in communication connection with the upper computer; and a signal detection acquisition unit in communication connection with the management control unit,
wherein, the management control unit receives the control command information sent by the upper computer and then further sends the control command information to the signal detection acquisition unit,
the signal detection and acquisition unit performs signal detection and data acquisition according to the control command information and sends acquired data information to the management control unit, so that the acquired data information is sent to the upper computer.
Preferably, the signal detection acquisition unit has: a first communication module and a data acquisition module,
the management control unit has: a second communication module and a third communication module,
the data acquisition module is used for detecting and acquiring signals in the surrounding environment according to the acquisition requirements corresponding to the control command information,
the first communication module is in communication connection with the second communication module so as to realize data transmission between the signal detection and acquisition unit and the management control unit,
and the third communication module is in communication connection with the upper computer, so that data transmission between the management control unit and the upper computer is realized.
Preferably, the signal detection acquisition unit and the management control unit realize data transmission based on a register data bus communication mode,
the signal detection acquisition unit is designed by adopting an FPGA chip architecture, the management control unit is designed by adopting an STM32 chip architecture, the signal detection acquisition unit and the management control unit respectively comprise a write-in register and a read-out register,
the first communication module is communicated with a reading register of the signal detection acquisition unit and a writing register of the management control unit, and the second communication module is communicated with a reading register of the management control unit and a writing register of the signal detection acquisition unit.
Preferably, the first communication module is connected to the input end of the write-in register in the management control unit through a first tri-state gate control module and a data bus from the output end of the read register of the signal detection and acquisition unit, and is configured to transmit the acquired data information to the management control unit,
the second communication module is connected with the input end of the write-in register in the signal detection acquisition unit through a second tri-state gate control module and the data bus by the output end of the read register of the management control unit and is used for transmitting the control command information to the signal detection acquisition unit,
the data bus is connected between the output ends of the three-state gates of the first three-state gate control module and the second three-state gate control module.
Preferably, the novel signal detection and acquisition device further comprises:
and the control signal output unit is respectively connected with the signal detection acquisition unit and the management control unit and triggers the read operation or the write operation between the signal detection acquisition unit and the management control unit by outputting a control signal.
Preferably, the control signal output unit includes: a read enable signal line, a write enable signal line and a chip select signal line,
the read enable signal line and the chip select signal line are connected to the control signal input end of the first tri-state gate control module through a NOR gate circuit, the read enable signal line is directly connected to the control signal input end of the second tri-state gate control module,
the write enable signal line and the chip selection signal line are connected to the clock input end of a write register of the signal detection acquisition unit through an OR gate circuit.
Preferably, the chip select signal line is set to hold a low level signal,
the first tri-state gate control module is set to be in an open state when the read enable signal line outputs a low level signal so as to enable the communication line corresponding to the first communication module to be conducted, and the signal detection acquisition unit is enabled to transmit acquired data information to the management control unit,
the second tri-state gate control module is set to be in an open state when the read enabling signal line outputs a high-level signal, so that a communication line corresponding to the second communication module is conducted, and the management control unit transmits the control command information to the signal detection and acquisition unit.
Preferably, a write register in the management control unit is set to trigger the write register to latch data based on a read signal sent by the upper computer,
when the management control unit transmits the acquired data information to the upper computer, the read enabling signal line outputs a low level signal to enable the first tri-state gate control module to be in an open state and the second tri-state gate control module to be in a closed state, so that the communication line corresponding to the first communication module is conducted, and the acquired data information is conveniently transmitted to the upper computer through the management control unit.
Preferably, the signal detection acquisition unit further has: a data processing module for performing data classification processing on the signals acquired by the data acquisition module according to the data types required to be acquired in the control command information to obtain corresponding data information,
the management control unit sets different transmission parameters for the data information acquired by the signal detection acquisition unit based on the data types so as to realize efficient transmission of the data.
Preferably, the third communication module is in communication connection with the upper computer through a wired network or a wireless network, so that data information is transmitted from the first communication module, the second communication module and the third communication module to a packet transmission and then to a class transmission.
Compared with the prior art, the invention has the beneficial effects that: the novel signal detection and acquisition equipment is integrally realized based on an STM32 chip and an FPGA chip framework, data transmission is carried out in a register data bus mode, namely data reading or writing, various data in the FPGA chip are transmitted to an STM32 chip through an FSMC interface, and then the STM32 chip drives a network port to realize data transmission with an upper computer, so that the original data acquired by detection is locally stored, the stability of transmission after signal detection and acquisition is ensured by the integral structure, and the high-speed transmission of the data is realized in a network port communication mode, so that the integral efficiency of data detection and acquisition is obviously improved.
Drawings
Fig. 1 is a block diagram of a novel signal detection and acquisition device in an embodiment of the invention;
FIG. 2 is a schematic diagram of the physical connections at the interface between an FPGA chip and an STM32 chip in an embodiment of the invention;
FIG. 3 is a diagram illustrating a read/write structure of a RAM module according to an embodiment of the present invention;
FIG. 4 is a state flow diagram of a RAM module read mechanism in an embodiment of the present invention;
FIG. 5 is a state flow diagram of a RAM module write mechanism in an embodiment of the present invention;
fig. 6 is a diagram of an information transmission structure of an FPGA chip in the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the following embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The present invention is further illustrated by the following examples, which are not to be construed as limiting the invention.
As shown in fig. 1, the present embodiment discloses a novel signal detection and acquisition device 100, which is in communication connection with an upper computer 200 to implement signal detection and acquisition and data transmission. Specifically, after the novel signal detection and acquisition device 100 is started, the novel signal detection and acquisition device will automatically realize communication connection with the upper computer 200 in a network communication mode; an operator configures control command information required by signal acquisition according to data acquisition requirements through the upper computer 200 and forms a configuration information file, wherein the configuration information file at least comprises parameters such as acquisition frequency band, acquisition frequency, acquisition time, data types and data transmission requirements; the configured configuration information file is sent to the novel signal detection and acquisition device 100 in a network communication mode, the novel signal detection and acquisition device 100 performs signal detection and acquisition according to parameters contained in the received configuration information file, transmits acquired data information to the upper computer 200 according to data transmission requirements, and thus performs data acquisition and transmission operation circularly based on the configuration information file until the signal detection and acquisition is completed.
The novel signal detection and acquisition device 100 specifically includes: a signal detection and acquisition unit 10 and a management control unit 20.
The management control unit 20 is in communication connection with the upper computer 200 in a network communication manner, so as to receive control command information sent by the upper computer 200. Furthermore, the signal detection and acquisition unit 10 is in communication connection with the management control unit 20, so as to realize data transmission between the two units.
Specifically, the management control unit 20 further sends the control command information to the signal detection and acquisition unit 10 after receiving the control command sent by the upper computer 200, and the signal detection and acquisition unit 10 performs signal detection and data acquisition according to the control command information and sends the acquired data information to the management control unit 20. The management control unit 20 sends the acquired data information to the upper computer 200 for storage through a network communication mode.
Here, the management control unit 20 serves as a core control part of the novel signal detection and acquisition device 100, and is used for controlling the whole acquisition and data transmission process.
Based on this, the signal detection acquisition unit 10 has: a first communication module 11; the management control unit 20 includes: a second communication module 21 and a third communication module 22.
The first communication module 11 is in communication connection with the second communication module 21, so that data transmission between the signal detection and acquisition unit 10 and the management control unit 20 is realized; the third communication module 22 is in communication connection with the upper computer 200, so that data transmission between the management control unit 20 and the upper computer 200 is realized. Specifically, the third communication module 22 is communicatively connected to the upper computer 200 through a wired network or a wireless network.
Further, the signal detection acquisition unit 10 further has: a data acquisition module 12 and a data processing module 13.
The data acquisition module 12 is configured to detect and acquire signals in the surrounding environment where the novel signal detection and acquisition device 100 is located according to the corresponding acquisition requirements in the control command information. The collected signals can be extremely low frequency (ELF:300Hz-3kHz) and very low frequency (VLF:3-30kHz) radio electromagnetic wave signals, and can be frequency band signals which are set randomly.
The data processing module 13 is configured to perform data classification processing on the acquired signals, specifically, perform classification processing according to the type of data to be acquired in the control command information, so as to obtain data information of a corresponding type.
As shown in fig. 2, in the specific embodiment, the signal detection and acquisition unit 10 is designed by using an FPGA chip architecture, the management control unit 20 is designed by using an STM32 chip architecture, and data transmission between the signal detection and acquisition unit 10 and the management control unit 20 is realized based on a register data bus communication manner, that is, the signal detection and acquisition unit 10 and the management control unit 20 respectively include a write register and a read register, and data transmission is realized through a read or write operation. In order to realize the data transmission direction control between the signal detection and acquisition unit 10 and the management control unit 20, the signal detection and acquisition unit 10 and the management control unit 20 further include a tri-state gate control module respectively.
In summary, the signal detection and acquisition unit 10 includes: the device comprises a first communication module 11, a data acquisition module 12, a data processing module 13, a write register 14, a read register 15 and a first tri-state gate control module 16.
The management control unit 20 includes: a second communication module 21, a third communication module 22, a write register 23, a read register 24, and a second tri-state gate control module 25.
As shown in fig. 1 and 2, the specific structure between the signal detection and acquisition unit 10 and the management control unit 20 is as follows: the first communication module 11 is connected to the input end of the write register 23 in the management control unit 20 through the first tri-state gate control module 16 and the data bus DB from the output end of the read register 15 of the signal detection acquisition unit 10, that is, the first communication module 11 communicates the read register 15 of the signal detection acquisition unit 10 and the write register 23 of the management control unit 20, and is configured to transmit the acquired data information to the management control unit 20. In fig. 2, DB is a bidirectional data bus.
The second communication module 21 is connected to the output end of the read register 24 of the management control unit 20 through the second tri-state gate control module 25 and the data bus DB and the input end of the write register 14 in the signal detection and acquisition unit 10, that is, the second communication module 21 is connected to the read register 24 of the management control unit 20 and the write register 14 of the signal detection and acquisition unit 10 for transmitting control command information to the signal detection and acquisition unit 10.
The data bus DB is connected between the output terminals of the tri-state gates of the first tri-state gate control module 16 and the second tri-state gate control module 25, and data transmission, i.e. register reading or writing operation, is performed after the corresponding communication line is conducted under the control of the conducting states of the first tri-state gate control module 16 and the second tri-state gate control module 25.
As shown in fig. 2, in order to control the conducting states of the first tri-state gate control module 16 and the second tri-state gate control module 25, the novel signal detection and acquisition device 100 further includes a control signal output unit 30. The control signal output unit 30 is respectively connected to the signal detection and acquisition unit 10 and the management control unit 20, specifically to the control signal input ends of the first tri-state gate control module 16 and the second tri-state gate control module 25, and triggers a read operation or a write operation between the signal detection and acquisition unit 10 and the management control unit 20 by outputting a control signal.
As shown in fig. 2, the control signal output unit 30 includes: a read enable signal line NOE, a write enable signal line NWE, and a chip select signal line NEx.
The read enable signal line NOE and the chip select signal line NEx are connected to the control signal input terminal of the first tri-state gate control block 16 through an nor gate. Furthermore, the read enable signal line NOE is also directly connected to the control signal input of the second tri-state gate control block 25. The write enable signal line NWE and the chip select signal line NEx are connected to the clock input terminal of the write register 14 of the signal detection collection unit 10 through an or gate circuit.
During practical use, the chip select signal line NEx is set to hold a low level signal, and accordingly,
the first tri-state gate control module 16 is set to be in an open state when the read enable signal line NOE outputs a low level signal, so as to enable the communication line corresponding to the first communication module 11 to be conducted, and the signal detection and acquisition unit 10 is enabled to transmit acquired data information to the management control unit 20.
The second tri-state gate control module 25 is set to be in an open state when the read enable signal line NOE outputs a high level signal, so as to enable the communication line corresponding to the second communication module 21 to be conducted, and the management control unit 20 is enabled to transmit control command information to the signal detection and acquisition unit 10.
When the management control unit 20 transmits the acquired data information to the upper computer 200, the write-in register 23 in the management control unit 20 is set to trigger the write-in register 23 to latch data based on a read signal sent by the upper computer 200; and, the low level signal is output through the read enable signal line NOE to enable the first tri-state gate control module 16 to be in an open state and the second tri-state gate control module 25 to be in a closed state, so as to implement the conduction of the communication line corresponding to the first communication module 11, thereby maintaining the data flow direction between the signal detection acquisition unit 10 and the management control unit 20 consistent with the data flow direction between the management control unit 20 and the upper computer 200, facilitating the transmission of the acquired data information to the upper computer 200 through the management control unit 20, and avoiding the occurrence of the problem of data transmission errors caused by inconsistent data flow directions.
In the internal structure of the FPGA chip corresponding to the signal detection and acquisition unit 10 shown in fig. 2, nrd _ en ═ NEx | NOE, nrd _ en are used as the tri-state gate control signals at the output end of the data bus DB, and when the tri-state gate control signals are at low level, the first tri-state gate control module 16 is opened, and in the STM32 chip of the management control unit 20, the tri-state gate control signals at the output end of the DB are set to be at active state when the tri-state gate control signals are at high level, so that the second tri-state gate control module 25 is currently in closed state. Therefore, the data _ out of the read register 15 inside the FPGA chip is communicated with the data bus DB, so that data is transmitted to the write register 23 inside the STM32 chip, and finally, the FPGA chip writes data into the STM32 chip, that is, the signal detection acquisition unit 10 transmits acquired data information to the management control unit 20, and a transmission path of the signal detection acquisition unit is shown as a dotted path a in fig. 2.
In the internal structure of the STM32 chip corresponding to the management control unit 20 shown in fig. 2, a read signal sent from an external device (i.e., the host computer 200) triggers the register 23 to latch data, thereby completing the data reading from the external device. When the STM32 chip writes to the external device memory, the NOE is high so that the first tri-state gate control module 16 at the bus pin of the data bus DB inside the FPGA chip is in a closed state and the second tri-state gate control module 25 at the bus pin of the data bus DB inside the STM32 chip is in an open state. Therefore, the data _ out signal of the read register 24 inside the STM32 chip is communicated with the input terminal of the write register 14 (i.e., the data _ in register) inside the FPGA chip through the pin of the data bus DB, and the data _ in register trigger signal CLK is shown as a wr signal, where wr is NWE | NEx. The rising edge of the NWE signal triggers the data _ in register to latch data (such as control command information) on the bus of the data bus DB sent by the STM32 chip, and finally, the STM32 chip writes data into the FPGA chip, that is, the management control unit 20 transmits the control command information to the signal detection and acquisition unit 10, and the transmission path is shown as a dotted path B in fig. 2.
Here, communication between the FPGA chip and the STM32 chip requires an interface driver module to be implemented on the FPGA chip and a driver to be implemented on the STM32 chip.
As shown in fig. 3, in this embodiment, the FPGA chip is specifically connected to an fsmc (flexible Static Memory controller) interface of the STM32 chip by using a RAM module. The RAM module adopts a dual-port design, a group of interfaces are respectively arranged for reading and writing, and specifically, a 256-word dual-port RAM module is respectively adopted for reading and writing of an STM32 chip. The RAM block is similar in timing to the registers, with wrlock and rdclock as the write and read triggers, respectively. When an STM32 chip reads a RAM module, an interface signal corresponding to a region 41 in fig. 3 is connected to other modules inside an FPGA chip, and an interface signal corresponding to a region 42 in fig. 3 is connected to an FSMC interface related signal, where a ramrden signal is always kept at a high level, that is, a read enable is always in an on state; the rdaddress signal is connected with an address register, and the register stores address information latched from the FSMC pin; the rd clock is connected with the rd signal generated by the FSMC, and the rising edge of the rd clock triggers the RAM module to output data of a corresponding address at the q terminal. When an STM32 chip is written into a RAM module, a region 43 in FIG. 3 is connected with FSMC interface related signals corresponding to an interface, a region 44 in FIG. 3 is connected with a data module in an FPGA chip corresponding to an interface, wherein a ramwren signal is always kept at a high level, namely, a write enable is always in an on state, a wradress signal is also connected with an address register, wrlock is connected with a wr signal generated by FSMC, and the rising edge of the wrlock latches data at a data end to a corresponding address in the RAM module.
In the embodiment, for reading and writing of the RAM module, the FPGA chip and the STM32 chip have corresponding interface control programs. In the whole transmission mechanism, the STM32 chip serves as a Master (Master), the FPGA chip serves as a Slave (Slave), and reading and writing operations are initiated by the STM32 chip.
As shown in fig. 4, the left side is the state flow corresponding to the FPGA chip of the read mechanism, and the right side is the state flow corresponding to the STM32 chip of the read mechanism. When reading, the FPGA chip is used as a slave device, and waits for a start signal sent by the STM32 chip, then data is written into the RAM module, and the STM32 chip is informed after the data is written. The STM32 chip starts reading the data in the RAM blocks after receiving the signal and informs the FPGA chip after completion. And finally, the FPGA chip sends a handshake signal to the STM32 chip to complete data reading of a data packet, namely, the management control unit 20 finishes transmitting the acquired data information to the upper computer 200.
As shown in fig. 5, the left side is the state flow corresponding to the FPGA chip of the write mechanism, and the right side is the state flow corresponding to the STM32 chip of the write mechanism. When writing, the STM32 chip is used as a master device, data can be written into the RAM module firstly, and then signals are sent to the FPGA chip. And after the FPGA chip waits for the signal, reading corresponding data from the RAM module, analyzing the data, and informing the STM32 chip after the signal is completed. Finally, after waiting for the signals of the FPGA chip, the STM32 chip sends handshake signals to the FPGA chip to complete data writing of one packet, that is, to complete transmission of control command information from the management control unit 20 to the signal detection acquisition unit 10.
In this embodiment, the information detected and collected by the signal detection and collection unit 10 needs to be sent to the management control unit 20, and also needs to receive the information sent by the management control unit 20, and these information interacting with the management control unit 20 can be divided into sending information and receiving information. From the perspective of the signal detection and acquisition unit 10, the transmitted information can be classified into error and warning information, status information and data information; the received information may be classified into control information and data information.
In the transmitted message, the generation of the error and warning messages is random and therefore of the interrupt (Interpret) type; the status information is updated in the signal detection and acquisition unit 10 at a fixed rate in real time, but the management control unit 20 uses the information as needed and obtains the information immediately when needed, so that the status information belongs to a polling (Polled) type; the data information is divided into two types, one type is original data, atmospheric noise data and station signal data, the rate of the data generation of the type is fixed, the mode of the data generation is the same as that of the state information, but different from the state information, the data of each byte of the data of the type needs to be sent, and therefore the data belong to the fixed rate type; the other is lightning data, randomly generated and therefore of the interrupt type. Specifically, the management control unit 20 may transmit data by a method of configuring an interrupt with respect to the interrupt type data at the time of designing a program; for polling type data, corresponding instructions can be sent to acquire the data when needed; for data of fixed rate type, data needs to be acquired constantly and regularly to ensure that all data is received. For different types of data, received in different ways at the management control unit 20, the CPU resources can be used more efficiently.
In the received information, the control information includes a trigger start time, a start signal, and the like; the data information includes configuration parameters for data processing. Among these pieces of received information, the management control unit 20 may directly transmit the information when necessary, and the signal detection and acquisition unit 10 is constantly in a state ready for reception.
Based on the classified transmission setting of all data information in the signal acquisition process, the data acquisition system corresponds to different transmission parameters, the overall efficiency of data detection and acquisition and the data transmission efficiency are obviously improved, and the high-efficiency transmission of data is realized.
As shown in fig. 6, the original data, the atmospheric noise data, the lightning signal data, and the station signal data are respectively allocated to one FIFO memory, the data of the FIFO memory is input to the transmission information control module again, and the state information and the error and warning information are directly accessed to the transmission information control module because the data amount is small. The data type selection signal is a signal output by the STM32 chip to the FPGA chip, and is directly connected to the sending information control module for selecting what type of data to be transmitted. The sending information control module is connected with the FSMC read data transmission module, transmits data to the read RAM module through the FSMC read data transmission module, and finally sends the data to the STM32 chip through the interface. On the other hand, the data written into the RAM module is written into the data transmission module through the FSMC interface and then is output to the received information control module, and the received information control module stores the data into corresponding modules such as control information or data information according to the selection of the data type at the moment. Each independent module analyzes specific information according to an agreed data packaging format, for example, the control information module analyzes year, month, day, hour, minute and second of the starting signal and the triggering time, and the data information module analyzes configuration parameters of the corresponding data processing module, for example, the resolution of atmospheric noise, the number of points of FFT operation, the central frequency of station signal demodulation, the time resolution of station signal phase and amplitude, and the like.
In practical application, the specific timing of the FSMC interface needs to be configured through a control program of an STM32 chip, and the configuration of each parameter of different modes is not completely the same, and needs to be configured according to the requirement in the multiplexing mode. In the FSMC _ BCRx register, EXTMOD is an extended address access field and needs to be set to 0x 0; MWID is memory data line bus width, configured as 0x1, i.e., 16 bits; MTYP is configured as a memory type and is configured as 0x2, namely a NOR Flash type; MUXEN is address/data multiplexing enable bit, configured as 0x1, i.e. on; MBKEN is a storage area enable bit, configured as 0x1, that opens the corresponding storage area. In the FSMC _ BTRx register, ACCMOD is configured to 0x 0; the DATAST field controls the overall duration of the second access phase, including setup time and hold time, with read accesses being DATAST HCLK cycles and write accesses being DATAST +1 HCLK cycles; the ADDHLD field controls the duration of the access intermediate phase, i.e., the hold time, as ADDHLD HCLK cycles; the ADDSET field controls the duration of the first access phase, i.e., setup time, as ADDSET HCLK cycles with an ADDSET minimum of 1. Combining read and write timing, one can find the theoretical read speed (MB/sec) as fHCLK/(ADDSET + ADDHLD + DATAST) × 2; the theoretical write speed (MB/sec) is fHCLK/(ADDSET + ADDHLD + DATAST +1) × 2.
For example, in the configuration parameters of the STM32 chip, the frequency of the configuration HCLK is 168 MHz. And the related pins of the FSMC interface are functionally multiplexed with the common IO port, and the related parameter registers of the FSMC interface are configured. Specifically, the configured timing parameter is ADDSET ═ 3; ADDHLD ═ 2; the theoretical read speed was 42 MB/sec and the theoretical write speed was 37.3 MB/sec, calculated as 3 DATAST. The reading and writing parameters of the STM32 chip are carried out in a circulating mode, a packet, namely 256-word data, is circularly put into a pre-distributed variable, and the data reading and writing of a data packet are completed by matching with a corresponding data packet reading and writing handshake mechanism. The whole measured data reading speed is 16.6 MB/s, the writing speed is 27.2 MB/s, and the reading speed and the writing speed both meet the data high-speed transmission target.
To sum up, the novel signal detection collection equipment of this embodiment is whole to be realized based on STM32 chip and FPGA chip architecture, and carry out data transmission through register data bus mode, reading or writing in of data promptly, all kinds of data in the FPGA chip pass through the FSMC interface and transmit to the STM32 chip, realize and carry out data transmission between the host computer by STM32 chip drive net gape again, thereby realize carrying out local storage to the original data who surveys the collection, overall structure has guaranteed the stability of signal detection post-collection transmission, can not cause data loss.
In addition, based on the FPGA and STM32 architecture, the communication mode of the data bus between the first communication module and the second communication module, and the wired network or wireless network communication mode between the third communication module and the upper computer, the data information is transmitted from word transmission to packet transmission and then to class transmission among the first communication module, the second communication module and the third communication module, so that the data transmission efficiency is improved.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (4)
1. The utility model provides a novel signal detection collection equipment, through with upper computer communication connection in order to realize the detection collection and the data transmission of signal, a serial communication port, include:
the management control unit is in communication connection with the upper computer; the signal detection acquisition unit is in communication connection with the management control unit; and a control signal output unit respectively connected with the signal detection acquisition unit and the management control unit,
wherein, the management control unit receives the control command information sent by the upper computer and then further sends the control command information to the signal detection acquisition unit,
the signal detection and acquisition unit performs signal detection and data acquisition according to the control command information and transmits the acquired data information to the management control unit, so that the acquired data information is transmitted to the upper computer,
the signal detection acquisition unit has: a first communication module and a data acquisition module,
the management control unit has: a second communication module and a third communication module,
the data acquisition module is used for detecting and acquiring signals in the surrounding environment according to the acquisition requirements corresponding to the control command information,
the first communication module is in communication connection with the second communication module so as to realize data transmission between the signal detection and acquisition unit and the management control unit,
the third communication module is in communication connection with the upper computer so as to realize data transmission between the management control unit and the upper computer,
the signal detection acquisition unit and the management control unit realize data transmission based on a register data bus communication mode,
the signal detection acquisition unit is designed by adopting an FPGA chip architecture, the management control unit is designed by adopting an STM32 chip architecture, the signal detection acquisition unit and the management control unit respectively comprise a write-in register and a read-out register,
the first communication module is communicated with a read register of the signal detection acquisition unit and a write register of the management control unit, the second communication module is communicated with a read register of the management control unit and a write register of the signal detection acquisition unit,
the first communication module is connected with the input end of a write-in register in the management control unit through a first tri-state gate control module and a data bus by the output end of a read register of the signal detection acquisition unit and is used for transmitting acquired data information to the management control unit,
the second communication module is connected with the input end of the write-in register in the signal detection acquisition unit through a second tri-state gate control module and the data bus by the output end of the read register of the management control unit and is used for transmitting the control command information to the signal detection acquisition unit,
the data bus is connected between the output ends of the three-state gates of the first three-state gate control module and the second three-state gate control module,
the control signal output unit triggers a read operation or a write operation between the signal detection acquisition unit and the management control unit by outputting a control signal, and the control signal output unit comprises: a read enable signal line, a write enable signal line and a chip select signal line,
the read enable signal line and the chip select signal line are connected to the control signal input end of the first tri-state gate control module through a NOR gate circuit, the read enable signal line is directly connected to the control signal input end of the second tri-state gate control module,
the write enable signal line and the chip select signal line are connected to the write register clock input end of the signal detection acquisition unit through an OR gate circuit,
the chip select signal line is set to hold a low level signal,
the first tri-state gate control module is set to be in an open state when the read enable signal line outputs a low level signal so as to enable the communication line corresponding to the first communication module to be conducted, and the signal detection acquisition unit is enabled to transmit acquired data information to the management control unit,
the second tri-state gate control module is set to be in an open state when the read enabling signal line outputs a high-level signal, so that a communication line corresponding to the second communication module is conducted, and the management control unit transmits the control command information to the signal detection and acquisition unit.
2. The novel signal detection and acquisition device according to claim 1, characterized in that:
a write register in the management control unit is set to trigger the write register to latch data based on a read signal sent by the upper computer,
when the management control unit transmits the acquired data information to the upper computer, the read enabling signal line outputs a low level signal to enable the first tri-state gate control module to be in an open state and the second tri-state gate control module to be in a closed state, so that the communication line corresponding to the first communication module is conducted, and the acquired data information is conveniently transmitted to the upper computer through the management control unit.
3. The novel signal detection and acquisition device according to claim 1 or 2, characterized in that:
the signal detection acquisition unit further has: a data processing module for performing data classification processing on the signals acquired by the data acquisition module according to the data types required to be acquired in the control command information to obtain corresponding data information,
the management control unit sets different transmission parameters for the data information acquired by the signal detection acquisition unit based on the data types so as to realize efficient transmission of the data.
4. The novel signal detection and acquisition device of claim 3, wherein:
the third communication module is in communication connection with the upper computer through a wired network or a wireless network, and word transmission, packet transmission and class transmission of data information among the first communication module, the second communication module and the third communication module are achieved.
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