CN112258515B - Graph segmentation method based on fixed vertex - Google Patents
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Abstract
The invention provides a graph segmentation method based on fixed vertices, which comprises the following steps: s1, modeling a circuit design netlist: converting the circuit design netlist into a weighted hypergraph, and pre-allocating fixed vertexes to designated logic groups; s2, clustering to construct a fixed vertex sub-graph and a movable sub-graph; s3, initial segmentation stage: distributing the fixed vertex subgraphs into predefined logical groups, and distributing the movable subgraphs into different logical groups randomly and uniformly; s4, optimizing and adjusting: and traversing the movable subgraph, calculating the profit of the movable vertex, moving the vertex to the corresponding group according to the profit size, and optimizing the size of the cut size cutting connecting line. The invention can satisfy the fixed distribution of the specific function nodes to the designated groups, and simultaneously achieves the purposes of faster segmentation speed, larger processing data scale, smaller coupling degree between the segmented data blocks and higher processing efficiency.
Description
Technical Field
The present disclosure relates to the field of computer software technologies, and in particular, to a graph segmentation method based on fixed vertices.
Background
Very Large Scale Integration (VLSI) complexity presents a significant challenge to eda (electronic Design automation) Design tools. The circuit division (CUT) technology divides the VLSI design problem into a plurality of smaller parts to be processed respectively, is one of the key technologies in the circuit design stage, and is an effective way to solve the VLSI complexity design problem. The circuit segmentation algorithm is a basic algorithm in an EDA tool and is also an important method for realizing hierarchical design of VLSI. The circuit partitioning algorithm is an NP (Non-Polynomial time-solvable) complete problem, which usually requires an approximate solution using a heuristic algorithm.
The current general circuit division algorithm is a multi-stage division algorithm, and has better operation speed when processing a large-scale integrated circuit. The multi-stage segmentation algorithm mainly comprises the following four stages as shown in fig. 1: (1) modeling a circuit design into a hypergraph (a graph with edges connecting two or more vertexes) netlist, (2) clustering the original netlists, (3) initially dividing, and (4) optimizing and adjusting.
The initial partitioning and optimization tuning phase typically employs an FM algorithm (Fiduccia and Mattheys) that optimizes the grouping results primarily by moving vertex reduction cut links (cutSize). The final segmentation result is generally based on the CutSize minimum under the constraint of the size balance of the vertices among the groups.
In some complex circuit design verification prototype systems and simulation platforms, since different hardware has different functions, specific circuit design modules/instances need to be assigned to specific groups, ultimately mapping to hardware resources of a specific function. The currently adopted FM algorithm cannot meet the characteristic segmentation constraint scene, and other segmentation algorithms have higher segmentation efficiency and larger grouping result cutsize under the condition of meeting the fixed node segmentation constraint condition.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a graph partitioning method based on fixed vertices, which can satisfy the requirements of fixedly allocating specific functional nodes to designated groups, so that the specific nodes are fixedly allocated to specific grouping scenes, and achieve the purposes of faster partitioning speed, larger processing data scale, smaller coupling degree between partitioned data blocks, and higher processing efficiency.
In order to achieve the above purpose, the invention provides the following technical scheme:
a graph segmentation method based on fixed vertices comprises the following steps:
s1, modeling a circuit design netlist: converting the circuit design netlist into a weighted hypergraph, and predefining and distributing fixed vertexes to specified logic groups;
s2, a hypergraph coarsening and clustering stage, wherein a fixed vertex sub-graph and a movable sub-graph are clustered;
s3, initial segmentation stage: distributing the fixed vertex subgraph to a predefined logic group, and then distributing the movable subgraph to different logic groups randomly and uniformly;
s4, optimizing and adjusting: and traversing the movable subgraph, calculating the profit of the movable vertex, moving the vertex to the corresponding group according to the profit size, and optimizing the size of the cut size cutting connecting line.
Further, in S1, different logic grouping types are defined according to the hardware resource function division, and the hypergraph vertices mapped by the logic module Cell/instance of a specific function in the circuit design are fixedly allocated to the divided hardware resource logic groups in advance.
And further defining different logic grouping types according to the resource function division of the programmable logic device, wherein the resource functions of the programmable logic device comprise general hardware, memory hardware resources and DSP (digital signal processor) resources.
Further, in S2, traversing all the fixed vertices, gathering the vertices tightly connected to the fixed vertices together with the fixed vertices as seeds, and constructing a fixed vertex subgraph;
and traversing the rest of the vertexes which are not clustered, randomly selecting a seed vertex, and clustering the vertexes which are tightly connected with the seed vertex to construct a movable subgraph.
Further, the vertex tightly connected with the fixed vertex comprises: vertices with edges connected to fixed vertices and with edges having a large weight.
Further, in S4, the movable subgraph is traversed and the movable vertex revenue is calculated using FM algorithm.
Further, the method also comprises the step of S5: and restoring the clustering structure subgraph into the original hypergraph.
The graph segmentation method based on the fixed vertex has the advantages that: aiming at the problem that the current FM algorithm cannot meet the condition of a characteristic segmentation constraint scene, the invention provides a graph segmentation method based on a fixed vertex, which can meet the condition of fixedly distributing specific function nodes to a specific grouping scene, so that the segmentation speed is higher, the processing data scale is larger, the coupling degree between segmented data blocks is smaller, and the processing efficiency is effectively improved.
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In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of an algorithm process according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an algorithm for optimizing the cutting process at the adjustment stage according to an embodiment of the present invention;
FIG. 3 is a diagram of a clustering construct graph according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a logic circuit according to an embodiment of the present invention;
FIG. 5 is a hypergraph of a mapping transformation of a logic circuit in an embodiment of the invention;
fig. 6 is a diagram of a programmable logic device with different functions according to an embodiment of the present invention.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
As shown in fig. 1 to 6, an embodiment of the present disclosure provides a graph segmentation method based on fixed vertices, including the following steps:
s1, modeling a circuit design netlist, and converting the circuit design netlist into a weighted hypergraph (edges have different weights); specifically, the logic circuit design and mapping of fig. 4. The logic circuit Cell module/instance is mapped as a hypergraph vertex and the connection Net is mapped as a hypergraph super edge.
Pre-assigning a designated vertex to a designated group:
(1) defining different logic grouping types according to different division of hardware resource functions; as shown in fig. 6 with 4 sets of FPGA hardware, FPGAs 1 and 4 are generic, FPGA2 is with RAM memory resources, and FPGA3 is with DSP digital signal processor resources. The hardware resources are divided into 4 groups of Grp1, Grp2_ RAM, Grp3_ Dsp and Grp4 according to the functions of the hardware resources, wherein Grp1 and Grp4 are universal hardware assignable arbitrary functional logic modules, Grp2_ RAM is a memory hardware resource and assignable memory related modules, and Grp3_ Dsp digital signal processor hardware resources and assignable Dsp related modules.
(2) The hypergraph vertices mapped by the logic module Cell/instance instances of a specific function in the circuit design are fixedly allocated to the logic groups in advance. For example, the logic circuit corresponding to the vertex g5 of the hypergraph of fig. 5 is a memory and is fixedly distributed to the Grp2_ RAM group, and the logic circuit module corresponding to g8 is a multiplier and is fixedly distributed to the Grp3_ Dsp group, so that higher computing performance can be achieved. The hypergraph vertex g2 is mapped by the logic circuit g2, and a common logic module can be fixedly allocated to Grp1 or Grp4, or can be allocated randomly by the subsequent initial allocation.
S2, clustering, namely clustering to construct two types of sub-graphs;
and in the first step, traversing all the fixed vertexes, taking the fixed vertexes as seeds, and gathering vertexes which are tightly connected with the fixed vertexes (connected with edges and have large weights of the edges) together to construct a fixed node subgraph FixGraphSub.
As shown in FIG. 5, g2 is fixedly assigned to a group of Grp1, g2 is selected as a cluster of seed vertices, i2 and g4 which are tightly connected with g2 and commonly function are clustered as a FixGraphSub type subgraph FS _ g2. g5 which is already fixedly assigned to a group of Grp2_ RAM is selected as a seed vertex, g9 and g7 which are tightly connected with g5 and similar in function are aggregated to generate a FixGraphSub type subgraph FS _ g5. with the fixed vertex g8 as a seed node, the aggregated g10 generates a FixGraphSub type subgraph FS _ g8.
Step two, traversing the residual vertexes which are not clustered, randomly selecting a seed vertex, and clustering vertexes which are tightly connected with the seed vertex to construct a movable subgraph MoveGrapSub;
randomly selecting g3 as a seed vertex, aggregating i3 vertex structures and moving MoveGrapSub type subgraphs MG _ g3., aggregating i4 vertex with g6 as a seed vertex, and aggregating i5 vertex structures MG _ g6, and the like. Referring to fig. 3, a is a seed vertex, and vertices b and c connected to a are aggregated together to form a subgraph abc.
S3, an initial segmentation stage;
firstly, distributing a fixed vertex subgraph FixGraphSub to a predefined grouping logic group;
FS _ g2 is assigned to Grp2 groups, FS _ g5 to Grp2_ RAM, FS _ g8 to Grp3_ Dsp;
secondly, randomly and uniformly distributing the movable subgraph MoveGrapSub into different groups;
MG _ g3 points to Grp1, MG _ g6 points to Grp4.
S4, optimizing and adjusting;
traversing the movable subgraph MoveGrapSub, calculating movable vertex profit by using an FM (frequency modulation-matching algorithms) algorithm, reducing cutting lines (CutSize) by moving the vertex by the FM algorithm, moving the vertex to a corresponding group according to the profit size, and optimizing the CutSize cutting line size. The specific flow refers to a schematic diagram of an algorithm of a cutting process in an optimization and adjustment stage of fig. 2, which specifically includes the following steps:
(1) calculating the profit according to an FM algorithm, and selecting the peak mobile packet with the maximum profit;
(2) comparing whether the CutSize calculated by current adjustment is reduced or not, and determining whether optimization is continued or not;
(3) if the FM gain is reduced, continuing optimization and jumping to the first step of the FM gain;
(4) if there is no decrease or less than the set threshold, the optimization ends.
And S5, restoring the clustering structure subgraph into the original hypergraph.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (3)
1. A graph segmentation method based on fixed vertices is characterized by comprising the following steps:
s1, modeling a circuit design netlist: converting the circuit design netlist into a weighted hypergraph, and predefining and distributing fixed vertexes to specified logic groups;
s2, a hypergraph coarsening and clustering stage, wherein a fixed vertex sub-graph and a movable sub-graph are clustered;
s3, initial segmentation stage: distributing the fixed vertex subgraph to a predefined logic group, and then distributing the movable subgraph to different logic groups randomly and uniformly;
s4, optimizing and adjusting: traversing the movable subgraph, calculating the profit of the movable vertex, moving the vertex into a corresponding group according to the profit size, and optimizing the size of the cut size cutting connecting line;
in S1, defining different logic grouping types according to hardware resource function division, and fixedly allocating the hypergraph vertex mapped by the logic module with specific function in the circuit design to the divided hardware resource logic grouping in advance;
in S2, traversing all fixed vertexes, taking the fixed vertexes as seeds, and gathering vertexes which are tightly connected with the fixed vertexes together to construct a fixed vertex subgraph;
traversing the rest of the vertexes which are not clustered, randomly selecting a seed vertex, and clustering vertexes which are tightly connected with the seed vertex to construct a movable subgraph; wherein, the vertex tightly connected with the fixed vertex comprises: vertices connected with edges to the fixed vertices and having edges with large weights;
in S4, the movable subgraph is traversed and the movable vertex revenue is calculated using FM algorithm.
2. The fixed vertex based graph partitioning method according to claim 1, wherein different logic grouping types are defined according to resource function partitioning of programmable logic devices, wherein the resource functions of the programmable logic devices comprise general purpose hardware, memory hardware resources, DSP digital signal processor resources.
3. The fixed vertex-based graph partitioning method according to claim 1, further comprising S5: and restoring the clustering structure subgraph into the original hypergraph.
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Address after: Room 27, 6th floor, No. 29 and 30, Lane 1775, Qiushan Road, Lingang New District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 201306 Patentee after: Shanghai Sierxin Technology Co.,Ltd. Address before: Room 27, 6th floor, No. 29 and 30, Lane 1775, Qiushan Road, Lingang New District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 201306 Patentee before: Shanghai Guowei silcore Technology Co.,Ltd. |