CN112235163A - Method, device, equipment and medium for preventing data from being blocked for FPGA (field programmable Gate array) architecture - Google Patents

Method, device, equipment and medium for preventing data from being blocked for FPGA (field programmable Gate array) architecture Download PDF

Info

Publication number
CN112235163A
CN112235163A CN202011132959.2A CN202011132959A CN112235163A CN 112235163 A CN112235163 A CN 112235163A CN 202011132959 A CN202011132959 A CN 202011132959A CN 112235163 A CN112235163 A CN 112235163A
Authority
CN
China
Prior art keywords
data
channel
data channel
judged
judging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202011132959.2A
Other languages
Chinese (zh)
Other versions
CN112235163B (en
Inventor
张文帅
刘明星
余波
魏荣超
水璇璇
徐孝芬
谌志强
陈起
赵洋
汪亨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nuclear Power Institute of China
Original Assignee
Nuclear Power Institute of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nuclear Power Institute of China filed Critical Nuclear Power Institute of China
Priority to CN202011132959.2A priority Critical patent/CN112235163B/en
Publication of CN112235163A publication Critical patent/CN112235163A/en
Application granted granted Critical
Publication of CN112235163B publication Critical patent/CN112235163B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
    • H04L43/0811—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking connectivity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/12—Avoiding congestion; Recovering from congestion

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Health & Medical Sciences (AREA)
  • Cardiology (AREA)
  • General Health & Medical Sciences (AREA)
  • Environmental & Geological Engineering (AREA)
  • Communication Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The method detects the data channel to be judged by a channel dynamic opening and closing method, takes the opened channel as an effective data channel, excludes the closed channel, and only polls the opened channel without polling each data channel, thereby effectively reducing the data volume of polling processing and relieving data blockage. And then selecting data of one effective data channel for polling, judging the data by an overtime prejudgment method, when the data is abnormal, directly polling the data of the next effective data channel, and repeatedly executing the step of judging the data by the overtime prejudgment method until all the effective data channels finish polling, eliminating the abnormal data, not polling the abnormal data, reducing the data amount of polling processing, relieving data blockage and ensuring the safety and stability of the data of the safety DCS platform of the nuclear power plant.

Description

Method, device, equipment and medium for preventing data from being blocked for FPGA (field programmable Gate array) architecture
Technical Field
The invention relates to the technical field of security level digital control, in particular to a method, a device, equipment and a medium for preventing data from being blocked for an FPGA (field programmable gate array) architecture.
Background
The safety level DCS platform of the nuclear power plant is a comprehensive platform comprising a plurality of functional stations, information interaction among the functional stations is completed through a communication module, one communication module can gather data of different functional stations, and transmission media among the data adopt optical fiber interfaces. At present, under the framework of a communication module full FPGA, a polling mode is generally adopted to process multiple paths of aggregated data, the polling mode does not consider the influence that multiple paths of aggregation come simultaneously and different channel data are different, and the polling mode causes data blocking, thereby causing data packet loss. Meanwhile, due to the physical characteristics of the hardware optical interface and the change of the external environment (for example, the influence of illumination on the exposed optical interface) may also cause the generation of error data information, thereby blocking the channel data from being transmitted and received. Therefore, the polling mechanism cannot solve the blocking phenomenon caused by data aggregation of the multifunctional station, and the requirement of the safety DCS platform of the nuclear power plant on the safety and reliability of communication is difficult to meet.
Disclosure of Invention
The invention provides a method, a device, equipment and a medium for preventing data blocking of an FPGA (field programmable gate array) framework, which are used for processing multi-channel data generated by a multifunctional station, preventing data blocking and ensuring the safety and stability of the data of a safety DCS (distributed control system) platform of a nuclear power plant.
The invention is realized by the following technical scheme:
a method for preventing data blocking of an FPGA architecture comprises the following steps:
detecting a data channel to be judged by a channel dynamic opening and closing method to obtain an effective data channel;
selecting data of one effective data channel for polling, and judging the data by an overtime prejudgment method;
and when the data is abnormal, directly polling the data of the next effective data channel, and repeatedly executing the step of judging the data by the overtime prejudgment method until all the effective data channels finish polling.
Further, the detecting the data channel to be judged by the channel dynamic opening and closing method to obtain the effective data channel includes:
analyzing the initialization configuration command, and taking the corresponding data channel as a data channel to be judged when the initialization configuration command is opened;
detecting an external link of a data channel to be judged in real time, closing the corresponding data channel to be judged when the external link is abnormal, responding a configuration command of the data channel to be judged in real time, and detecting the external link of the data channel to be judged in real time;
and when the configuration command of the data channel to be judged is open or the external link of the data channel to be judged is recovered to be normal, taking the data channel to be judged as an effective data channel.
Further, the method for preventing data blocking based on the FPGA architecture further comprises:
when the external link is abnormal, reporting the abnormal condition of the external link;
and calling a link exception recovery script to recover the external link exception based on the external link exception.
Further, the determining the data by the timeout anticipation method includes:
dividing the data according to the frame head and the frame tail to obtain a data packet to be detected;
acquiring a preset data packet sending period, and taking the preset data packet sending period as an interval period;
acquiring the sending length of a preset data packet, and calculating the receiving time for completing receiving of a data packet to be detected based on the sending length of the preset data packet and a module clock;
calculating a reserved time length based on the interval period and the receiving time length;
and judging the data based on the interval period, the sending length, the receiving time length and the reserved time length.
Further, the determining the data based on the interval period, the transmission length, the receiving duration and the reserved duration includes:
when the receiving duration exceeds the interval period, judging that the data is abnormal;
when the receiving duration exceeds the reserved duration, judging that the data is abnormal;
and when the sending length exceeds the preset maximum length, judging that the data is abnormal.
Further, the determining the data by the timeout pre-determination method further includes:
and detecting whether the data has a frame head, and if the data does not have the frame head, judging that the data has abnormality.
An FPGA-architecture data blocking prevention apparatus, comprising:
the channel dynamic opening and closing processing module is used for detecting the data channel to be judged by a channel dynamic opening and closing method to obtain an effective data channel;
the overtime prejudgment processing module is used for selecting data of one effective data channel for polling and judging the data by an overtime prejudgment method;
and the polling module is used for directly polling the data of the next effective data channel when the data is abnormal, and repeatedly executing the step of judging the data by the overtime prejudgment method until all the effective data channels finish polling.
Further, the dynamic channel opening and closing processing module comprises:
the device comprises a to-be-judged data channel determining unit, a judging unit and a judging unit, wherein the to-be-judged data channel determining unit is used for analyzing an initialization configuration command, and when the initialization configuration command is opened, the corresponding data channel is used as a to-be-judged data channel;
the external link processing unit is used for detecting an external link of a data channel to be judged in real time, closing the corresponding data channel to be judged when the external link is abnormal, responding to a configuration command of the data channel to be judged in real time and detecting the external link of the data channel to be judged in real time;
and the effective data channel determining unit is used for taking the data channel to be judged as an effective data channel when the configuration command of the data channel to be judged is open or the external link of the data channel to be judged is recovered to be normal.
A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the above-mentioned method for preventing data blocking of an FPGA architecture when executing the computer program.
A computer-readable storage medium, in which a computer program is stored, which, when executed by a processor, implements a method of preventing data blocking of an FPGA architecture as described above.
According to the method, the device, the equipment and the medium for preventing the data from being blocked for the FPGA architecture, the data channel to be judged is detected through a channel dynamic opening and closing method, the opened channel is used as an effective data channel, and the closed channel is excluded, so that each data channel does not need to be polled, only the opened channel is polled, the data volume of polling processing is effectively reduced, and the data blocking is relieved. And then selecting data of one effective data channel for polling, judging the data by an overtime prejudgment method, when the data is abnormal, directly polling the data of the next effective data channel, and repeatedly executing the step of judging the data by the overtime prejudgment method until all the effective data channels finish polling, eliminating the abnormal data, not polling the abnormal data, reducing the data amount of polling processing, relieving data blockage and ensuring the safety and stability of the data of the safety DCS platform of the nuclear power plant.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 is a flowchart of a method for preventing data blocking in an FPGA architecture according to the present invention.
Fig. 2 is a specific flowchart of step S10 in fig. 1.
FIG. 3 is another flowchart of a method for preventing data blocking according to an FPGA architecture of the present invention.
Fig. 4 is a specific flowchart of step S20 in fig. 1.
FIG. 5 is a diagram illustrating a timeout pre-judging method according to an embodiment of the present invention
FIG. 6 is a schematic block diagram of a data blocking prevention apparatus of an FPGA architecture according to the present invention.
FIG. 7 is a schematic diagram of the computer apparatus of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1
As shown in fig. 1, the present invention provides a method for preventing data blocking for an FPGA architecture, which specifically includes the following steps:
s10: and detecting the data channel to be judged by a channel dynamic opening and closing method to obtain an effective data channel.
The data channel to be judged refers to a channel which is configured to be opened and needs to be polled. The effective data channel refers to a channel which is used for detecting a data channel to be judged by a channel dynamic opening and closing method and is configured to be opened and an external link is normal.
The dynamic channel opening and closing method in this embodiment is a method for determining whether a channel is opened or not and whether an external link is normal or not in real time. The specific steps are step S11-step S13.
S20: and selecting data of one effective data channel for polling, and judging the data by an overtime prejudgment method.
The timeout pre-judging method is used for judging whether data in the valid channel is abnormal, and the specific steps are step S21-step S25.
S30: and when the data is abnormal, directly polling the data of the next effective data channel, and repeatedly executing the step of judging the data by the overtime prejudgment method until all the effective data channels finish polling.
The case where the data has an exception in the present embodiment includes, but is not limited to, the frame length of the data exceeding the protocol-defined length, the absence of a frame head and/or a frame end of the data, and a data reception timeout.
Further, as shown in fig. 2, in step S10, detecting the data channel to be determined by a channel dynamic opening and closing method to obtain an effective data channel, the method specifically includes the following steps:
s11: and analyzing the initialization configuration command, and taking the corresponding data channel as a data channel to be judged when the initialization configuration command is opened.
Wherein, the initialization configuration command refers to an instruction for opening or closing certain channels input by a user at the client.
S12: and detecting an external link of the data channel to be judged in real time, closing the corresponding data channel to be judged when the external link is abnormal, responding to a configuration command of the data channel to be judged in real time, and detecting the external link of the data channel to be judged in real time.
The link abnormality in the present embodiment includes, but is not limited to, an abnormality of frame data. Anomalies in frame data include, but are not limited to, a frame length exceeding a protocol-defined length, a lack of a frame header and/or a frame trailer, and a reception timeout, among others.
S13: and when the configuration command of the data channel to be judged is open or the external link of the data channel to be judged is recovered to be normal, taking the data channel to be judged as an effective data channel.
Further, as shown in fig. 3, the method for preventing data blocking based on the FPGA architecture further includes:
s121: and when the external link is abnormal, reporting the abnormal condition of the external link.
S122: and calling a link exception recovery script to recover the exception of the external link based on the exception condition of the external link.
The link exception recovery script in this embodiment refers to a script for performing recovery processing on an external link exception condition. The link exception recovery script can correspondingly recover the external link exception. If the frame data lacks a frame head, the frame head is added to the frame data.
Further, as shown in fig. 4, in step S20, the determining the data by the timeout predicting method specifically includes the following steps:
s21: and dividing the data according to the frame head and the frame tail to obtain a data packet to be detected.
The data packet to be detected refers to a complete data packet obtained by segmenting data according to the frame head and the frame tail of the data.
S22: and acquiring a preset data packet sending period, and taking the preset data packet sending period as an interval period.
The preset data packet sending period in this embodiment refers to a period for sending data set on the main control board by the user. The preset data packet sending period is set by the user according to actual needs.
S23: and acquiring the sending length of the preset data packet, and calculating the receiving time for completing the receiving of the data packet to be detected based on the sending length of the preset data packet and the module clock.
S24: the reservation duration is calculated based on the interval period and the reception duration.
S25: and judging the data based on the interval period, the sending length, the receiving time length and the reserved time length.
Further, when any one of the conditions that the receiving time length exceeds the interval period, the receiving time length exceeds the reserved time length, the sending length exceeds the preset maximum length, and if the data does not exist in the frame head, the data is judged to have abnormality.
If any one of the conditions exists, the data is judged to be abnormal.
For easy understanding, fig. 5 is a schematic diagram of the timeout prediction method in the present embodiment. Wherein, T1For the reception duration, T2For reserving duration, T3Is a spacing period.
Specifically, the formula for calculating the reserved time length is T2＝T3-T1Wherein, T1For the reception duration, T2For reserving duration, T3Is a spacing period.
Example 2
As shown in fig. 6, the present embodiment is different from embodiment 1 in that the data blocking prevention apparatus of an FPGA architecture includes:
and the channel dynamic opening and closing processing module 10 is used for detecting the data channel to be judged by a channel dynamic opening and closing method to obtain an effective data channel.
The timeout pre-judging processing module 20 is configured to select data of one of the valid data channels for polling, and judge the data by a timeout pre-judging method.
And the polling module 30 is configured to, when the data is abnormal, directly poll the data of the next valid data channel, and repeatedly perform the step of judging the data by using the timeout prejudging method until all valid data channels finish polling.
Further, the channel dynamic opening and closing processing module 10 includes a data channel determining unit to be determined, an external link processing unit, and an effective data channel determining unit.
And the to-be-judged data channel determining unit is used for analyzing the initialization configuration command, and taking the corresponding data channel as the to-be-judged data channel when the initialization configuration command is opened.
And the external link processing unit is used for detecting the external link of the data channel to be judged in real time, closing the corresponding data channel to be judged when the external link is abnormal, responding the configuration command of the data channel to be judged in real time and detecting the external link of the data channel to be judged in real time.
And the effective data channel determining unit is used for taking the data channel to be judged as the effective data channel when the configuration command of the data channel to be judged is open or the external link of the data channel to be judged is recovered to be normal.
Further, the method for preventing data blocking based on the FPGA architecture further comprises a link exception handling unit and an exception recovery handling unit.
And the link exception handling unit is used for reporting the exception condition of the external link when the external link is abnormal.
And the exception recovery processing unit is used for calling the link exception recovery script to recover the exception of the external link based on the exception condition of the external link.
Further, the timeout pre-judging processing module 20 includes a data packet dividing unit, an interval period determining unit, a receiving duration calculating unit, a reserved duration calculating unit, and a timeout pre-judging processing unit.
And the data packet dividing unit is used for dividing the data according to the frame head and the frame tail to obtain the data packet to be detected.
And the interval period determining unit is used for acquiring a preset data packet sending period and taking the preset data packet sending period as the interval period.
And the receiving duration calculation unit is used for acquiring the sending length of the preset data packet and calculating the receiving duration for completing receiving the data packet to be detected based on the sending length of the preset data packet and the module clock.
A reserved time length calculation unit for calculating a reserved time length based on the interval period and the reception time length.
And the overtime prejudgment processing unit is used for judging the data based on the interval period, the sending length, the receiving time length and the reserved time length.
Further, the timeout pre-judging processing unit comprises a first abnormality judging unit, a second abnormality judging unit, a third abnormality judging unit and a fourth abnormality judging unit.
And the first abnormity judgment unit is used for judging that the data is abnormal when the receiving duration exceeds the interval period.
And the second abnormity judgment unit is used for judging that the data is abnormal when the receiving time length exceeds the reserved time length.
And the third anomaly judgment unit is used for judging that the data is abnormal when the sending length exceeds the preset maximum length.
And the fourth abnormity judging unit is used for detecting whether the data has a frame head or not, and judging that the data has abnormity if the data does not have the frame head.
For specific definition of the data blocking prevention device based on the FPGA architecture, reference may be made to the above definition of a data blocking prevention method for the FPGA architecture, which is not described herein again. The modules in the device for preventing data blocking based on the FPGA architecture can be wholly or partially implemented by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
Example 3
The embodiment provides a computer device, which may be a server, and the internal structure diagram of the computer device may be as shown in fig. 7. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a computer readable storage medium, an internal memory. The computer readable storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the computer-readable storage medium. The database of the computer device is used for storing data involved in a method for preventing data blocking of an FPGA framework. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of preventing data blocking for an FPGA architecture.
The present embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and capable of running on the processor, where the processor implements the steps of the method for preventing data blocking of an FPGA architecture in the above embodiments when executing the computer program, for example, steps 10 to S30 shown in fig. 1, or steps shown in fig. 2 to 4, and are not described herein again to avoid repetition. Alternatively, the processor, when executing the computer program, implements the functions of the modules/units of the FPGA architecture for preventing data blocking, such as the functions of the modules 10 to 30 shown in fig. 6, in the above embodiments. To avoid repetition, further description is omitted here.
Example 4
In an embodiment, a computer-readable storage medium is provided, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method for preventing data blocking of an FPGA architecture in the foregoing embodiments are implemented, for example, steps S10 to S30 shown in fig. 1 or steps shown in fig. 2, which are not described herein again to avoid repetition. Alternatively, the processor, when executing the computer program, implements the functionality of the modules/units in this embodiment of an FPGA architecture, such as the functionality of modules 10 to 30 shown in fig. 6, to prevent data blocking. To avoid repetition, further description is omitted here.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A method for preventing data blocking of an FPGA architecture is characterized by comprising the following steps:
detecting a data channel to be judged by a channel dynamic opening and closing method to obtain an effective data channel;
selecting data of one effective data channel for polling, and judging the data by an overtime prejudgment method;
and when the data is abnormal, directly polling the data of the next effective data channel, and repeatedly executing the step of judging the data by the overtime prejudgment method until all the effective data channels finish polling.
2. The method according to claim 1, wherein the detecting the data channel to be determined by the channel dynamic opening and closing method to obtain an effective data channel comprises:
analyzing the initialization configuration command, and taking the corresponding data channel as a data channel to be judged when the initialization configuration command is opened;
detecting an external link of a data channel to be judged in real time, closing the corresponding data channel to be judged when the external link is abnormal, responding a configuration command of the data channel to be judged in real time, and detecting the external link of the data channel to be judged in real time;
and when the configuration command of the data channel to be judged is open or the external link of the data channel to be judged is recovered to be normal, taking the data channel to be judged as an effective data channel.
3. The method for preventing data blocking of FPGA architecture according to claim 2, further comprising:
when the external link is abnormal, reporting the abnormal condition of the external link;
and calling a link exception recovery script to recover the external link exception based on the external link exception.
4. The method according to claim 1, wherein the determining the data by the timeout prejudging method comprises:
dividing the data according to the frame head and the frame tail to obtain a data packet to be detected;
acquiring a preset data packet sending period, and taking the preset data packet sending period as an interval period;
acquiring the sending length of a preset data packet, and calculating the receiving time for completing receiving of a data packet to be detected based on the sending length of the preset data packet and a module clock;
calculating a reserved time length based on the interval period and the receiving time length;
and judging the data based on the interval period, the sending length, the receiving time length and the reserved time length.
5. The method according to claim 1, wherein the determining the data based on the interval period, the transmission length, the reception duration, and the reserved duration includes:
when the receiving duration exceeds the interval period, judging that the data is abnormal;
when the receiving duration exceeds the reserved duration, judging that the data is abnormal;
and when the sending length exceeds the preset maximum length, judging that the data is abnormal.
6. The method according to claim 4, wherein the determining the data by the timeout prejudging method further comprises:
and detecting whether the data has a frame head, and if the data does not have the frame head, judging that the data has abnormality.
7. An apparatus for preventing data blocking for an FPGA architecture, comprising:
the channel dynamic opening and closing processing module is used for detecting the data channel to be judged by a channel dynamic opening and closing method to obtain an effective data channel;
the overtime prejudgment processing module is used for selecting data of one effective data channel for polling and judging the data by an overtime prejudgment method;
and the polling module is used for directly polling the data of the next effective data channel when the data is abnormal, and repeatedly executing the step of judging the data by the overtime prejudgment method until all the effective data channels finish polling.
8. The device for preventing data blocking in FPGA architecture according to claim 7, wherein the channel dynamic open/close processing module comprises:
the device comprises a to-be-judged data channel determining unit, a judging unit and a judging unit, wherein the to-be-judged data channel determining unit is used for analyzing an initialization configuration command, and when the initialization configuration command is opened, the corresponding data channel is used as a to-be-judged data channel;
the external link processing unit is used for detecting an external link of a data channel to be judged in real time, closing the corresponding data channel to be judged when the external link is abnormal, responding to a configuration command of the data channel to be judged in real time and detecting the external link of the data channel to be judged in real time;
and the effective data channel determining unit is used for taking the data channel to be judged as an effective data channel when the configuration command of the data channel to be judged is open or the external link of the data channel to be judged is recovered to be normal.
9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements a method of preventing data blocking for an FPGA architecture as claimed in any one of claims 1 to 6 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, implements a method of preventing data blocking for an FPGA architecture according to any one of claims 1 to 6.
CN202011132959.2A 2020-10-21 2020-10-21 Method, device, equipment and medium for preventing data from being blocked for FPGA (field programmable Gate array) architecture Active CN112235163B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011132959.2A CN112235163B (en) 2020-10-21 2020-10-21 Method, device, equipment and medium for preventing data from being blocked for FPGA (field programmable Gate array) architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011132959.2A CN112235163B (en) 2020-10-21 2020-10-21 Method, device, equipment and medium for preventing data from being blocked for FPGA (field programmable Gate array) architecture

Publications (2)

Publication Number Publication Date
CN112235163A true CN112235163A (en) 2021-01-15
CN112235163B CN112235163B (en) 2021-12-07

Family

ID=74108924

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011132959.2A Active CN112235163B (en) 2020-10-21 2020-10-21 Method, device, equipment and medium for preventing data from being blocked for FPGA (field programmable Gate array) architecture

Country Status (1)

Country Link
CN (1) CN112235163B (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040240528A1 (en) * 2003-05-28 2004-12-02 Kindred Daniel R. Last finger polling for rake receivers
CN1996898A (en) * 2005-12-28 2007-07-11 中兴通讯股份有限公司 A system and method for real time detection of the data channel states
CN101159627A (en) * 2007-11-07 2008-04-09 杭州华三通信技术有限公司 Link state detecting method and apparatus
CN101399811A (en) * 2007-09-27 2009-04-01 华为技术有限公司 Multi-channel data transmitting/receiving and transmission control method, corresponding device
CN101729284A (en) * 2008-10-29 2010-06-09 中兴通讯股份有限公司 Equipment end initiative based method for realizing link polling in management system
WO2011088183A1 (en) * 2010-01-15 2011-07-21 Hunt Technologies, Llc Network event detection
WO2016008240A1 (en) * 2014-07-16 2016-01-21 中兴通讯股份有限公司 Method and device for polling and detecting links
CN108073446A (en) * 2016-11-10 2018-05-25 华为技术有限公司 Overtime pre-judging method and device
CN110120922A (en) * 2019-05-14 2019-08-13 中国核动力研究设计院 A kind of data interaction Network Management System and method based on FPGA

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040240528A1 (en) * 2003-05-28 2004-12-02 Kindred Daniel R. Last finger polling for rake receivers
CN1996898A (en) * 2005-12-28 2007-07-11 中兴通讯股份有限公司 A system and method for real time detection of the data channel states
CN101399811A (en) * 2007-09-27 2009-04-01 华为技术有限公司 Multi-channel data transmitting/receiving and transmission control method, corresponding device
CN101159627A (en) * 2007-11-07 2008-04-09 杭州华三通信技术有限公司 Link state detecting method and apparatus
CN101729284A (en) * 2008-10-29 2010-06-09 中兴通讯股份有限公司 Equipment end initiative based method for realizing link polling in management system
WO2011088183A1 (en) * 2010-01-15 2011-07-21 Hunt Technologies, Llc Network event detection
WO2016008240A1 (en) * 2014-07-16 2016-01-21 中兴通讯股份有限公司 Method and device for polling and detecting links
CN108073446A (en) * 2016-11-10 2018-05-25 华为技术有限公司 Overtime pre-judging method and device
CN110120922A (en) * 2019-05-14 2019-08-13 中国核动力研究设计院 A kind of data interaction Network Management System and method based on FPGA

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
SJ LI等: "Multi-link cooperative polling scheme for UAV data link based on Gilbert-Elliot channel", 《IEEE》 *
李庆安: "星载数据处理虚拟多通道大容量存储技术研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》 *

Also Published As

Publication number Publication date
CN112235163B (en) 2021-12-07

Similar Documents

Publication Publication Date Title
KR101225374B1 (en) Apparatus and method for device management in mobile communication terminal
CN107294808B (en) Interface test method, device and system
CN110149220B (en) Method and device for managing data transmission channel
US10447561B2 (en) BFD method and apparatus
CN112035182A (en) Kong-based API gateway monitoring method and system
CN100466556C (en) Network device management method and system
CN114448896B (en) Network optimization method and device
CN107395451B (en) Processing method, device and equipment for internet traffic abnormity and storage medium
CN113709126A (en) Network protocol security fuzzy test method, device, equipment and storage medium
CN112511422A (en) Data transmission method and device, computer equipment and storage medium
CN112235163B (en) Method, device, equipment and medium for preventing data from being blocked for FPGA (field programmable Gate array) architecture
CN113207146A (en) Wireless communication network quality monitoring system and method
CN111314290A (en) Method and device for protecting continuity of WEB application firewall service and electronic equipment
CN105530110A (en) Network failure detection method and related network elements
CN105323093A (en) Fault information collection method, device and system
KR101263218B1 (en) Method and apparatus for aggregating one packet of one session
CN112134760A (en) Link state monitoring method, device, equipment and computer readable storage medium
CN109815052A (en) Method, apparatus, computer equipment and the storage medium of exception service processing
EP3772834B1 (en) A method of predicting the time course of a plurality of data relative to a telephony infrastructure for network function virtualization
CN114826886B (en) Disaster recovery method and device for application software and electronic equipment
CN115955414B (en) Remote control abnormality analysis method and related device for distribution network automation terminal
US11849064B1 (en) Techniques for detecting calling anomalies in inbound call traffic in telecommunications networks
CN112311765B (en) Message detection method and device
CN113595837B (en) Communication protocol management method, device, electronic equipment and storage medium
Mendiratta et al. Rich network anomaly detection using multivariate data

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant