CN112219276A - Chip and chip packaging method - Google Patents
Chip and chip packaging method Download PDFInfo
- Publication number
- CN112219276A CN112219276A CN201880094194.2A CN201880094194A CN112219276A CN 112219276 A CN112219276 A CN 112219276A CN 201880094194 A CN201880094194 A CN 201880094194A CN 112219276 A CN112219276 A CN 112219276A
- Authority
- CN
- China
- Prior art keywords
- die
- chip
- semiconductor
- insulating material
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 181
- 239000011810 insulating material Substances 0.000 claims description 67
- 239000000758 substrate Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 20
- 230000008569 process Effects 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000012858 packaging process Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 241000701384 Tipula iridescent virus Species 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A chip and a chip packaging method are provided to increase the number of interconnected channels in the chip in a unit area, thereby improving the bandwidth of the chip and controlling the cost of chip packaging. The chip includes: a wiring layer; a first bare chip and a semiconductor board which are arranged on the wiring layer; wherein a first semiconductor channel is provided in the semiconductor board; a second die disposed on the first die and the semiconductor board; wherein the second die is coupled with the routing layer through the first semiconductor via.
Description
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a chip and a chip packaging method.
With the development of semiconductor technology, electronic devices are becoming thinner and smaller, and more performance and features are being integrated into smaller and smaller spaces, so the status of chip packaging technology in the industry chain of electronic devices is becoming more important.
Currently, a Package On Package (POP) technology and a fan-out wafer level package (FOWLP) technology adopted in the industry are combined, and chips are stacked in a thickness direction to improve an integration level of chip packaging. Since the chips in the above-mentioned packaging technology are interconnected by solder balls (solder balls)/micro bumps (micro bumps), the requirement of high interconnection density chip packaging cannot be met, and thus Hybrid Bonding (HB) technology has been developed.
In a chip package structure adopting the HB package technology in the prior art, upper and lower chips are usually interconnected by a hybrid bonding structure, a through insulation layer via (TIV) in a filling material between the upper and lower chips, and a wiring layer (RDL). However, under the existing process technology capability condition, the feature size of the insulating layer through hole is large, the interconnection density is low, the number of vertical interconnection channels between the upper chip and the lower chip is limited, and thus the bandwidth of the upper chip (such as a memory) is limited, and if the package is required to reach a certain number of insulating layer through holes, the area of the package must be increased. In addition, the existing manufacturing process of the insulating layer through hole is immature, the cost is high, and the packaging cost of the chip is high.
Disclosure of Invention
The application provides a chip and a chip packaging method, which are used for solving the problems of low bandwidth and high packaging cost of the conventional chip.
In a first aspect, the present application provides a chip, comprising: a wiring layer; a first bare chip and a semiconductor board which are arranged on the wiring layer; wherein a first semiconductor channel is provided in the semiconductor board; a second die disposed on the first die and the semiconductor board; wherein the second die is coupled with the routing layer through the first semiconductor via.
Through the scheme, the first bare chip and the semiconductor board in the chip are arranged on the wiring layer, the second bare chip is arranged on the first bare chip and the semiconductor board, and the second bare chip is coupled with the wiring layer through the semiconductor channel in the semiconductor board, so that the second bare chip can be interconnected with the first bare chip through the semiconductor channel and the wiring layer. Compared with the TIV manufactured in the insulating material in the prior art, the characteristic size of the semiconductor channel manufactured in the semiconductor board is smaller, the number of the semiconductor channels in a unit area can be effectively increased, the interconnection density and the bandwidth of a chip can be further increased, and the area of chip packaging can be controlled. Moreover, compared with the prior art in which the TIV is made in the insulating material, the cost for making the semiconductor channel in the semiconductor board is lower, and the making process is more mature.
In addition, since the semiconductor channels are made in the semiconductor board in the chip, the risk of warping of the chip can be reduced when the thermal expansion coefficients of the material of the semiconductor board and the material of the first die and the second die are close compared to the prior art, in which the chip is filled with less insulating material.
In one possible embodiment, the first die may be a logic die (logic die) such as a processor or an intellectual property IP core, and the second die may be a memory (including a random access memory SRAM and a dynamic random access memory DRAM), a micro-electro-mechanical system MEMS, a passive device or a patch board, or the like; alternatively, the first die may be a memory, MEMS, passive device or interposer, etc., and the second die may be a logic die, such as a processor or intellectual property core. The semiconductor board can be a silicon board or a silicon bridge, and the semiconductor channel can be a Through Silicon Via (TSV). The wiring layer may be a fan-out rewiring FO-RDL layer or a Mz metal wiring layer.
In a possible embodiment, the active surface of the first die and the active surface of the second die face the wiring layer, and a plurality of pads are disposed on the active surface of the second die and the passive surface of the first die; the second die is coupled to the first semiconductor channel through a portion of the plurality of bonding pads, and the second die is coupled to the first die through another portion of the plurality of bonding pads.
In a possible embodiment, the active surface of the first die faces the wiring layer, the active surface of the second die faces the first die, and a plurality of bonding pads are disposed on the active surfaces of the second die and the first die; the second die is coupled to the first semiconductor channel through a portion of the plurality of bonding pads, and the second die is coupled to the first die through another portion of the plurality of bonding pads.
In a possible implementation manner, a second semiconductor channel is disposed in the semiconductor substrate of the first die, and the first die is further coupled with the second die and the wiring layer through the second semiconductor channel, so that a signal transmission path between the first die and the second die can be effectively shortened, and a response speed of a chip is improved.
In a possible embodiment, in order to reduce the risk of warpage of the chip, the material of the semiconductor substrate in the first die and the material of the semiconductor substrate in the second die are the same (or similar) as the thermal expansion coefficient of the semiconductor board. For example, the semiconductor substrate in the first die, the semiconductor substrate in the second die and the semiconductor board are made of the same material.
In a possible embodiment, the chip further includes an insulating material that encapsulates the first die, the semiconductor board, and the second die.
Further, the insulating material includes a first insulating material and a second insulating material, wherein the first insulating material encapsulates the first die and the semiconductor board, and the second insulating material encapsulates the second die. Wherein, the first insulating material can be silicon oxide or silicon nitride. The second insulating material can be silicon oxide or silicon nitride, and under the condition that the requirement on the thickness of the chip packaging body is not high, underfill, molding compound or other epoxy resin can be used, so that the manufacturing difficulty of the insulating material in the chip packaging process can be effectively reduced. In addition, the underfill, the molding compound or other epoxy resin is used as the second insulating material, the thickness of the packaging body is thicker, and when the wiring layer is manufactured, a silicon slide is not needed, so that the process is simple and the cost is low.
In one possible embodiment, the chip further includes solder balls disposed under the wiring board for interconnecting the first die and the second die with the outside (such as a printed circuit board PCB, other chips, etc.), so that the chip can be directly interconnected with the outside through the solder balls without a substrate, thereby reducing the package thickness of the chip and improving the heat dissipation performance.
In a possible embodiment, the chip includes at least two of the first dies, or includes at least two of the second dies, or includes at least two of the first dies and at least two of the second dies. The plurality of first bare chips can be distributed on the same layer or different layers, and the plurality of second bare chips can be distributed on the same layer or different layers.
In one possible embodiment, the at least two first dies are stacked, and the active surfaces of two adjacent first dies are coupled with each other.
In one possible embodiment, the at least two second dies are stacked, and the active surfaces of two adjacent second dies are coupled with each other.
In a second aspect, the present application provides an integrated chip, where the integrated chip includes a first chip and a second chip, where the first chip is the chip described in any one of the possible implementations of the first aspect, and the first chip and the second chip are packaged together.
In one possible embodiment, the first chip may be packaged with the second chip by a package on package POP.
In a third aspect, the present application provides a chip packaging method, including: bonding a semiconductor board and a first die on a first carrier; wherein a first semiconductor channel is processed in the semiconductor board; bonding a second die together with the semiconductor board and the first die; removing the first carrier, and preparing a wiring layer on the semiconductor board and the surface of the first bare chip bonded with the first carrier; wherein the second die is coupled with the routing layer through the first semiconductor via.
In a possible embodiment, bonding the second die with the semiconductor board and the first die includes: preparing a first insulating material to form a first packaging body; wherein the first insulating material encapsulates the semiconductor board and the first die; preparing a plurality of pads on the first insulating material to form a second packaging body; a second die is coupled to the first semiconductor via through a portion of the plurality of bonding pads and to the first die through another portion of the plurality of bonding pads to form a third package.
In one possible embodiment, after preparing the first insulating material and before preparing the pads on the first insulating material, the first insulating material is polished to expose the first semiconductor channels in the semiconductor board. Specifically, the polishing may be performed by a chemical mechanical polishing CMP method.
In one possible embodiment, after preparing a plurality of pads on the first insulating material, the second die is coupled to the first semiconductor via through a portion of the plurality of pads, and before being coupled to the first die through another portion of the plurality of pads, a polishing (e.g., CMP) process may be performed to remove excess bonding dielectric layer structure on the plurality of pads.
In one possible embodiment, after the semiconductor board and the first die are bonded on the first carrier and before the first insulating material is prepared, the semiconductor board and the first die may be thinned to the same thickness.
In a possible embodiment, if the thickness of the second insulating material is smaller than a set value, the fourth package body is further bonded to the second carrier before a wiring layer is prepared on the surface of the semiconductor board and the first die bonded to the first carrier; and removing the second carrier after preparing wiring layers on the faces of the semiconductor board and the first bare chip bonded with the first carrier.
In one possible embodiment, after a wiring layer is prepared on the surface of the semiconductor board and the surface of the first die bonded to the first carrier, a plurality of solder balls can be prepared under the wiring layer.
FIG. 1 is a schematic diagram of a chip structure of a 3D IC package adopting HB technology in the prior art;
fig. 2 is a schematic structural diagram of a chip according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a die provided in an embodiment of the present application;
fig. 4 is a second schematic structural diagram of a chip according to an embodiment of the present disclosure;
fig. 5a is a third schematic structural diagram of a chip according to an embodiment of the present disclosure;
fig. 5b is a fourth schematic structural diagram of a chip according to an embodiment of the present disclosure;
fig. 6 is a fifth schematic structural diagram of a chip according to an embodiment of the present disclosure;
fig. 7 is a sixth schematic structural view of a chip according to an embodiment of the present application;
fig. 8 is a seventh schematic structural diagram of a chip according to an embodiment of the present disclosure;
fig. 9a is a schematic structural diagram of an integrated chip according to an embodiment of the present disclosure;
fig. 9b is a schematic structural diagram of another integrated chip provided in the embodiment of the present application;
fig. 10 is a schematic flowchart of a chip packaging method according to an embodiment of the present application;
fig. 11 is a schematic flowchart of another chip packaging method according to an embodiment of the present application;
fig. 12 is a flowchart illustrating a chip packaging method according to an embodiment of the present disclosure.
To meet the requirements of high interconnection density chip packaging, Hybrid Bonding (HB) technology is used for chip packaging. As shown in fig. 1, a conventional chip structure of a three-dimensional Integrated Circuit (3D IC) package using an HB technology is composed of an upper layer 100, a lower layer 200, a wiring layer 300 (RDL), and solder balls 400, and the upper layer 100 and the lower layer 200 are bonded together by a hybrid bonding structure 500. The upper layer 100 includes an upper layer die (die)101 and a filling material 102, the lower layer 200 includes a lower layer die 201 and a filling material 202, a Through Insulator Via (TIV) 203 is fabricated in the filling material 202, an active surface 103 of the upper layer die 101 is connected to a wiring layer 300 through a hybrid bonding structure 500 and the TIV 203, an active surface 204 of the lower layer die 201 is connected to the wiring layer 300, and a solder ball 400 is used for interconnecting the upper layer die 101, the lower layer die 201 and an external Printed Circuit Board (PCB).
The upper die 101 and the wiring layer 300 are vertically interconnected through the TIV 203 in the filling material 202, and the TIV manufactured under the existing process technology capability condition has large characteristic size and low interconnection density, so that the number of vertical interconnection channels in a chip is limited, and the bandwidth of the upper die is further limited. If the chip package requires a certain number of insulation layer vias (TIVs), the area of the chip package must be increased. Moreover, under the existing process capability conditions, the manufacturing process of the TIV is not mature, the cost is high, and the yield of the packaged chip is not high.
In order to solve the above problems in the conventional chip packaging structure, the present application provides a chip and a chip packaging method, so as to increase the number of interconnection channels in the chip in a unit area, further improve the bandwidth of the chip, and control the chip packaging cost.
In the present embodiment, a plurality of the reference numerals means two or more. In addition, it should be understood that the terms first, second, etc. in the description of the embodiments of the present application are used for distinguishing between the descriptions and not for indicating or implying relative importance or order.
In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings.
As shown in fig. 2, a chip 200 provided in the embodiment of the present application includes: a wiring layer 210, a first die 220, a semiconductor board 230, and a second die 240. Wherein the first die 220 and the semiconductor board 230 are disposed on the wiring layer 210, and a first semiconductor channel 231 is disposed in the semiconductor board 230; the second die 240 is disposed on the first die 220 and the semiconductor board 230, and the second die 240 is coupled with the wiring layer 210 through the first semiconductor via 231.
Dice (die) are dies of the IC before it is packaged, each die being an independent, functionally unpackaged chip that may be comprised of one or more circuits. As shown in fig. 3, a bare chip generally includes a semiconductor substrate on which semiconductor devices such as transistors are formed, and a circuit layer disposed on the semiconductor substrate, in which multiple circuit layers are disposed, and the circuit layer is generally provided with various functional circuits, and these circuits are coupled with the semiconductor devices on the semiconductor substrate, so as to form a complete chip circuit structure. The surface of the side of the die where the circuit layer is located is referred to as an active surface, and the surface of the side of the die where the semiconductor substrate is located is referred to as a passive surface.
Specifically, the first die 220 may be a logic die (logic die), such as a processor or an Intellectual Property (IP) core (Cores), and the second die 240 may be a memory (including a random-access memory (SRAM) and a dynamic random-access memory (DRAM)), a micro-electro-mechanical system (MEMS), a passive device (passive device), an interposer (interposer), or the like; alternatively, the first die 220 may be a memory, MEMS, passive device or interposer, etc., and the second die 240 may be a logic die, such as a processor or intellectual property core. The semiconductor plate 230 may be a silicon plate or a silicon bridge (dummy silicon bridge), the semiconductor channel 231 may be a Through Silicon Via (TSV), and the semiconductor channel 231 is plated with a metal layer or filled with a metal pillar, so that the semiconductor channel can be used as a signal path, which is also the case with the TIV in the prior art. The wiring layer 210 may be a fan-out redistribution layer (FO-RDL) layer or a common metal wiring layer on which signal traces are disposed.
It should be noted that, the present application does not limit the specific shape of the semiconductor board 230, the shape of the semiconductor board is not limited to a flat plate structure, and any semiconductor board that can make the semiconductor channel 231, and the second die 240 and the wiring layer 210 and the first die 220 are coupled through the semiconductor channel 231 is suitable for the present application.
In a specific implementation, the second die 240 may be coupled to the semiconductor channels 231 in the semiconductor board 230 and the first die 220 by any one of, but not limited to:
first, as shown in fig. 2, the active surface 221 of the first die 220 faces the wiring layer 210, the active surface 241 of the second die 240 faces the first die 220, and a plurality of pads (pads) 250 are disposed on the active surface 241 of the second die 240 and the active surface 221 of the first die 220. The second die 240 is coupled to the first semiconductor channel 231 through a portion of the plurality of pads 250, and the second die 240 is coupled to the first die 220 through another portion of the plurality of pads 250.
In a second mode, as shown in fig. 4, the active surface 221 of the first die 220 and the active surface 241 of the second die 240 both face the wiring layer 210, and a plurality of pads 250 are disposed on the active surface 241 of the second die 240 and the passive surface 222 of the first die 220. The second die 240 is coupled to the first semiconductor channel 231 through a portion of the plurality of pads 250, and the second die 240 is coupled to the first die 220 through another portion of the plurality of pads 250.
It should be noted that a part of the pads 250 may vertically correspond to the first semiconductor channels 231, or the pads 250 may not vertically correspond to the first semiconductor channels 231, and are interconnected with the first semiconductor channels 231 by a wiring manner.
Further, as shown in fig. 5a or 5b, a second semiconductor 223 channel is disposed in the semiconductor substrate of the first die 220, and the first die 220 is further coupled with the second die 240 and the wiring layer 210 through the second semiconductor 223 channel, so that a signal transmission path between the first die 220 and the second die 220 can be effectively shortened, and a response speed of a chip is improved.
The prior art TIV is fabricated in an insulating material, typically silicon oxide or silicon nitride, around which the die is also typically wrapped. While the semiconductor substrate of the die is mainly made of Silicon (Silicon), the thermal expansion coefficients of the semiconductor substrate of the die and the insulating material are not matched, so that the whole chip has a large warping (warping) risk in the packaging process. The present invention, however, reduces the volume of insulating material around or between the dies by disposing the semiconductor board between the second die 240 and the wiring layer 230. Both the bare chip and the semiconductor board can be manufactured by a preprocessing process, the form and the stress of the semiconductor board are more stable than those of an insulating material filled in the packaging process, and the semiconductor board replaces the insulating material, so that the stress generated in the packaging process is reduced, and the warping risk is reduced. To further reduce the risk of warpage of the chip 200, the material of the semiconductor substrate in the first die 220 and the material of the semiconductor substrate in the second die 240 have the same (or similar) thermal expansion coefficient as the semiconductor board 230. Since the circuit layers in the dies are thin and mostly semiconductor substrates (as shown in fig. 3), when the thermal expansion coefficients of the material of the semiconductor substrate in the first die 220 and the material of the semiconductor substrate in the second die 240 and the semiconductor board 230 are matched, the deformation of the first die 220, the semiconductor board 230 and the second die 240 under the same condition can be substantially the same, and the warpage risk of the chip 200 is further reduced. For example, the semiconductor substrate in the first die 220, the semiconductor substrate in the second die 240 and the semiconductor board 230 are made of the same material.
In the embodiment of the present application, the number of the first die 220, the semiconductor board 230, and the semiconductor channels 231 in the semiconductor board 230 in the chip 200, the number of the second die 240, and the arrangement of the first die 220, the semiconductor board 230, and the second die 240 are not limited, and the chip structure shown in fig. 2 is only an example and is not limited to the present application. The number of the first dies 220, the semiconductor boards 230, and the semiconductor channels 231 in the semiconductor boards 230 in the chip 200, and the number of the second dies 240 are determined according to specific performance (such as bandwidth, area, processing speed, etc.) requirements of the chip 200, for example, the chip 200 is required to have a larger bandwidth, and the chip 200 may include more semiconductor boards 230 and semiconductor channels 231.
In one possible embodiment, the chip 220 includes at least two of the first dies 220, or includes at least two of the second dies 240, or includes at least two of the first dies 220 and at least two of the second dies 240. The plurality of first dies 210 may be distributed on the same layer or different layers, and the plurality of second dies 240 may be distributed on the same layer (e.g., the second dies 240 in fig. 2) or different layers.
Specifically, when the plurality of first dies 210 are distributed in different layers, the at least two first dies 210 can be arranged in a stacked manner, and the active surfaces of two adjacent first dies 210 are coupled with each other. In two adjacent first dies 210, the active surface of the upper first die may be coupled to the active surface of the lower first die through a semiconductor via (e.g., TSV) provided in the lower first die.
When the plurality of second dies 240 are distributed on different layers, the at least two second dies 240 can be stacked, and the active surfaces of two adjacent second dies 240 are coupled with each other, as shown in fig. 6. In two adjacent second dies 240, the active surface of the upper second die may be coupled to the active surface of the lower second die through a semiconductor via (e.g., TSV) provided in the lower second die.
It should be noted that, in the embodiment of the present application, the direction of the active surface (or the passive surface) of each of the at least two first dies 220 in the stacked arrangement and the direction of the active surface (or the passive surface) of each of the at least two second dies 240 in the stacked arrangement are not defined. For example, the active side of each of the at least two first dies 220 can be facing the routing layer 210, or the passive side of each of the at least two first dies 220 can be facing the routing layer 210; alternatively, the passive side of a portion of the at least two first dies 220 faces the routing layer 210, and the active side of another portion of the at least two first dies 220 faces the routing layer 210. The direction of the active surface (or passive surface) of each of the at least two second dies 240 is similar to that of the first die 220, and the description thereof is omitted here.
In a specific implementation, as shown in fig. 2, the chip 200 further includes an insulating material 260, and the insulating material 260 encapsulates the first die 220, the semiconductor board 230, and the second die 240. Further, as shown in fig. 7, the insulating material 260 includes a first insulating material 261 and a second insulating material 262, wherein the first insulating material 261 wraps the first die 220 and the semiconductor board 230, and the second insulating material 262 wraps the second die 240.
In the chip packaging process, the requirement on the thickness of the first insulating material 261 is usually high, and therefore, Silicon Oxide (Silicon Oxide) or Silicon Nitride (Nitride Oxide) is generally used for the first insulating material 261. For the second insulating material 262, besides silicon oxide or silicon nitride, under some scenes that the requirement on the thickness of the chip package is not high, underfill (underfill), molding compound (molding compound) or other epoxy resin (epoxy) may also be used, so that the difficulty in manufacturing the insulating material in the chip packaging process may be effectively reduced. In addition, the underfill, the molding compound or other epoxy resin is used as the second insulating material 262, so that the thickness of the package is relatively thick, a silicon carrier (support silicon) is not needed when the wiring layer is manufactured, the process is simple, and the cost is low.
Further, as shown in fig. 8, the chip 200 further includes solder balls 270, and the solder balls 270 are disposed under the wiring board 210 and are used for interconnecting the first die 210 and the second die 240 with the outside (such as a PCB, other chips, etc.), so that the chip 200 can be directly interconnected with the outside through the solder balls 270 without a substrate, thereby reducing the package thickness of the chip 200 and improving the heat dissipation performance.
With the above scheme, a first die and a semiconductor board 230 in the chip 200 are disposed on a wiring layer 210, a second die 240 is disposed on the first die 220 and the semiconductor board 230, and the second die 240 is coupled to the wiring layer 210 through a semiconductor via 231 in the semiconductor board 230, so that the second die 240 can be interconnected with the first die 220 through the semiconductor via 231 and the wiring layer 210. Compared with the TIV fabricated in the insulating material in the prior art, the feature size of the semiconductor channels 231 fabricated in the semiconductor board 230 is smaller, so that the number of the semiconductor channels in a unit area can be effectively increased, the interconnection density and the chip bandwidth can be further increased, and the chip packaging area can be controlled. Also, the cost of fabricating the semiconductor channel 231 in the semiconductor plate 230 is lower and the fabrication process is more mature than fabricating TIVs in insulating materials as in the prior art.
In addition, since the semiconductor channels 231 are formed in the chip 200 in the semiconductor board 230, compared to the prior art, the semiconductor board 230 is filled with less insulating material, so that when the thermal expansion coefficients of the material of the semiconductor board 230 and the material of the first die 220 and the second die 240 are close, the risk of warping of the chip 200 can be reduced.
Based on the above embodiments, the present application further provides an integrated chip, where the integrated chip includes a first chip and a second chip, the first chip is the chip 200 described above in one possible implementation, and the first chip and the second chip are packaged together.
Wherein the first chip may be packaged with the second chip by a Package On Package (POP). For example, as shown in fig. 9a, the first chip may be packaged with the second chip by a FOWLP method, or the first chip may be packaged with the second chip by another POP method, as shown in fig. 9 b.
Based on the above embodiments, the present application further provides a chip packaging method for packaging and forming the chip 200, as shown in fig. 10, the method mainly includes the following steps:
s1001: bonding the first die 220 and the semiconductor board 230 on a first carrier; wherein a first semiconductor channel 231 is processed in the semiconductor board 230;
s1002: bonding a second die 240 with the semiconductor board 230 and the first die 220;
s1003: removing the first carrier, and preparing a wiring layer 210 on the semiconductor board 230 and the surface of the first die 220 bonded to the first carrier; wherein the second die 240 is coupled with the routing layer 210 through the first semiconductor 231 lane.
In step 1002, bonding the second die 240 with the semiconductor board 230 and the first die 220 includes:
i. preparing a first insulating material 261 to form a first package body; wherein the first insulating material 261 encapsulates the semiconductor board 230 and the first die 220;
ii. Preparing a plurality of pads 250 on the first insulating material 261 to form a second package body;
the pad (pad)250 can be manufactured by photolithography and electroplating processes, and can be used as an HB metal structure, and an HB bonding layer dielectric layer structure is manufactured by a Chemical Vapor Deposition (CVD) process.
iii, coupling a second die 240 with the first semiconductor channel 231 through a portion of the plurality of bonding pads 250 and with the first die 220 through another portion of the plurality of bonding pads 250 to form a third package. The second die is also provided with a plurality of pads for bonding with the second package body.
After the first insulating material 261 is prepared, and before the pads 250 are prepared on the first insulating material 261, the first insulating material 261 is polished to expose the first semiconductor channels 231 in the semiconductor board 230. Specifically, the polishing may be performed by Chemical Mechanical Polishing (CMP).
After preparing a plurality of pads on the first insulating material 261, the second die 240 may be coupled to the first semiconductor via 231 through a portion of the plurality of pads 250, and may be further subjected to a polishing (e.g., CMP) process to remove excess bonding dielectric layer structure on the plurality of pads 250 before being coupled to the first die 220 through another portion of the plurality of pads 250.
Further, since the thickness of the semiconductor board 230 is not necessarily the same as the thickness of the first die 220, the semiconductor board and the first die are also thinned to the same thickness after the step S1001 is performed and before the first insulating material 261 is prepared.
Since only the passive side of the first die 220 can be thinned, when the chip shown in fig. 2 is formed by packaging, after the thinning process, the semiconductor board 230 and the thinned surface of the first die 220 are bonded to a third carrier, so that the active side of the first die 220 faces upward, the first carrier is removed, and then the subsequent packaging process is continued.
After step S1002 is performed, before step S1003 is performed, a second insulating material 262 is also prepared to form a fourth package body; wherein the second insulating material 262 encapsulates the second die 240. After the second insulating material 262 is prepared, the second insulating material 262 may be polished.
Specifically, if the thickness of the second insulating material 262 is smaller than a predetermined value, the fourth package is further bonded to a second carrier before the wiring layer 210 is prepared on the surface of the semiconductor board 230 and the first die 220 bonded to the first carrier; after the wiring layer 210 is prepared on the face of the semiconductor board 230 and the first die 220 bonded to the first carrier, the second carrier is removed, as shown in fig. 11.
In addition, after step S1003 is executed, a plurality of solder balls may be fabricated below the wiring layer.
The chip packaging method provided in the present application will be described in detail below by taking the example of packaging and forming the chip 200 shown in fig. 4.
Packaging to form the chip 200 shown in fig. 4 mainly includes the following steps:
s1201: bonding the semiconductor board 230 and the first die 220 on the first carrier; wherein a first semiconductor channel 231 is processed in the semiconductor board 230.
S1202: the semiconductor board 230 and the first die are thinned to the same thickness (typically to around 20 microns).
S1203: a first insulating material 261 is prepared, and the first insulating material 261 may be silicon oxide or silicon nitride.
S1204: a CMP process is performed to remove the excess first insulating material 261 and expose the semiconductor channels 231 in the semiconductor board 230.
S1205: a plurality of pads 250 are prepared on the post-CMP surface as HB bonding structures. The HB bonding structure comprises an HB bonding layer metal structure and an HB bonding layer medium structure.
S1206: and performing CMP treatment to remove the redundant HB bonding layer medium structure.
S1207: the second die 240 is bonded to the package obtained in step 6 using HB techniques. A plurality of bonding pads 250 are also prepared on the bonding surface of the second die 240 as an HB bonding structure, so that the second die 240 can be interconnected with the semiconductor channels 231 in the semiconductor board 230 after bonding.
S1208: a second insulating layer 262 is prepared. Wherein the thickness of the second insulating layer 262 is greater than the set value.
S1209: the first carrier is removed, and the wiring layer 210 and the solder balls 270 are prepared.
The process of packaging and forming the chip 200 shown in fig. 2 is similar to the process of S1203-S1209, and will not be repeated herein, except that after the step S1202, the semiconductor board 230 and the thinned surface of the first die 220 are bonded on a third carrier, so that the active surface of the first die 220 faces upward, the first carrier is removed, and then the subsequent packaging process is continued.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.
Claims (13)
- A chip, comprising: a wiring layer;a first bare chip and a semiconductor board which are arranged on the wiring layer; wherein a first semiconductor channel is provided in the semiconductor board;a second die disposed on the first die and the semiconductor board; wherein the second die is coupled with the routing layer through the first semiconductor via.
- The chip of claim 1, wherein the active surface of the first die and the active surface of the second die are both facing the routing layer, the active surface of the second die and the passive surface of the first die having a plurality of pads disposed thereon;the second die is coupled to the first semiconductor channel through a portion of the plurality of bonding pads, and the second die is coupled to the first die through another portion of the plurality of bonding pads.
- The chip of claim 1, wherein an active surface of the first die faces the routing layer, an active surface of the second die faces the first die, and a plurality of pads are disposed on the active surface of the second die and the active surface of the first die;the second die is coupled to the first semiconductor channel through a portion of the plurality of bonding pads, and the second die is coupled to the first die through another portion of the plurality of bonding pads.
- The chip of any of claims 1-3, wherein the semiconductor substrate of the first die has a second semiconductor via disposed therein, the first die further coupled to the second die and the routing layer through the second semiconductor via.
- The chip of any one of claims 1-4, wherein a material of the semiconductor substrate in the first die, a material of the semiconductor substrate in the second die, and a material of the semiconductor board have the same coefficient of thermal expansion.
- The chip of any one of claims 1-5, wherein the chip comprises at least two of the first dies; and/or, the chip comprises at least two of the second dies.
- The chip of claim 6, in which the at least two first dies are arranged in a stack, active faces of adjacent two of the first dies being coupled to each other.
- The chip of claim 6, in which the at least two second dies are arranged in a stack, active faces of adjacent two of the second dies being coupled to each other.
- The chip of any one of claims 1-8, further comprising an insulating material encasing the first die, the semiconductor board, and the second die.
- The chip of claim 9, wherein the insulating material comprises a first insulating material and a second insulating material, wherein the first insulating material encapsulates the semiconductor board and the first die, and the second insulating material encapsulates the second die.
- An integrated chip comprising a first chip and a second chip, the first chip being as claimed in any one of claims 1 to 9, the first chip being packaged together with the second chip.
- A method of chip packaging, comprising:bonding a semiconductor board and a first die on a first carrier; wherein a first semiconductor channel is processed in the semiconductor board;bonding a second die together with the semiconductor board and the first die;removing the first carrier, and preparing a wiring layer on the semiconductor board and the surface of the first bare chip bonded with the first carrier; wherein the second die is coupled with the routing layer through the first semiconductor via.
- The method of claim 12, wherein bonding a second die with the semiconductor board and the first die together comprises:preparing a first insulating material to form a first packaging body; wherein the first insulating material encapsulates the semiconductor board and the first die;preparing a plurality of pads on the first insulating material to form a second packaging body;a second die is coupled to the first semiconductor via through a portion of the plurality of bonding pads and to the first die through another portion of the plurality of bonding pads to form a third package.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2018/117314 WO2020103162A1 (en) | 2018-11-23 | 2018-11-23 | Chip and chip packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112219276A true CN112219276A (en) | 2021-01-12 |
Family
ID=70774302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201880094194.2A Pending CN112219276A (en) | 2018-11-23 | 2018-11-23 | Chip and chip packaging method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN112219276A (en) |
| WO (1) | WO2020103162A1 (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110037157A1 (en) * | 2009-08-17 | 2011-02-17 | Shin Hangil | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
| WO2013127045A1 (en) * | 2012-03-01 | 2013-09-06 | 江苏物联网研究发展中心 | Hybrid bonding structure used for three-dimensional integration and bonding method therefor |
| CN106252324A (en) * | 2015-06-09 | 2016-12-21 | 华亚科技股份有限公司 | Package on package stacked package component |
| CN106486383A (en) * | 2015-08-31 | 2017-03-08 | 台湾积体电路制造股份有限公司 | Encapsulating structure and its manufacture method |
| US20170186732A1 (en) * | 2015-12-29 | 2017-06-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seal-ring structure for stacking integrated circuits |
| CN107785358A (en) * | 2016-08-25 | 2018-03-09 | Imec 非营利协会 | Semiconductor die package and the method for this encapsulation of production |
| CN207149555U (en) * | 2017-07-25 | 2018-03-27 | 华天科技（昆山）电子有限公司 | Slim 3D fan-out packaging structures |
-
2018
- 2018-11-23 WO PCT/CN2018/117314 patent/WO2020103162A1/en active Application Filing
- 2018-11-23 CN CN201880094194.2A patent/CN112219276A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110037157A1 (en) * | 2009-08-17 | 2011-02-17 | Shin Hangil | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
| WO2013127045A1 (en) * | 2012-03-01 | 2013-09-06 | 江苏物联网研究发展中心 | Hybrid bonding structure used for three-dimensional integration and bonding method therefor |
| CN106252324A (en) * | 2015-06-09 | 2016-12-21 | 华亚科技股份有限公司 | Package on package stacked package component |
| CN106486383A (en) * | 2015-08-31 | 2017-03-08 | 台湾积体电路制造股份有限公司 | Encapsulating structure and its manufacture method |
| US20170186732A1 (en) * | 2015-12-29 | 2017-06-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seal-ring structure for stacking integrated circuits |
| CN107785358A (en) * | 2016-08-25 | 2018-03-09 | Imec 非营利协会 | Semiconductor die package and the method for this encapsulation of production |
| CN207149555U (en) * | 2017-07-25 | 2018-03-27 | 华天科技（昆山）电子有限公司 | Slim 3D fan-out packaging structures |
Non-Patent Citations (1)
| Title |
|---|
| 唐和明等: "《先进倒装芯片封装技术》", 28 February 2017, 化学工业出版社 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020103162A1 (en) | 2020-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11587909B2 (en) | High bandwidth die to die interconnect with package area reduction | |
| CN107851615B (en) | Independent 3D stacking | |
| US9768144B2 (en) | Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate | |
| KR101884971B1 (en) | Fan-out stacked system in package(sip) having dummy dies and methods of making the same | |
| JP5246831B2 (en) | Electronic device and method of forming the same | |
| US9991190B2 (en) | Packaging with interposer frame | |
| US8004079B2 (en) | Chip package structure and manufacturing method thereof | |
| CN110739229A (en) | Manufacturing method of chip packaging body structure | |
| US20120146216A1 (en) | Semiconductor package and fabrication method thereof | |
| US11145627B2 (en) | Semiconductor package and manufacturing method thereof | |
| US20230197563A1 (en) | Semiconductor chip device integrating thermal pipes in three-dimensional packaging | |
| US20230230902A1 (en) | Semiconductor package structure and manufacturing method thereof | |
| US20230029098A1 (en) | Semiconductor package | |
| KR100983471B1 (en) | Semiconductor device and method for manufacturing the same | |
| CN114203562A (en) | Packaging method and packaging structure of multilayer stacked high-bandwidth memory | |
| CN112219276A (en) | Chip and chip packaging method | |
| TW202201567A (en) | Split substrate interposer | |
| KR20130077627A (en) | Semicondcutor apparatus and method of manufacturing the same | |
| CN110828430A (en) | Packaging structure and preparation method thereof | |
| TWI773400B (en) | Semiconductor device and manufacturing method thereof | |
| US20230361048A1 (en) | Semiconductor package and method of fabricating semiconductor package | |
| KR102457349B1 (en) | Semiconductor packages and methods of manufacturing the same | |
| CN210516718U (en) | Packaging structure | |
| US20240120317A1 (en) | Semiconductor device including vertically interconnected semiconductor dies | |
| US20240063193A1 (en) | Semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20210112 |