CN112214435A - Method and apparatus for data encoding and decoding using standardized data storage and retrieval protocols - Google Patents
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Abstract
The invention discloses a device and a method for coding and decoding data by using a standardized data storage and retrieval protocol, belonging to the technical field of digital data storage. An apparatus and method of data encoding and decoding of the present invention using a standardized data storage and retrieval protocol a computer system, a host processor, a main memory, an I/O device, a user interface, a network interface, a data bus, a controller memory, a host interface, an (input/output) buffer, a programmable circuit, a mass storage, a bus; the main processor is coupled with the network interface to provide a network, the main processor is coupled with the I/O equipment of the main processor through a data bus, the main processor is also coupled with the I/O equipment through the data bus, and the user interface is coupled with the main processor through the data bus. The invention has the advantages that: enabling the host processor to delegate heavy encoding or decoding to the I/O device, freeing up host processor resources for other tasks.
Description
Technical Field
The present invention relates to the field of digital data storage, and more particularly, to a method and apparatus for data encoding and decoding using a standardized data storage and retrieval protocol.
Background
Commercial mass data storage has become an important component of modern economies. Thousands of companies rely on secure, fail-safe data storage to provide services to their customers. Data storage in a business environment typically provides some form of data protection to prevent accidental data loss due to component and equipment failures and man-made or natural disasters. The simplest form of protection is called redundancy. Redundancy involves making multiple copies of the same data and then storing the copies on separate physical drives. If one drive fails, the data can be recovered simply by accessing the other drive. This is obviously expensive in terms of physical storage requirements.
More advanced recovery systems use Redundant Arrays of Independent Disks (RAID). RAID systems typically utilize erasure coding to mitigate unexpected loss of data. Erasure coding divides a data block into n equal-sized segments and adds m parity segments. Thus, a RAID system may store n + m segments and may be resistant to failures of up to m segment failures.
Erasure coding using coding techniques such as reed-solomon codes requires significant computational resources from the host CPU. Thus, encoding data prior to storage may keep computing resources available for other computations away from the host. The result is that the processing speed of other applications becomes slower. It is desirable to provide redundancy in a data storage system without tying up the computational resources of the host CPU.
Disclosure of Invention
1. Technical problem to be solved by the invention
It is an object of the present invention to provide a method and apparatus for encoding and decoding data using a standardized data storage and retrieval protocol, and in particular, a method and apparatus for encoding or decoding large amounts of data by an I/O device coupled to a host processor and a host memory through a high speed data bus. The I/O device performs encoding or decoding of data stored in the (input/output) buffer in accordance with commands issued by the host processor using a standardized data storage and retrieval protocol. This architecture enables the host processor to delegate heavy encoding or decoding to the I/O device, freeing up host processor resources for other tasks. The method is applicable to a horizontally-extended architecture where data may be encoded or decoded in parallel by a single I/O device or multiple I/O devices, each coupled to a host processor through a high-speed data bus.
2. Technical scheme
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
an apparatus and method of data encoding and decoding using a standardized data storage and retrieval protocol of the present invention is characterized by comprising: a computer system, a main processor, a main memory, an I/O device, a user interface, a network interface, a data bus, a controller; a controller memory; a host interface, an (input/output) buffer, a programmable circuit, a mass storage, a bus; the main processor is coupled with the network interface to provide a network, the main processor is coupled with the I/O device of the main memory through a data bus, the main memory is also coupled with the I/O device through the data bus, the main processor is used for generating an encoded command and storing the encoded command into a submission queue, and the encoded command comprises a command modification version defined by a standardized data storage and retrieval protocol; the main memory is used for storing executable commands of the main processor; the user interface is coupled to the main processor via a data bus.
Preferably, the data bus comprises a PCle bus and the standardized data storage and retrieval protocol comprises an NVMe protocol.
Preferably, the I/O device includes a controller configured to retrieve an encoded command from a submission queue according to a standardized data and retrieval protocol, to cause data to be encoded according to the encoding algorithm, and to provide a completion queue entry into the completion queue upon completion of the encoding algorithm; the controller memory coupled with the controller is used for storing an encoding algorithm for encoding data and storing a submission queue and a completion queue; wherein the controller memory further stores a coding algorithm index for associating one or more coding algorithms stored in the controller memory with one or more coding algorithm index values, respectively; wherein the controller is configured to encode the data according to the first encoding algorithm index value specified by the encode command using a first encoding algorithm in the encoding algorithm index.
Preferably, the I/O device comprises an (input/output) buffer coupled to the controller, the controller being configured to encode data by retrieving one or more data blocks from an input buffer at an input buffer address specified by the encode command.
Preferably, the I/O device includes programmable circuitry for encoding data according to an encoding algorithm, the programmable circuitry programmed by the controller in response to the controller retrieving management commands from the management submission queue according to a data storage and retrieval protocol.
Preferably, the programmable circuit is an embedded FPGA.
Preferably, the I/O device includes a mass storage device coupled to the controller by a number of data lines and control lines. Mass storage includes one or more non-transitory information storage devices, such as RAM memory, flash memory, SD memory, XD memory, or other types of electronic, optical, or mechanical storage devices, for storing encoded or decoded data.
Preferably, the bus comprises a PCle bus and the standardized data storage and retrieval protocol comprises the NVMe protocol, wherein the first encoding algorithm index value is provided by the host in a namespace ID field defined by one of the vendor specific commands.
Preferably, the method performed by the I/O device for encoding data includes: generating, by the host processor, an encoded command comprising a modified version of the vendor-specific command defined by the NVMe data storage and retrieval. The main processor stores the coding command in a submission queue; retrieving, by a controller in an I/O device coupled to a primary processor through a data bus, an encoded command from a commit queue according to an NVMe data storage and retrieval protocol; the controller retrieves data from an (input/output) buffer coupled to the controller at an (input/output) buffer address identified by a modified version of the vendor-specific command; encoding the data block according to the encoding command to generate encoded data, wherein encoding the data comprises: acquiring a coding algorithm index value from a coding command; retrieving a first encoding algorithm coupled to a controller memory associated with the encoding algorithm index value; encoding the data block using a first encoding algorithm; and storing the data encoding result in a completion queue by the controller.
Preferably, the encoding algorithm index value is retrieved from a namespace ID field defined by the vendor specific command as a field identifying an area in the controller memory for storing data.
Preferably, the method of encoding and decoding data using a standardized data storage and retrieval protocol, wherein encoding the data comprises: providing the data to programmable circuitry in the I/O device, the programmable circuitry programmed by the controller in response to the controller retrieving a management command from a management submission queue stored therein, in compliance with the NVMe data storage and retrieval protocol.
3. Advantageous effects
Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:
(1) a method and apparatus for encoding and decoding data using a standardized data storage and retrieval protocol, and in particular, a method and apparatus for encoding or decoding large amounts of data by an I/O device coupled to a host processor and a main memory through a high speed data bus. The I/O device performs encoding or decoding of data stored in the (input/output) buffer in accordance with commands issued by the host processor using a standardized data storage and retrieval protocol. This architecture enables the host processor to delegate heavy encoding or decoding to the I/O device, freeing up host processor resources for other tasks.
(2) A method and apparatus for data encoding and decoding using a standardized data storage and retrieval protocol, suitable for use in a horizontally-extended architecture, in which data may be encoded or decoded in parallel by a single I/O device or multiple I/O devices, each coupled to a host processor through a high-speed data bus.
Drawings
FIG. 1 is a functional block diagram of a computer system according to the present invention;
FIG. 2 is a functional block diagram of an I/O device;
FIG. 3 is a flow chart of a method performed by a host processor and an I/O device;
the reference numerals in the drawings are explained below:
1. a computer system; 2. a main processor; 3. a main memory; 4. an I/O device; 5. a user interface; 6. a network interface; 7. a data bus; 8. a controller; 9. a controller memory; 10. a host interface; 11. an (input/output) buffer; 12. a programmable circuit; 13. a mass storage; 14. a bus.
Detailed Description
For a further understanding of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings and examples.
FIG. 1 is a functional block diagram of a computer system according to the present invention.
With reference to fig. 1, the computer system comprises a main processor 2, a main memory 3, I/O devices 4, a user interface 5, a network interface 6 and a data bus 7. The main processor 2, main memory 3 and I/O device 4 are electrically coupled via a data bus 7, the I/O device comprising a connector to plug into an expansion port on the motherboard of the computer system 1.
The computer system 1 may include a personal computer or a cloud computing-based server to perform various tasks such as word processing, web browsing, electronic mail, and mass data storage and retrieval. The computer system 1 may include a server coupled to the internet that is specially configured to process data, including data encoding and/or decoding, prior to storing and/or transmitting the data. The I/O device is a dedicated encoding/decoding device and may include a large capacity SSD for storing large capacity (1tb or more) data. The dedicated encoding/decoding device may be preconfigured with one or more encoding or decoding algorithms and related parameters. The coding algorithm index is used to associate a plurality of coding algorithms with respective coding algorithm index values. In this way, the main processor 2 may specify the particular encoding algorithm used by the I/O device 4 without providing the I/O device 4 with the encoding algorithm itself;
the computer system 1 may be used to encode data for transmission by a destination to a remote location or to decode encoded data received via the network interface 6 from a wide area data network such as the internet. To quickly encode or decode large amounts of data, the main processor 2 offloads computationally intensive encoding and decoding activities to the I/O device 4;
the main memory 3 comprises one or more non-transitory information storage devices such as RAM, ROM, EEPROM, UVPROM, flash memory, SD memory, XD memory or other types of electronic, optical or mechanical storage devices. The main memory 3 is used to store processor-executable instructions for the operation of the computer system 1, as well as data for encoding, decoding, encoding algorithm indices, one or more submission queues, one or more completion queues, and one or more management queues;
the data bus 7 includes a high speed command and data interface between the main processor 2 and, for example, the I/O device 4. The data bus 7 conforms to the PCIe standard. PCIe is a high-speed serial computer expansion bus standard intended to replace the old PCI, PCI-x and AGP bus standards. The data bus 7 is configured to allow high speed data transfer, such as data storage and retrieval, between the main processor 2 and the I/O device 4, but may also transfer configuration information, operating instructions and related parameters for processing by the I/O device 4.
FIG. 2 is a functional block diagram of an I/O device.
In connection with fig. 2, the I/O device comprises a controller 8, a controller memory 9, a host interface 10, an (input/output) buffer 11, a programmable circuit 12, a mass storage 13 and a bus 14.
The I/O device 4 comprises a high capacity SSD, such as a 1tb, 16 channel ONFI compatible NAND SSD with an 800MBps NVMe interface. The I/O device 4 performs data storage and retrieval according to the NVMe protocol, and also performs encoding prior to storage and decoding at the time of data retrieval according to one or more modified vendor-specific commands defined by the NVMe protocol;
the controller 8 includes one or more custom ASICs, PGAs, and/or peripheral circuits to perform the functions of the I/O device 4. The controller memory 9 includes one or more non-transitory information storage devices such as RAM, ROM, EEPROM, flash memory, SD memory, XD memory, or other types of electronic, optical, or mechanical storage devices. The controller memory 9 is for storing processor-executable instructions operated by the controller 8, and one or more encoding algorithms in the encoding algorithm index;
the (input/output) buffer 11 comprises one or more data storage devices for providing temporary storage for data waiting to be encoded or decoded or data already encoded/decoded. The (input/output) buffer 11 typically comprises a RAM memory for fast access data;
the mass memory 13 includes one or more non-transitory information storage devices, such as RAM memory, flash memory, SD memory, XD memory, or other types of electronic, optical, or mechanical storage devices, for storing encoded or decoded data. The mass memory 13 is electrically coupled to the controller 8 through a number of data lines and control lines, the mass memory 13 not including a medium for propagating signals.
FIG. 3 is a flow chart of a method performed by a host processor and an I/O device.
Referring to fig. 3, fig. 3 is a flowchart illustrating a data encoding or decoding method performed by the main processor 2 and the I/O device 4. The method is implemented by the main processor 2 and the controller 8 executing processor executable instructions stored in the main memory 3 and the controller memory 9, respectively.
First, the host processor 2 and the controller 8 cooperate to determine initial settings, such as identifying one or more coding algorithms, formulating a coding index, associating one or more coding algorithms with respective coding algorithm index values to determine commit queues, completion queues and memory allocations, and/or allocating physical memory to namespace IDs. One or more encoding algorithm keys may be identified as a one-time event, for example, when the computer system 1 is first powered on. The encoding algorithms are stored in the controller memory 9 or the main memory 3, wherein each encoding algorithm is associated with a respective encoding algorithm index value. The main processor 2 receives data to be encoded, such as large text, image or video files, from the network interface 6 or the user interface 5. Data is stored in an (input/output) buffer 11; subsequently, the main processor 2 generates an encoded command according to the modified vendor-specific command; and writes the encoded command to a commit queue stored by the main memory 3 or the controller memory 9. The commit queue is a circular buffer of fixed slot size that the host processor 2 uses to commit commands for execution by the controller 8. Commands are placed in the commit queue by the host processor 2 and placed in the associated completion queue is completed by the controller 8. Multiple commit queues may use the same completion queue. Commit and completion queues are allocated in the main memory 3 and controller memory 9 by the main processor 2 and controller 8; in response to writing the encoded command to the commit queue, the main processor 2 writes a new tail pointer to a hardware register associated with the commit queue, alerting the controller 8 that a command is available for execution in the commit queue; subsequently, the controller 8 retrieves the encoded command from the commit queue on the data bus 7 according to the NVMe protocol; the controller 8 recognizes and verifies the coded command as a command for coding data by recognizing the operation code stored in the controller memory 9; next, the controller 8 retrieves and verifies the encoding algorithm index value as the namespace ID stored in the namespace ID field; in response to identifying the coding algorithm index value, the controller 8 retrieves the coding algorithm associated with the coding algorithm index value from the coding algorithm index values stored in the controller memory 9; at this time, the controller 8 recognizes a pointer in the encode command, pointing to the start address of the amount of data to be encoded or decoded in the main memory 3 or the (input/output) buffer 11; subsequently, the controller 8 recognizes some Dwords stored in the main memory 3 or the (input/output) buffer 11 to encode/decode; and retrieves from the main memory 3 or (input/output) buffer 11 the amount of data starting from the address provided by the pointer. The host interface 10 may be used to assist in the transfer of data, and the data may be temporarily stored in an (input/output) buffer 11; the controller 8 then encodes the retrieved data using the encoding algorithm retrieved in the above step. The controller 8 performs the encoding using an encoding algorithm stored in the controller memory 9; when the data is encoded, the controller 8 stores the encoded data in the main memory 3 or in the (input/output) buffer 11; further, the controller 8 writes a completion queue entry to the completion queue stored in the main memory 3 indicating success or failure of the encode/decode command. The NVMe protocol defines the completion queue as a circular buffer with a fixed slot size for issuing the status of completed commands. The completion queue head pointer is updated by the main processor 2 after processing the completion queue entry; the main processor 2 receives a notification that an entry entering the completion queue according to the NVMe protocol exists; the completion queue entry is then evaluated to determine whether the encoded command was successful. The host processor 2 may simultaneously provide additional encode/decode commands to the I/O device 4 using a maximum of 64k of the commit queue and a maximum of 64k of the completion queue to encode or decode a large amount of data. Each queue can store up to 64k commands. Thus, a large amount of data can be encoded/decoded without consuming excessive host processor resources; finally the main processor 2 may provide the encoded/decoded data from the main memory 3 or the (input/output) buffer 11 to a remote location via the wide area network via the network interface 6.
The present invention and its embodiments have been described above schematically, without limitation, and what is shown in the drawings is only one of the embodiments of the present invention, and the actual structure is not limited thereto. Therefore, if the person skilled in the art receives the teaching, without departing from the spirit of the invention, the person skilled in the art shall not inventively design the similar structural modes and embodiments to the technical solution, but shall fall within the scope of the invention.
Claims (11)
1. An apparatus and method for data encoding and decoding using a standardized data storage and retrieval protocol, comprising: the system comprises a computer system (1), a main processor (2), a main memory (3), I/O equipment (4), a user interface (5), a network interface (6), a data bus (7) and a controller (8); a controller memory (9); a host interface (10), an (input/output) buffer (11), a programmable circuit (12), a mass storage (13), and a bus (14); said host processor (2) coupled to a network interface (6) to provide a network, the host processor (2) coupled to an I/O device (4) of the host memory (3) via a data bus (7), the host memory (3) coupled to the I/O device (4) via the data bus (7), the host processor (2) configured to generate encoded commands and store the encoded commands in a submission queue, said encoded commands comprising a modified version of the commands defined by a standardized data storage and retrieval protocol; the main memory (3) is used for storing executable commands of the main processor (2); the user interface (5) is coupled to the main processor (2) via a data bus (7).
2. An apparatus and method for data encoding and decoding using a standardized data storage and retrieval protocol as defined in claim 1 wherein: the data bus (7) comprises a PCle bus and the standardized data storage and retrieval protocol comprises an NVMe protocol.
3. An apparatus and method for data encoding and decoding using a standardized data storage and retrieval protocol as defined in claim 1 wherein: the I/O device (4) includes a controller (8) configured to retrieve an encoded command from a submission queue according to a standardized data and retrieval protocol, to cause data to be encoded according to the encoding algorithm, and to provide a completion queue entry into the completion queue upon completion of the encoding algorithm; the controller memory (9) coupled with the controller (8) is used for storing an encoding algorithm for encoding data and storing a submission queue and a completion queue; wherein the controller memory (9) further stores a coding algorithm index for associating one or more coding algorithms stored in the controller memory (9) with one or more coding algorithm index values, respectively; wherein the controller (8) is configured to encode the data according to a first encoding algorithm index value specified by the encoding command using a first encoding algorithm in the encoding algorithm index.
4. An apparatus and method for data encoding and decoding using a standardized data storage and retrieval protocol as defined in claim 1 wherein: the I/O device (4) comprises an (input/output) buffer (11) coupled to the controller (8), the controller (8) being configured to encode data by retrieving one or more data blocks from the input buffer (11) at an input buffer address specified by the encode command.
5. An apparatus and method for data encoding and decoding using a standardized data storage and retrieval protocol as defined in claim 1 wherein: the I/O device (4) includes programmable circuitry (12) for encoding data according to an encoding algorithm, the programmable circuitry (12) being programmed by the controller (8) to retrieve management commands from the management submission queue according to a data storage and retrieval protocol.
6. An apparatus and method for data encoding and decoding using a standardized data storage and retrieval protocol as defined in claim 5 wherein: the programmable circuit (12) is an embedded FPGA.
7. An apparatus and method for data encoding and decoding using a standardized data storage and retrieval protocol as defined in claim 1 wherein: the I/O device (4) comprises a mass storage (13), the mass storage (13) being coupled to the controller (8) via a number of data lines and control lines, the mass storage (13) comprising one or more non-transitory information storage devices, such as RAM memory, flash memory, SD memory, XD memory or other types of electronic, optical or mechanical storage devices, for storing encoded or decoded data.
8. An apparatus and method for data encoding and decoding using a standardized data storage and retrieval protocol as defined in claim 1 wherein: the bus (14) comprises a PCle bus and the standardized data storage and retrieval protocol comprises an NVMe protocol wherein the first encoding algorithm index value is provided by the host in a namespace ID field defined by one vendor specific command.
9. An apparatus and method for data encoding and decoding using a standardized data storage and retrieval protocol as defined in claim 1 wherein: the method performed by an I/O device (4) for encoding data comprises: generating, by the host processor (2), an encoded command comprising a modified version of the vendor-specific command defined by the NVMe data storage and retrieval. The main processor (2) stores the coded command in a submission queue; retrieving, by a controller (8) in an I/O device (4) coupled to a host processor (2) through a data bus (7), an encoded command from a submission queue according to an NVMe data storage and retrieval protocol; the controller (8) retrieving data from an (input/output) buffer (11) coupled to the controller (8) at an (input/output) buffer (11) address identified by the modified version of the vendor specific command; encoding the data block according to the encoding command to generate encoded data, wherein encoding the data comprises: acquiring a coding algorithm index value from a coding command; retrieving a first encoding algorithm from a controller memory (9) coupled to the associated encoding algorithm index value; encoding the data block using a first encoding algorithm; and the data encoding result is stored in the completion queue by the controller (8).
10. An apparatus and method for data encoding and decoding using a standardized data storage and retrieval protocol as defined in claim 9 wherein: the encoding algorithm index value is retrieved from a namespace ID field defined by the vendor specific command as a field identifying a region in the controller memory (9) for storing data.
11. A method of encoding and decoding data using a standardized data storage and retrieval protocol according to claims 9-10, characterized in that: encoding the data comprises: providing the data to a programmable circuit (12) in the I/O device (4), the programmable circuit (12) being programmed by the controller (8) in response to retrieving a management command from a management commit queue stored therein.
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