CN112203314A

CN112203314A - IP core-based method for adapting and testing IQ data of CPRI interface

Info

Publication number: CN112203314A
Application number: CN202010914323.7A
Authority: CN
Inventors: 甘浩; 曹建业; 吴思谦; 钟俊龙
Original assignee: Guangdong Communications and Networks Institute
Current assignee: Guangdong Communications and Networks Institute
Priority date: 2020-09-02
Filing date: 2020-09-02
Publication date: 2021-01-08

Abstract

The invention discloses a CPRI interface IQ data adaptation and test method based on an IP core, which comprises the following steps: after the register is switched into an application mode, sending user data to a first IQ data channel, sending the user data to a first FIFO memory, and caching according to IQ arrangement rules; after receiving a plurality of periods of basic frame identification of an IP core sent after a system is started, sending user data cached by a first FIFO memory to the IP core of the CPRI; extracting IQ data in the user data according to an IQ arrangement rule, caching the IQ data in the second FIFO memory, and sending the IQ data to a second IQ data channel; and after checking the IQ data, outputting a corresponding checking result to a user to complete the adaptation of the IQ data. The invention can smoothly switch the data to the user clock domain provided by the CPRI IP core under any system clock from the viewpoint of the system clock domain architecture, meets the time sequence requirement of the IQ data interface of the CPRI IP core, and increases the flexibility and the universality of the design of the CPRI related module.

Description

IP core-based method for adapting and testing IQ data of CPRI interface

Technical Field

The invention relates to the technical field of data processing, in particular to a CPRI interface IQ data adaptation and test method based on an IP core.

Background

The common public radio interface CPRI is one of the main interface specifications between the radio equipment control center REC and the radio equipment RE in the radio base station, and this specification flexibly and effectively divides the radio base station into products and independently develops the radio equipment control center and radio equipment technology, and this specification includes the essential elements for the transmission, communication and control and other flows, specifically, the user plane data, control plane data, management plane transmission mechanism and synchronization plane mechanism.

Nowadays, after years of development, the CPRI protocol is more mature in application after being upgraded for multiple versions, and some FPGA manufacturers make the protocol into an IP core form for the convenience of users, where the most critical of the interfaces reserved for users by the CPRI IP core of the Xilinx manufacturer is an IQ data interface, which is mainly used for transmitting user data between a radio equipment control center REC and a radio equipment RE.

However, in the course of research and practice on the prior art, the inventors of the present invention found that the prior art generally develops research around specific application methods and cases of CPRI, lacks design versatility from the viewpoint of system clock domain architecture, and cannot smoothly switch data to the user clock domain provided by the IP core of CPRI under any system clock to meet the timing requirements of the IQ data interface of the IP core of CPRI. In addition, the CPRI interface has a characteristic of a high data rate, and the CPRI interface must be required to have a high stability requirement, so that the stability is used as an important index for judging the quality of the interface. However, a large number of tests are required to ensure the stability of the interface, and the prior art currently lacks research on a CPRI interface test method. Therefore, there is a need for an IQ data adaptation and testing method for CPRI interface based on IP core that can overcome the above technical drawbacks.

Disclosure of Invention

The technical problem to be solved by the embodiments of the present invention is to provide a CPRI interface IQ data adaptation and test method based on an IP core, which can adapt and test an IQ data interface of a CPRI IP core.

In order to solve the above problem, an embodiment of the present invention provides an IP core-based method for adapting IQ data of a CPRI interface, which at least includes the following steps:

defining a configuration register through macro parameters, switching modes, and sending user data to a corresponding first IQ data channel after switching to an application mode;

after receiving the user data through the first IQ data channel, sending the user data to a first FIFO memory, and caching according to IQ arrangement rules;

after receiving a plurality of periods of basic frame identification of the IP core sent after the system is started, sending the user data cached by the first FIFO memory to the IP core of the CPRI;

extracting IQ data in the user data according to the IQ arrangement rule through a data interface of the IP core of the CPRI, and caching the IQ data in the second FIFO memory;

sending IQ data in the user data to a second IQ data channel corresponding to an application mode through the second FIFO memory;

checking the IQ data in the user data received by the second IQ data channel, and outputting a corresponding checking result to the user after the checking is finished, thereby finishing the adaptation of the IQ data.

Further, the IQ alignment rule specifically includes:

identifying that the current CPRI interface needs to transmit data of one or more antennas;

when the CPRI interface is identified to need to transmit the data of one antenna, setting all AXC containers stored in each basic frame to be sequentially arranged in sequence;

and when the CPRI interface is identified to need to transmit data of a plurality of antennas, setting all AXC containers stored in each basic frame to be alternately arranged according to the number of the antennas.

Further, the IQ alignment rule further includes:

reserving unused AXC Container locations present per said basic frame.

Further, before the sending the user data buffered by the first FIFO memory to the IP core of the CPRI, the method further includes:

and sending the user data cached by the first FIFO memory to the IP core of the CPRI only when the result of the AND of the read ready signal of the first FIFO memory and the enable phase of the external read first FIFO memory is valid.

Further, before the extracting, according to the IQ arrangement rule, IQ data in the user data through the data interface of the IP core of the CPRI, and buffering the IQ data in the second FIFO memory, the method further includes:

and when the second FIFO memory judges that the data read signal is valid, extracting IQ data in the user data.

Further, the checking the IQ data in the user data received by the second IQ data channel further includes:

carrying out synchronous detection and synchronous processing on the received IQ data and a local signal; wherein the synchronization process includes synchronization of an accumulated number and synchronization of a pseudo random number.

An embodiment of the present invention further provides a CPRI interface IQ data testing method based on an IP core, which at least includes the following steps:

defining a configuration register through macro parameters, switching modes, and sending test data to a corresponding first IQ data channel after switching to a test mode;

after receiving the test data through the first IQ data channel, sending the test data to a first FIFO memory, and caching according to IQ arrangement rules;

after receiving a plurality of periods of basic frame identification of the IP core sent after the system is started, sending the test data cached by the first FIFO memory to the IP core of the CPRI;

extracting IQ data in the test data according to the IQ arrangement rule through a data interface of the IP core of the CPRI, and caching the IQ data in the second FIFO memory;

sending the IQ data in the test data to a second IQ data channel corresponding to an application mode through the second FIFO memory;

and sending the IQ data in the test data received by the second IQ data channel to a checking module for checking, and outputting a corresponding checking result to a user after the checking is finished so as to finish the test of the IQ data.

Further, the test data is specifically corresponding test data generated when the current system clock is not the user clock provided by the IP core of the CPRI.

Further, the content of the test data includes one or both of an accumulated number and a pseudo random number.

Further, the content of the test data also comprises a flag bit indicating that the data is valid.

The embodiment of the invention has the following beneficial effects:

the embodiment of the invention provides a CPRI interface IQ data adaptation and test method based on an IP core, wherein the adaptation method comprises the following steps: defining a configuration register through macro parameters, switching modes, and sending user data to a corresponding first IQ data channel after switching to an application mode; after receiving the user data through the first IQ data channel, sending the user data to a first FIFO memory, and caching according to IQ arrangement rules; after receiving a plurality of periods of basic frame identification of the IP core sent after the system is started, sending the user data cached by the first FIFO memory to the IP core of the CPRI; extracting IQ data in the user data according to the IQ arrangement rule through a data interface of the IP core of the CPRI, and caching the IQ data in the second FIFO memory; sending IQ data in the user data to a second IQ data channel corresponding to an application mode through the second FIFO memory; checking the IQ data in the user data received by the second IQ data channel, and outputting a corresponding checking result to the user after the checking is finished, thereby finishing the adaptation of the IQ data.

Compared with the prior art, the invention provides two test data generation and verification methods based on the IQ data adaptation and test method of the CPRI interface based on the IP core, wherein the two methods both support long-time on-hook verification to verify the channel stability, and play a key role in troubleshooting problems in a large-scale system. The embodiment can flexibly support the adaptation of the applications with different antenna numbers through an adaptation mode, can support various application scenes under the condition of not changing codes too much, and simultaneously solves the problem of cross-clock domain adaptation under the condition that a system clock and a CPRI user clock are not the same clock, so that a user can use the own system clock without depending on the user clock of the CPRI IP core when using the CPRI IP core.

Drawings

Fig. 1 is a schematic flowchart of a CPRI interface IQ data adaptation method based on an IP core according to a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of an arrangement manner of antenna data in a basic frame according to a first embodiment of the present invention;

fig. 3 is a schematic structural diagram of an arrangement manner of two-antenna data in a basic frame according to a first embodiment of the present invention;

fig. 4 is a schematic structural diagram of an arrangement manner of four-antenna data in a basic frame according to a first embodiment of the present invention;

fig. 5 is a schematic flowchart of a method for testing CPRI interface IQ data based on an IP core according to a second embodiment of the present invention;

fig. 6 is a block diagram of a structure of an IQ data adaptation and testing method for a CPRI interface IP core according to a third embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

First, the application scenarios that can be provided by the present invention, such as the adaptation and test of CPRI interface IQ data based on IP core, are introduced.

Before describing the embodiments of the present invention, the related terms referred to in the embodiments will be explained. The Common Public Radio Interface (CPRI) is applied to a communication Interface between a device control center (REC) and a wireless device (RE) in the field of wireless communication. The FPGA usually exists in the form of an IP core, the IP core comprises a bottom layer serdes module, a CPRI protocol module based on the serdes module and other clock and reset modules, an FPGA manufacturer encapsulates the modules, an interface reserved for a user is provided with an IQ data interface and a control interface, and the control interface comprises an Ethernet interface, an HDLC interface, a manufacturer specified interface and the like. Because the serdes part comprises a high-speed serial-parallel-serial conversion interface, a CPRI IP core usually gives a user clock, and a user sends data on different interfaces into the IP core according to a required specific time sequence by the clock frequency, so that the data volume entering the IP core on a path is the same as the data volume coming out of the IP core, and the data loss or the repeated occurrence is prevented. In a larger system, the clock structure may be more complex, the system clock is often not the user clock given by the CPRI IP core, at this time, processing across clock domains is required, and the user data is adapted to the time sequence required by the IP core.

The CPRI interface is a high-speed interface, the supported rates in the existing protocol specification are 614.44Mb/s, 1228.8Mb/s, 2457.6Mb/s, 3072.0Mb/s, 4915.2Mb/s, 6144.0Mb/s, 8110.08Mb/s, 9830.4Mb/s, 10137.6Mb/s, 12165.12Mb/s and 24330.24Mb/s, and a large amount of tests are needed in the engineering realization to ensure the stability of the interface. In addition, if a problem occurs in the system joint debugging process, whether the problem appears on the interface or not can be eliminated through the test module.

The first embodiment of the present invention:

please refer to fig. 1-4.

As shown in fig. 1, the present embodiment provides a CPRI interface IQ data adaptation method based on an IP core, which at least includes the following steps:

s101, defining a configuration register through macro parameters, carrying out mode switching, and sending user data to a corresponding first IQ data channel after switching to an application mode.

Specifically, for step S101, since the two paths of data need to multiplex the IQ data channel of the CPRI, the mode is switched through the macro parameter definition configuration register, and after the mode is switched to the application mode, the user data is selected in the application mode and sent to the back-stage module.

S102, after receiving the user data through the first IQ data channel, sending the user data to a first FIFO memory, and caching according to IQ arrangement rules.

Specifically, in step S102, the data from step S101 is received and stored in the FIFO for buffering. The IQ data interface of CPRI transmits data in the form of basic frames, the rate of the basic frames is 3.84MHz, each basic frame is divided into 16 words, word0 is used for transmitting control information, word1-word15 is used for transmitting IQ data, the bit width of each word varies with the rate, and can be 8 bits, 16 bits, 32 bits and the like, and the maximum is 384 bits. After the CPRI rate is determined, the bit width of each word is determined, and the amount of data transmitted in each basic frame is also determined.

In a preferred embodiment, the IQ alignment rule specifically includes:

In a preferred embodiment, the IQ alignment rule further includes:

reserving unused AXC Container locations present per said basic frame.

Specifically, after the system is started, the basic frame identifier of the IP core will come regardless of whether data transmission is available or not. A CPRI interface may need to transmit data of one or more antennas, a position for storing a pair of IQ data of one antenna is referred to as an AxC Container, and data of different antennas need to be arranged according to a certain rule, as shown in fig. 2-4, when transmitting IQ data of 1 antenna, all AxC containers are sequentially arranged, and when all AxC containers of a basic frame are not used, the remaining positions are reserved; when transmitting multi-antenna IQ data, the AxC containers of each antenna are arranged alternately, and similarly, when not all AxC containers of one basic frame are used, the remaining positions are reserved.

S103, after receiving a plurality of periods of basic frame identification of the IP core sent after the system is started, sending the user data cached by the first FIFO memory to the IP core of the CPRI.

In a preferred embodiment, before the sending the user data buffered by the first FIFO memory to the IP core of the CPRI, the method further includes:

Specifically, for step S103, since the basic frame id of each IP core comes after the system is started, IQ data needs to be transmitted several cycles after the basic frame id, where several values along with different line rates are different, and for a 10G line rate, IQ data is transmitted in 4 cycles after the basic frame is represented. Under normal conditions, the data buffered in the FIFO should be read for transmission, however, sometimes IQ data does not arrive, if the FIFO is read, the action of reading the FIFO is required to fail to read the data, which requires that the read ready signal of the FIFO is anded with the enable of the external read FIFO, specifically, two signal lines are anded, and then the read ready signal is sent to the read enable port of the actual FIFO, when the read ready of the FIFO is invalid, the read enable of the actual FIFO is also invalid, at this time, the actual data cannot be read even if the read enable is valid, and for the adaptation module of the IQ data channel, the balance of input and output data is ensured.

And S104, extracting IQ data in the user data according to the IQ arrangement rule through a data interface of the IP core of the CPRI, and caching the IQ data in the second FIFO memory.

In a preferred embodiment, before the extracting, by the data interface of the IP core of the CPRI, the IQ data in the user data according to the IQ arrangement rule and buffering the extracted IQ data in the second FIFO memory, the method further includes:

Specifically, for step S104, IQ data from the CPRI is received, extracted according to the IQ arrangement rule described in step S102, and stored in the FIFO for buffering. At the other end of the FIFO, no specific timing requirement exists, and only the fact that whether the data read ready is effective is needed to be judged, if the data read ready is high, the ready signal is effective, and if the data read ready is not high, the data read ready signal is invalid. Once valid, the data is read out, if the IQ data of multiple antennas are transmitted in the same basic frame, the data of different antennas are separated, and corresponding valid signals are generated at the same time and sent to the next module together with the data.

S105, sending the IQ data in the user data to a second IQ data channel corresponding to an application mode through the second FIFO memory.

Specifically, in step S105, if the current application mode is the application mode, the data is sent to the corresponding second IQ data channel for further processing, and the configuration is performed through the register during implementation.

S106, checking the IQ data in the user data received by the second IQ data channel, outputting a corresponding checking result to the user after the checking is finished, and finishing the adaptation of the IQ data.

In a preferred embodiment, the checking IQ data in the user data received by the second IQ data channel further includes:

Specifically, in step S106, the received IQ data is checked and the check result is output for the user to read. The checking process is to judge whether the received data is the same as the locally generated data, if so, the data is considered to be correctly received, otherwise, the data is considered to be incorrectly received, and the link has problems. The key to correct verification, in addition to data consistency, requires that the phases be identical, i.e., that the received data be synchronized with locally generated data. In order to synchronize the received signal with the local signal, a synchronization process is required.

For synchronization of the accumulated number, a register is required to be manually intervened to configure a synchronization enabling signal, the signal received at the current moment is assigned to a local accumulated signal at the moment of receiving the synchronization enabling signal, and the local accumulated signal is accumulated on the basis; when receiving the synchronization enabling signal, need clear away the statistic to clear away the influence of statistic before not synchronizing, after the synchronization, the user can look over the statistic, if the statistic is zero, then explain correctly receiving, if the statistic is not zero, have two kinds of possibilities, firstly the data of sending have not been received, another is that the transmission process has the mistake, needs specific analysis.

For the synchronization of the pseudo random number, a synchronization enabling signal is not required to be configured through human intervention, the pseudo random code has periodicity, a shift register generating the pseudo random code has an initial value, as long as the received signal is equal to the initial value, the synchronization can be considered to be started from the moment, if the statistical value does not change any more, the correct receiving is indicated, otherwise, the data is considered to be in error in the transmission process. It should be noted that the period of the pseudo random code is proportional to the length of the generator polynomial, and the period of the 32-bit generator polynomial can reach 13s at 300MHz, so it is meaningful to wait for a period of time before looking at the statistical value.

The method for adapting the IQ data of the CPRI interface based on the IP core provided by the embodiment comprises the following steps: defining a configuration register through macro parameters, switching modes, and sending user data to a corresponding first IQ data channel after switching to an application mode; after receiving the user data through the first IQ data channel, sending the user data to a first FIFO memory, and caching according to IQ arrangement rules; after receiving a plurality of periods of basic frame identification of the IP core sent after the system is started, sending the user data cached by the first FIFO memory to the IP core of the CPRI; extracting IQ data in the user data according to the IQ arrangement rule through a data interface of the IP core of the CPRI, and caching the IQ data in the second FIFO memory; sending IQ data in the user data to a second IQ data channel corresponding to an application mode through the second FIFO memory; checking the IQ data in the user data received by the second IQ data channel, and outputting a corresponding checking result to the user after the checking is finished, thereby finishing the adaptation of the IQ data.

In the embodiment, from the perspective of a system clock domain architecture, data can be smoothly switched to a user clock domain provided by a CPRI IP core under any system clock, so that the time sequence requirement of an IQ data interface of the CPRI IP core is met.

Second embodiment of the invention:

please refer to fig. 5.

As shown in fig. 5, the present embodiment provides a method for testing CPRI interface IQ data based on an IP core, which at least includes the following steps:

s201, defining a configuration register through macro parameters, switching modes, and sending test data to a corresponding first IQ data channel after switching to a test mode.

In a preferred embodiment, the test data is specifically corresponding test data generated when the current system clock is not the user clock provided by the IP core of the CPRI.

In a preferred embodiment, the content of the test data comprises one or both of an accumulated number and a pseudo random number.

In a preferred embodiment, the content of the test data further comprises a flag bit indicating that the data is valid.

Specifically, for step S201, test data is generated, the test data is generated in a system clock domain, and a scenario that a system clock is not a user clock given by the CPRI IP core is simulated. For the simplicity and randomness of the test, two test data generation modes of indicating data validity by a valid signal, indicating data start by sop and indicating data end by eop are supported, wherein the contents of the two test data are one of an accumulated number and the other one of a pseudo-random number, only one of the two modes can be selected at the same time, and when the engineering is realized, different data generation modes can be selected by defining a configuration register through a macro parameter. Since the CPRI core transmits data in units of basic frames, the test module is required to generate data in an amount equal to the amount of data transmitted by the CPRI in the same time. In the engineering realization, a macro parameter is adopted to define an effective signal as a data effective zone bit; the signal is output along with the test data as a source of the test data. The generated test data is used in a test scene, the data is the data of a user in actual use, the two paths of data need to multiplex an IQ data channel of CPRI, the mode switching is carried out through a macro parameter definition configuration register, and the test data is selected and sent to a back-stage module in a test mode.

S202, after receiving the test data through the first IQ data channel, sending the test data to a first FIFO memory, and caching according to IQ arrangement rules.

Specifically, in step S202, the data from step S201 is received and stored in the FIFO for buffering. The IQ data interface of CPRI transmits data in the form of basic frames, the rate of the basic frames is 3.84MHz, each basic frame is divided into 16 words, word0 is used for transmitting control information, word1-word15 is used for transmitting IQ data, the bit width of each word varies with the rate, and can be 8 bits, 16 bits, 32 bits and the like, and the maximum is 384 bits. After the CPRI rate is determined, the bit width of each word is determined, and the amount of data transmitted in each basic frame is also determined.

S203, after receiving a plurality of periods of basic frame identification of the IP core sent after the system is started, sending the test data cached by the first FIFO memory to the IP core of the CPRI.

Specifically, for step S203, since the basic frame id of each IP core comes after the system is started, IQ data needs to be transmitted several cycles after the basic frame id, where several values along with different line rates are different, and for a 10G line rate, IQ data is transmitted in 4 cycles after the basic frame indicates. Under normal conditions, the data buffered in the FIFO should be read for transmission, however, sometimes IQ data does not arrive, if the FIFO is read, the action of reading the FIFO is required to fail to read the data, which requires that the read ready signal of the FIFO is anded with the enable of the external read FIFO, specifically, two signal lines are anded, and then the read ready signal is sent to the read enable port of the actual FIFO, when the read ready of the FIFO is invalid, the read enable of the actual FIFO is also invalid, at this time, the actual data cannot be read even if the read enable is valid, and for the adaptation module of the IQ data channel, the balance of input and output data is ensured.

And S204, extracting IQ data in the test data according to the IQ arrangement rule through a data interface of the IP core of the CPRI, and caching the IQ data in the second FIFO memory.

Specifically, for step S204, the IQ data from the CPRI is received, the IQ data is extracted according to the IQ arrangement rule in step S202, and is stored in the FIFO for buffering. At the other end of the FIFO, no specific timing requirement exists, and only the fact that whether the data read ready is effective is needed to be judged, if the data read ready is high, the ready signal is effective, and if the data read ready is not high, the data read ready signal is invalid. Once valid, the data is read out, if the IQ data of multiple antennas are transmitted in the same basic frame, the data of different antennas are separated, and corresponding valid signals are generated at the same time and sent to the next module together with the data.

S205, sending the IQ data in the test data to a second IQ data channel corresponding to the application mode through the second FIFO memory.

Specifically, in step S205, if the current mode is the test mode, the received data is sent to the check module for checking, and the data is sent to the corresponding second IQ data channel for further processing, and the configuration is performed through the register when the data is implemented.

S206, sending the IQ data in the test data received by the second IQ data channel to a checking module for checking, outputting a corresponding checking result to a user after checking is finished, and finishing the test of the IQ data.

Specifically, in step S206, the received IQ data is checked and the check result is output for the user to read. The checking process is to judge whether the received data is the same as the locally generated data, if so, the data is considered to be correctly received, otherwise, the data is considered to be incorrectly received, and the link has problems. The key to correct verification, in addition to data consistency, requires that the phases be identical, i.e., that the received data be synchronized with locally generated data. In order to synchronize the received signal with the local signal, a synchronization process is required.

The method for testing CPRI interface IQ data based on an IP core according to the present embodiment includes: defining a configuration register through macro parameters, switching modes, and sending test data to a corresponding first IQ data channel after switching to a test mode; after receiving the test data through the first IQ data channel, sending the test data to a first FIFO memory, and caching according to IQ arrangement rules; after receiving a plurality of periods of basic frame identification of the IP core sent after the system is started, sending the test data cached by the first FIFO memory to the IP core of the CPRI; extracting IQ data in the test data according to the IQ arrangement rule through a data interface of the IP core of the CPRI, and caching the IQ data in the second FIFO memory; sending the IQ data in the test data to a second IQ data channel corresponding to an application mode through the second FIFO memory; and sending the IQ data in the test data received by the second IQ data channel to a checking module for checking, and outputting a corresponding checking result to a user after the checking is finished so as to finish the test of the IQ data.

In order to ensure the stability of a link of the CPRI interface, the embodiment provides a method for testing and verifying a large number of CPRI interfaces, a module for automatically testing data generation and data verification is added on the basis of the complete link, testing of the stability of the link can be facilitated by configuring a register, and when data output is wrong, whether the CPRI interface is wrong or not can be eliminated, the difficulty of problem location is greatly reduced, and the flexibility and the stability of design of the CPRI-related modules are improved.

Third embodiment of the invention:

as shown in fig. 6, on the basis of the first embodiment and the second embodiment, the present embodiment describes the adaptation and testing method of the present invention in detail by combining the actual cases.

For convenience of presentation, the CPRI uses a line rate of 10.1376Gb/s, and as known from the CPRI protocol specification, the rate of basic frames is 3.84MHz, and the time length of each basic frame is about 260.42 ns. In the Xilinx CPRI IP core, the IQ data bit width at this rate is 32 bits, and a basic frame has a total of 80 clock cycles, here called user clock, with a clock frequency of 307.2MHz, which can verify that 1/307.2MHz 80 ≈ 260.42 ns. The first 4 of 80 clock cycles are used to transmit the control word and the rest are used to transmit the IQ data. In addition, in order to accurately simulate the scenario of 5G NR communication, referring to the 5G standard, the data amount generated by a signal with 30KHz spacing between subcarriers in one symbol time is simulated, the time of 0 th or 7 th × 2 μ OFDM symbol plus CP in one subframe is 36.2us, the time of other OFDM symbol plus CP is 35.68us, there are 352 data in CP corresponding to 0 th or 7 th × 2 μ OFDM symbol in one subframe, there are 288 data in CP of other OFDM symbol, and all OFDM symbols are 4096 data. The data amount of one OFDM plus CP is 4448 or 4384. Only 32 data of one antenna are transmitted in each basic frame, and the OFDM plus CP data needs 4448/32-139 or 4384/32-137 basic frames to be transmitted respectively. This can be exactly up in time, i.e. 36.2us/260.42 ≈ 139 or 35.68us/260.42 ≈ 137.

After the data generation module is powered on and reset, the frame interruption, the subframe interruption, the time slot interruption and the symbol interruption of the wireless system are counted by a counter of the data generation module. According to the symbol interruption, the accumulated number of IQ data of two antennas is generated in each symbol time interval, the bit width of an accumulator is 16 bits, the accumulated value is simultaneously given to IQ values of the two antennas, the data amount is 4448 or 4384 64 bits, wherein 0-15 bits represent I-path data of the antenna 1, 16-31 bits represent Q-path data of the antenna 1, 32-47 bits represent I-path data of the antenna 2, and 48-63 bits represent Q-path data of the antenna 2. Therefore, the I path and the Q path of the two antennas are the same numerical value, and therefore the verification of the receiving end is facilitated. The data of one symbol is continuously output along with the data valid signal, and is output according to a system clock frequency which is 368.64 MHz.

A data selection enabling signal is defined in a data path selection module of a sending end, the value of the enabling signal is changed through a configuration register, test data is selected to be sent to a data sending adaptation module when the configuration is 1, and user data is selected to be sent to the data sending adaptation module when the configuration is 0. The default is 0, so when performing the CPRI interface test, the enable signal needs to be configured to be 1.

The data transmission adaptation module receives two antenna data with 64-bit width, splits the two antenna data into respective 32-bit IQ data after the two antenna data come in, and respectively caches the data. In order to completely buffer the data of 1 OFDM symbol, the buffer depth of two antennas needs to be carefully designed. It is known that the input data comes in continuously at 368.64MHz rate, and the maximum amount of time required for calculation of the OFDM symbol data 4448 is 1/368.64MHz 4448 ≈ 12.07 us. Under the speed of 10.1376Gb/s, the user clock given by the IP core is 307.2MHz, as long as the data in the buffer memory is detected, the read operation is started immediately, and the data in the buffer memory is read out for sending. On this premise, it can be considered that the read cache operation is started immediately while the data is written into the cache, and how much data is read during the period of writing into the cache is calculated, and the cache space required by the data which is not read is the requirement of the maximum cache depth. As it is known that one basic frame can transmit 32 IQ data of one antenna, 12.07us is roughly calculated as 47 basic frames, so 4448 data are buffered in the period of time, 47 × 32 — 1504 data are taken away, and 2944 data are left to be buffered. Since the depth of the FIFO can only be 2^ n, the minimum depth to enable the next 2944 data to be cached and meet the FIFO depth setting requirement is 4096. Thus, the bit width and depth of the FIFO for caching the data of the two antennas in the module are calculated, namely the bit width is 32bit and the depth is 4096.

The CPRI IP core has 80 periods at the rate of 10.1376Gb/s, and the bit width of one IQ data is exactly one period, because one period can transmit exactly 32 bits. The first 4 cycles are used for transmitting control words and the remaining 76 cycles are used for transmitting IQ data. One antenna needs to transmit 32 IQ data in one basic frame, and takes 32 cycles, and two antennas take 64 cycles, so that one clock cycle of the CPRI IP core can be considered to be exactly one AxC Container. The IQ data transmitted by the antenna 1 is located at AxC Container 1, denoted as AxC1, and the IQ data transmitted by the antenna 2 is located at AxC Container 2, denoted as AxC2, and the two antennas are transmitted in the format of AxC1, AxC2, AxC1, AxC2, AxC1 and AxC2 … … on the link of the CPRI IQ data interface until both antennas complete the transmission of 32 IQ data, and the remaining positions are reserved, and the reserved part can transmit a 0 value in the transmission process, as shown in fig. 3.

In a scene of one antenna, each basic frame only needs to send IQ data of one antenna, and arrangement of data of different antennas in the basic frame is not required to be considered. Each basic frame finishes transmitting 32 IQ data, and the rest places are reserved for transmitting 0 values, as shown in fig. 2.

In a two-antenna scenario, IQ data of each antenna is 32 bits, one CPRI link transmits data of two antennas, which occupies 64 cycles, and if data of four antennas are to be transmitted, it is obvious that one basic frame is not enough to completely transmit all data. In order to support one CPRI channel to transmit data of four antennas, IQ data of each antenna needs to be compressed, and a specific compression algorithm is not within the scope of the present invention. After compression, the IQ data bit width of one antenna is 16 bits, the four antennas are 64 bits in total, a storage frame for two antennas can be reserved, only the data of the antenna 1 and the antenna 2 are merged and cached in the memory 1, and the data of the antenna 3 and the antenna 4 are merged and cached in the memory 2. Therefore, the scenes of the two antennas and the four antennas are completely consistent in the adaptive operation, and only data compression operation is needed before data enters the adaptive module, so that the design can ensure the completeness of the functions of the modules and reduce the interoperation among the modules.

At a receiving end, the IP core still outputs IQ data in the form of a CPRI basic frame, the first 4 periods of the CPRI IP core IQ data basic frame bear the information of control words, a user does not need to care about skipping the control information of the periods, and if the IP core IQ data basic frame is an antenna, the IQ data of 32 periods is cached; if the number of the antennas is two or four, 64 periods of data are buffered. The buffer memory is used for crossing clock domains, and as no specific timing requirement is needed at the system clock domain end, once the data in the buffer memory can be read, the data can be read away immediately. The system clock is larger than the user clock of CPRI, so that under the application scene, too large cache is not needed, the requirements can be met by adopting FIFO with 32bit width and 1024 depths, and the cache configuration uses the minimum resource block in the RAM resource of the FPGA block. When the system clock side reads out the buffered data, a data valid signal is accompanied.

A data selection enabling signal is defined in a data path selection module of the receiving end, the value of the data selection enabling signal is changed through a configuration register, data are selectively sent to a verification module for verification when the configuration is 1, and the data are sent to a user when the configuration is 0.

After the data check module receives the data, whether the received data is the same as the local check data or not is compared, and if not, the error number statistic value is accumulated. Since the data generated by the data generation module is 16 bits, a 16-bit register is also used for accumulation in the check module. Comparing the input data with local check data every 16 bits, if the input data is 64 bits, comparing the input data with 0-15 bits, 16-31 bits, 32-47 bits and 48-63 bits in each period for four times, if the input data is inconsistent with the local 16 bits once, judging that the input data is wrong, and adding 1 to the statistical value. Because the mode of checking the accumulated number is used, before starting the statistics, a register is needed to be configured, so that the local check data is locked on the received data. When the synchronization enabling signal is received, the low 16 bits of the received data are assigned to a local check accumulation number, and then every time data comes in, the accumulation number is added with 1, and the coming data are compared. And (4) the statistical result is provided for the user to read, if no error exists, the link is good, and the whole verification process is finished.

The adaptation module provided in the embodiment is convenient and flexible, can support data adaptation of one antenna, two antennas and four antennas with minimum change, accurately calculates the cache bit width and depth required by adaptation from a theoretical angle, and ensures that the data transmission process cannot be lost. The invention adds the module for automatically testing data generation and data verification on the basis of the complete link, can facilitate the test of the stability of the link by configuring the register, and can help to eliminate whether the CPRI interface has a problem or not when the data output has errors, thereby greatly reducing the difficulty of problem positioning.

In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The foregoing is directed to the preferred embodiment of the present invention, and it is understood that various changes and modifications may be made by one skilled in the art without departing from the spirit of the invention, and it is intended that such changes and modifications be considered as within the scope of the invention.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

Claims

1. A CPRI interface IQ data adaptation method based on IP core is characterized by at least comprising the following steps:

2. The IP core-based CPRI interface IQ data adaptation method according to claim 1, wherein the IQ alignment rule specifically is:

3. The IQ data adaptation method for a CPRI interface based on IP core according to claim 1, wherein the IQ permutation rule further comprises:

reserving unused AXC Container locations present per said basic frame.

4. The IP core-based CPRI interface IQ data adaptation method according to claim 1, further comprising, before the sending the user data buffered by the first FIFO memory to the IP core of CPRI:

5. The IP core-based CPRI interface IQ data adaptation method according to claim 1, wherein before the extracting IQ data in the user data according to the IQ ordering rule through the data interface of the IP core of the CPRI and buffering the extracted IQ data in the second FIFO memory, further comprising:

6. The IP core based CPRI interface IQ data adaptation method according to claim 1, wherein the checking IQ data in the user data received by the second IQ data channel further comprises:

7. A CPRI interface IQ data testing method based on IP core is characterized in that it at least includes the following steps:

8. The IP-core based CPRI interface IQ data testing method according to claim 7, characterized in that the test data is specifically corresponding test data generated when a current system clock is simulated not to be a user clock provided by the IP core of the CPRI.

9. The IP core based CPRI interface IQ data testing method according to claim 7, wherein the content of the test data comprises one or both of an accumulated number and a pseudo random number.

10. The IP core based CPRI interface IQ data testing method according to claim 7, wherein the content of the test data further comprises a flag bit indicating data validity.