CN112199173B

CN112199173B - Data processing method for dual-core CPU real-time operating system

Info

Publication number: CN112199173B
Application number: CN202011044892.7A
Authority: CN
Inventors: 邵永杰; 方科; 唐洪军; 谢玲
Original assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Current assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2023-02-28
Anticipated expiration: 2040-09-28
Also published as: CN112199173A

Abstract

The invention discloses a data processing method of a dual-core CPU real-time operating system, and aims to provide a data processing implementation method which is quick in response, simple in driving program and small in transplanting workload. The invention is realized by the following technical scheme: sending an interrupt signal generated by FPGA logic into a real-time bare computer program by using a processing signal processing board card, and storing the real-time logic program on a CPU0 into a DDR0 bare computer memory DDR2 shared memory for memory logic distribution; the interrupt signal is sent to the processor of the CPU0, and the interrupt signal runs by respective programs and is communicated with the cores of the CPU; displaying a non-real-time Linux operating system through an application program, and operating the non-real-time operating system on the CPU1 to form a dual-core CPU processor operating system for simultaneously processing a non-real-time task and a real-time task; CPU0 responds to the real-time hardware environment and exchanges data between the two CPUs in the shared memory range of the two CPUs.

Description

Data processing method for dual-core CPU real-time operating system

Technical Field

The invention relates to an application technology of a dual-core microprocessor in the fields of a real-time operating system, high-speed signal processing, measurement and control, communication and the like in the field of industrial control, in particular to a communication mechanism between two cores in the field of real-time signal processing and a communication method between two cores of a shared memory-based dual-core processor software architecture.

Background

The embedded dual-core processor is an important development direction of the embedded processor at present, has the characteristics of low power consumption, low dominant frequency and high operational performance, and paves a way for the application of the dual-core processor in the embedded field. However, the dual-core processor is not transparent to software, an operating system is required for supporting the dual-core processor, and user codes which are operated in a single-core processor environment before can be applied to the dual-core processor after being transplanted. From the perspective of application software, the application system software requires a real-time operating system to provide forward compatibility so as to reduce the migration cost of the application software, so it requires the operating system to shield the influence of dual-core processor hardware on the application software as much as possible, which is a main reason for the birth of the real-time operating system based on the dual-core processor. With the continuous maturity of embedded technology and the continuous improvement of industrial equipment miniaturization and personalization requirements in the industry, more and more industrial equipment is controlled by adopting embedded system design. People put forward higher requirements on an embedded system in terms of processing speed, processing precision, real-time performance and the like, in a traditional control system, a single-core processor architecture is the mainstream, the response speed of the system is improved by improving the main frequency of a processor, and the system performance can be further improved by using a preemptive real-time operating system, introducing multiple threads, improving a system task scheduling strategy and other software methods. However, with the continuous complexity of the application, the requirement for control accuracy is continuously improved, and the limited system resources become the biggest bottleneck in improving the system performance. In a single-core environment, an interrupt running environment is always in a preemptive mode, data consistency in a running space is achieved for a task, the task is usually guaranteed by interrupt turning, in a dual-core processor environment, two instruction streams of the task and two instruction streams of the interrupt are provided respectively, and therefore the data consistency in a system is threatened, and the single-CPU architecture limitation is overcome. On the basis of a single-core embedded operating system architecture, the prior art provides a dual-core processor embedded operating system architecture based on symmetric communication, so as to solve the problems of communication efficiency and shared memory utilization of heterogeneous dual-core processors. The operating systems of the dual-core processor can be divided into two categories, namely a time-sharing operating system and a real-time operating system according to whether the operating systems have real-time performance. The system resource scheduling in the time-sharing operating system adopts a time slice rotation mode, so that the application program cannot be guaranteed to obtain system resources immediately, cannot be interrupted by other programs before the task is completed, and does not have a real-time characteristic; the real-time operating system has a high-precision timing system, adopts a multi-level interrupt mechanism to schedule different tasks in real time, ensures that high-level tasks can obtain system resources in time, and has real-time characteristics. The communication protocol and the communication interface package are important links for dual-core communication. Through simple data communication, two parties can directly send data, and the default two parties know the meaning of the data and the memory address where the data should be placed. However, as the system becomes more complex, the amount of code increases, and the protocol-less data communication causes great problems in both programming and understanding, reducing the scalability of the system. In the design, the dual-core communication can adopt the same communication protocol as the system peripheral, for example, a Modbus protocol used for serial port communication, so that a protocol analysis function can be repeatedly utilized, and the portability can be improved. In addition, an applicable communication protocol can be defined by self according to actual needs, or the general communication protocol is modified appropriately to adapt to data communication with large data volume of the shared memory. The dual cores alternately obtain tokens according to the rule of the agreement, and then operate the corresponding shared memory segment. When dual cores simultaneously apply for the same token, the semaphore management unit decides who occupies the token first. In the design, mutual exclusion access of the double-core to the shared memory area can be realized by applying a corresponding token before accessing the memory. The other strategy for realizing data sharing is to define the same data locally at the double cores as shared data, and realize data synchronization through data communication between the double cores by using an interruption mode according to the principle of timely updating after writing. The method is suitable for the condition that the shared data meets a certain condition, namely the shared data is read only for one kernel, otherwise, the operation progress is almost not restricted due to the independent operation of the dual cores, and if the dual cores rewrite the shared data, the validity of the data cannot be ensured. Data communication between the two cores is completed, and besides a data transmission medium, namely a shared memory, a system is required to provide a set of signal mechanism for interaction between the two cores. Generally, the signaling mechanism includes both interrupt and non-interrupt signals. By using the signal mechanism and combining with the shared memory, various flexible communication modes can be designed. From the perspective of communication signals, communication modes can be classified into a polling mode and an interrupt mode. The polling method is mainly used for the case that events between the dual cores need to be executed in a certain order, for example, the initialization interaction between the dual cores when the system is started. In the field of parallel computing, many architectures in application, there are three parallel computing architectures (dual processor, hyper-threading, dual core processor) (a) dual processor architecture. Two separate processors share a bus and are connected to the Memory through the bus. The architecture has the characteristics that the COREs are mutually independent and are easy to construct, and the defect that the cooperation between the two processors is more dependent on the structure of software due to the reuse of the conventional general single-CORE processor. (b) Hyper-threading architecture (dual-threading), with two sets of CS and IL, but only one execution unit, in a processor. The hyper-threading architecture has the advantage that the problem of reduced CPU utilization caused by the conflict between the high speed of the CORE and the low speed of the MEMORY is solved by using a plurality of sets of register structures and a set of execution units. However, the disadvantage is that the control of the multi-threaded instruction stream is difficult, which makes the re-entry of the processing task difficult in software. (c) The dual-core processor architecture is internally provided with two sets of (CS + IL + ALU) structures and a bus interface. In a multi-thread architecture, the access speed bottleneck between the CORE and a memory is solved through a multi-instruction stream; in the dual-CORE processor architecture, two instruction streams are used for solving the contradiction between the operation capability of the processor and the CORE main frequency. The purpose of both is to improve the overall computational performance of the processor, but the approach is different.

Real-time systems not only require high throughput, but also require that all components of the system be reliable and predictable. A common real-time system consists of three parts, namely bottom hardware, an RTOS and an upper application. The application layer is operating system dependent, and although there are some algorithms that verify whether an application meets time limit requirements, these methods are all based on the operating system being on a real-time basis. The bottom hardware is required to be deterministic, software real-time operating systems such as VxWorks, windows CE, UC/OS-II, hopenOS and the like appear inside and outside at present, the real-time operating system realized by software design is executed in different microprocessors in a transplantable mode, and management tasks and operation tasks are finished by installing and modifying configuration files according to different hardware environments and by means of device driving functions. Although the real-time operating system is more and more mature, the processing speed still can not meet the requirements of the current times, the reaction speed is low, the driving program is more and more complex, the transplanting workload is large, and the like.

Disclosure of Invention

Aiming at the problems, the invention provides a structure which is simple, stable and convenient to realize; the method has the advantages of high reaction speed, simple driving program and small transplanting workload.

The above object of the present invention can be achieved by a method for processing data of a dual-core CPU real-time operating system, which has the following features: sending an interrupt signal generated by FPGA logic into a real-time bare computer program by using a processing signal processing board card, and storing the real-time logic program on a CPU0 into a DDR0 bare computer memory DDR2 shared memory for memory logic distribution; the interrupt signal is sent to the processor of the CPU0, and is operated by respective programs and the inter-core communication of the CPU, and the real-time bare computer program of the CPU0 responds and processes the interrupt signal; displaying a non-real-time Linux operating system through an application program, and operating the non-real-time operating system on the CPU1 to form a dual-core CPU processor operating system for simultaneously processing a non-real-time task and a real-time task; generating an interrupt signal needing to be processed in real time by FPGA logic of the signal processing board card; the CPU1 runs non-real-time task processing and non-real-time kernel program processing in an application program of a Linux operating system, the general CPU is set to be in an AMP mode, a core processor of each CPU processes different tasks, the non-real-time kernel of the CPU1 faces a non-real-time hardware environment, a bare computer program starts the non-real-time kernel on the CPU1, the CPU0 runs the bare computer program for network communication, responds to the real-time hardware environment, and exchanges data between the two CPUs in a memory sharing range shared by the two CPUs.

Compared with the prior art, the invention has the beneficial effects that:

simple structure, stability, it is convenient to realize. The invention adopts a processing signal processing board card to send an interrupt signal generated by FPGA logic into a real-time bare computer program, and stores the real-time logic program on a CPU0 into a DDR0 bare computer memory DDR2 shared memory for memory logic distribution; the dual-core CPU processor operating system real-time sound system is composed of a CPU0 bare computer program, a CPU1 non-real-time processing program and a shared DDR memory, and is simple in structure, stable and convenient to implement.

The reaction speed is high. The invention adopts FPGA logic of a signal processing board card to generate an interrupt signal needing to be processed in real time; the CPU1 runs non-real-time task processing and non-real-time kernel program processing in an application program of a Linux operating system, the general CPU is set to be in an AMP mode, a core processor of each CPU processes different tasks, a non-real-time kernel of the CPU1 faces to a non-real-time hardware environment, the CPU0 is started to run a bare computer program network for communication, the real-time hardware environment is responded, and data exchange is carried out between the two CPUs in a memory sharing range shared by the two CPUs. Under the condition that the original operating system on the CPU0 is modified slightly to adapt to the condition that the operating system does not run on the CPU1, the real-time response to the real-time hardware interruption can be realized only by realizing a simple bare computer processing program on the CPU1, the driving design complexity can be simplified on the basis of ensuring the stable and reliable running of the operating system, the reaction speed of a processor is increased, and the project development period is greatly shortened.

The driving program is simple, and the transplanting workload is small. The interrupt signal of the invention is sent to the processor of the CPU0, runs and communicates with the kernel of the CPU by respective programs, and is responded and processed by the real-time bare computer program of the CPU 0; the non-real-time Linux operating system is displayed through an application program, the non-real-time operating system is operated on the CPU1, and the dual-core CPU processor operating system which simultaneously processes the non-real-time task and the real-time task is formed and can simultaneously process the non-real-time task and the real-time task. The FPGA logic of the signal processing board card generates an interrupt signal needing real-time processing, the interrupt signal is connected to a processor of the CPU0, and the real-time bare computer program of the CPU0 responds and processes the interrupt signal. The general purpose CPU is set to be in an AMP mode, namely, the core processors of all CPUs process different tasks without mutual interference, taking ARM9 as an example: the ARM9 is a dual-core processor, the CPU1 runs a common Linux operating system, is used for processing non-real-time tasks and non-real-time kernel programs in application programs, and is mainly oriented to non-real-time hardware environments such as network communication. The CPU0 runs a bare computer program, the driving program is simple, and the transplanting workload is small. The bare computer program has the characteristics of simple structure and quick response, and is mainly used for responding to real-time hardware environments, such as peripherals of a mouse, a keyboard, data acquisition and the like. The project processed by the method can be shortened to a week in the original 3 months, and because each CPU runs an independent program, the interference between the CPUs is avoided, and the stability of the system is greatly enhanced.

The universality is high. The invention relates to a method for realizing data processing of a dual-core CPU real-time operating system, which can be used for any CPU which supports more than 2 processing units in an AMP mode, and comprises imported and domestic processors such as a DSP (digital signal processor), an ARM (advanced RISC machine), a Feiteng and the like.

The invention is suitable for processors with any dual-core and more than dual-core CPU architecture.

Drawings

The patent is further described below with reference to the drawings and examples.

FIG. 1 is a block diagram of the real-time response hardware of the dual core CPU processor operating system of the present invention;

FIG. 2 is a block diagram of a dual core CPU processor operating system real-time response flow;

the technical scheme of the invention is further described in detail in the following with reference to the attached drawings.

Detailed Description

Refer to fig. 1 and 2. According to the invention, an interrupt signal generated by FPGA logic is sent to a real-time bare computer program by adopting a processing signal processing board card, and the real-time logic program on a central processing unit CPU0 is stored into a DDR0 bare computer memory DDR2 shared memory for memory logic distribution; the interrupt signal is sent to the processor of the CPU0, and is operated by respective programs and the inter-core communication of the CPU, and the real-time bare computer program of the CPU0 responds and processes the interrupt signal; displaying a non-real-time Linux operating system through an application program, and running the non-real-time operating system on the CPU1 to form a dual-core CPU processor operating system for simultaneously processing a non-real-time task and a real-time task; generating an interrupt signal needing to be processed in real time by FPGA logic of the signal processing board card; the CPU1 runs non-real-time task processing and non-real-time kernel program processing in an application program of a Linux operating system, the general CPU is set to be in an AMP mode, a core processor of each CPU processes different tasks, the non-real-time kernel of the CPU1 faces a non-real-time hardware environment, a bare computer program starts the non-real-time kernel on the CPU1, the CPU0 runs the bare computer program for network communication, responds to the real-time hardware environment, and exchanges data between the two CPUs in a memory sharing range shared by the two CPUs.

In the signal processing board card, the FPGA logic generates an interrupt signal needing real-time processing, the interrupt signal is transmitted to a processor of the CPU0, and the real-time bare computer program of the CPU0 responds and processes the interrupt signal.

The real-time logic program on the CPU0 is responsible for processing an interrupt signal of the FPGA bare engine of the signal processing board card; CPU0 and CPU1 share 1GB DDR memory, and 1GB DDR memory is used for program operation of CPU0 and CPU1d and inter-core communication of CPU. CPU1 and the non-real-time operating systems running on CPU1 handle complex, non-real-time tasks such as applications, network communications, virtualization, etc.

The logical real-time operating program of CPU0 runs on 320M of 1GB memory, with the first 256M for the data and programs of the program itself and the last 64MB for communication with CPU 1.

When compiling programs on the CPU0 and the CPU1, memory ranges of the programs on the CPU0 and the CPU1 are specified, the CPU0 and the CPU1 occupy 1GB DDR memory together, wherein the CPU0 occupies the first 320MB, the CPU1 occupies the second 768MB, the middle overlapped part is a memory range shared by the two CPUs, and the shared memory range is used for data exchange between the two CPUs.

The CPU1 runs an operating system of a Linux non-real kernel, is used for non-real tasks such as application programs, network communication, virtualization, and the like, and is mainly oriented to a non-real-time hardware environment, such as network communication. In the process of power-on and startup, a bare computer real-time operation program in the CPU0 is loaded first, and after program codes and the like of the CPU1 are loaded to an internal buffer of the CPU1, and a reset register is released, a CPU1 program is started.

All features disclosed in this specification may be combined in any combination, except features and/or steps that are mutually exclusive. While the present invention has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.

Claims

1. A data processing method of a dual-core CPU real-time operating system has the following characteristics: sending an interrupt signal generated by FPGA logic into a real-time bare computer program by using a processing signal processing board card, and storing the real-time logic program on a CPU0 into a DDR0 bare computer memory DDR2 shared memory for memory logic distribution; the interrupt signal is sent to the processor of the CPU0, and is operated by respective programs and the inter-core communication of the CPU, and the real-time bare computer program of the CPU0 responds and processes the interrupt signal; displaying a non-real-time Linux operating system through an application program, and operating the non-real-time operating system on the CPU1 to form a dual-core CPU processor operating system for simultaneously processing a non-real-time task and a real-time task; generating an interrupt signal needing to be processed in real time by FPGA logic of the signal processing board card; the CPU1 runs non-real-time task processing and non-real-time kernel program processing in an application program of a Linux operating system, the general CPU is set to be in an AMP mode, a core processor of each CPU processes different tasks, the non-real-time kernel of the CPU1 faces a non-real-time hardware environment, a bare computer program starts the non-real-time kernel on the CPU1, the CPU0 runs the bare computer program for network communication, responds to the real-time hardware environment, and exchanges data between the two CPUs in a memory sharing range shared by the two CPUs.

2. The method for processing data of a dual-core CPU real-time operating system according to claim 1, wherein: in the signal processing board card, the FPGA logic generates an interrupt signal needing real-time processing, the interrupt signal is transmitted to a processor of the CPU0, and the real-time bare computer program of the CPU0 responds and processes the interrupt signal.

3. The method for processing data of a dual-core CPU real-time operating system according to claim 1, wherein: and the real-time logic program on the CPU0 is responsible for processing the interrupt signal of the FPGA bare engine of the signal processing board card.

4. The method for processing data of a dual-core CPU real-time operating system according to claim 1, wherein: CPU0 and CPU1 occupy 1GB DDR memory, 1GB DDR memory for CPU0 and CPU1d program operation and CPU inter-core communication.

5. The method for processing data of a dual-core CPU real-time operating system according to claim 1, wherein: the logical real-time operating program of CPU0 runs on 320M of 1GB memory, with the first 256M for the data and programs of the program itself and the last 64MB for communication with CPU 1.

6. The method for processing data of a dual-core CPU real-time operating system according to claim 1, wherein: when compiling programs on the CPU0 and the CPU1, memory ranges of the programs on the CPU0 and the CPU1 are specified, the CPU0 and the CPU1 occupy 1GB DDR memory, wherein the CPU0 occupies the front 320MB, the CPU1 occupies the rear 768MB, the middle overlapped part is a memory range shared by the two CPUs, and the shared memory range is used for data exchange between the two CPUs.

7. The method for processing data of a dual-core CPU real-time operating system according to claim 1, wherein: operating the operating system application program of the Linux non-real kernel, performing network communication, virtualizing a non-real task, and performing network communication in a non-real-time hardware environment.

8. The method for processing data of a dual-core CPU real-time operating system according to claim 1, wherein: in the process of powering on and starting up, the real-time operating program of the bare computer in the CPU0 is loaded first, the program code of the CPU1 is loaded to the internal buffer of the CPU1, the reset register is released, and the program of the CPU1 is started.