CN112187233A - Reset device, method, clock system and electronic equipment - Google Patents
Reset device, method, clock system and electronic equipment Download PDFInfo
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Abstract
The application discloses resetting device, method, clock system and electronic equipment, relates to the field of clock design, and the resetting device comprises: the output end of the clock generation circuit is connected with the input end of the clock signal, and the clock generation circuit is used for: when detecting that the system clock circuit does not output a first clock signal, acquiring an asynchronous reset signal, wherein the asynchronous reset signal is used for executing reset operation on an asynchronous reset sequential circuit, and the first clock signal is used for executing reset operation on a synchronous reset circuit; and generating a second clock signal according to the asynchronous reset signal, wherein the second clock signal is used for executing reset operation on the synchronous reset circuit. Therefore, when the system does not output the first clock signal to reset the synchronous reset circuit, the clock generation circuit can generate the second clock signal for executing the reset operation on the synchronous reset circuit according to the asynchronous reset signal, and the synchronous reset circuit is prevented from being incapable of resetting when the synchronous reset circuit does not receive the first clock signal.
Description
Technical Field
The present disclosure relates to the field of clock design, and more particularly, to a reset device, a reset method, a clock system, and an electronic device.
Background
The system on chip or other lsi may include a processor, a bus, and other electronic components, and since different electronic components may use different timing circuits, an asynchronous reset timing circuit and a synchronous reset timing circuit may exist simultaneously in the system on chip or other lsi, which puts new requirements on clock design.
Disclosure of Invention
The application provides a reset device, a reset method, a clock system and an electronic device, so as to overcome the defects.
In a first aspect, an embodiment of the present application provides a reset device, which is applied to a clock system, where the clock system includes an asynchronous reset sequential circuit, a synchronous reset sequential circuit, and a system clock circuit, the system clock circuit is connected to a clock signal input end of the synchronous reset circuit, the system clock circuit is configured to input a first clock signal to the clock signal input end, the first clock signal is configured to trigger the synchronous reset circuit to perform a reset operation, and the reset device includes: a clock generation circuit, an output of the clock generation circuit being connected to the clock signal input, the clock generation circuit being configured to: when detecting that the system clock circuit does not output a first clock signal, acquiring an asynchronous reset signal, wherein the asynchronous reset signal is used for executing reset operation on the asynchronous reset sequential circuit; and generating a second clock signal according to the asynchronous reset signal, wherein the second clock signal is used for triggering the synchronous reset circuit to execute reset operation.
In a second aspect, an embodiment of the present application further provides a clock system, including: the asynchronous reset device comprises an asynchronous reset sequential circuit, a synchronous reset sequential circuit, a system clock circuit and the reset device, wherein the system clock circuit is connected with a clock signal input end of the synchronous reset circuit, the system clock circuit is used for inputting a first clock signal to the clock signal input end, the first clock signal is used for triggering the synchronous reset circuit to execute reset operation, and an output end of a clock generating circuit is connected with the clock signal input end.
In a third aspect, an embodiment of the present application further provides an electronic device, which includes a device body and the clock system described above, where the clock system is disposed in the device body.
In a fourth aspect, an embodiment of the present application further provides a reset method, which is applied to a clock system, where the clock system includes an asynchronous reset sequential circuit, a synchronous reset sequential circuit, and a system clock circuit, the system clock circuit is connected to a clock signal input end of the synchronous reset circuit, the system clock circuit is configured to input a first clock signal to the clock signal input end, the first clock signal is configured to trigger the synchronous reset circuit to perform a reset operation, and the method includes: when detecting that the system clock circuit does not output a first clock signal, acquiring an asynchronous reset signal, wherein the asynchronous reset signal is used for executing reset operation on the asynchronous reset sequential circuit; generating a second clock signal according to the asynchronous reset signal; and inputting the second clock signal to the clock signal input end, and instructing the synchronous reset sequential circuit to execute reset operation according to the second clock signal.
The application provides a resetting means, method, clock system and electronic equipment, is applied to clock system, clock system includes asynchronous reset sequential circuit, synchronous reset sequential circuit and system clock circuit, system clock circuit with synchronous reset circuit's clock signal input end is connected, resetting means includes: a clock generation circuit. The system clock circuit can output a first clock signal to a clock signal input end of the synchronous reset circuit, the synchronous reset circuit executes reset operation when the clock signal input end receives the first clock signal, the synchronous reset circuit cannot reset according to the first clock when the clock generation circuit detects that the system clock circuit does not output the first clock signal, and then the clock generation circuit generates a second clock signal according to the asynchronous reset signal when acquiring the asynchronous reset signal and inputs the second clock signal to the clock signal input end. The asynchronous reset signal is used for executing reset operation on the asynchronous reset sequential circuit, and the synchronous reset circuit cannot execute the reset operation when not receiving the first clock signal, so that when the system does not output the first clock signal to reset the synchronous reset circuit, the clock generation circuit can generate a second clock signal for executing the reset operation on the synchronous reset circuit according to the asynchronous reset signal, and output instability of the whole system caused by the fact that the synchronous reset circuit is not reset when the synchronous reset circuit does not receive the first clock signal is avoided, and system disorder is avoided.
Additional features and advantages of embodiments of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of embodiments of the present application. The objectives and other advantages of the embodiments of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram illustrating an asynchronous reset circuit provided by an embodiment of the present application;
FIG. 2 is a schematic diagram of a synchronous reset circuit provided by an embodiment of the present application;
FIG. 3 shows a corresponding timing diagram of FIG. 2;
FIG. 4 is a circuit diagram of a reset device according to an embodiment of the present application;
FIG. 5 shows a corresponding timing diagram of FIG. 4;
FIG. 6 is a circuit diagram of a reset device according to another embodiment of the present application;
FIG. 7 is a circuit schematic diagram of a reset apparatus provided in accordance with yet another embodiment of the present application;
FIG. 8 is a circuit schematic diagram of a reset device provided in accordance with yet another embodiment of the present application;
FIG. 9 is a circuit schematic diagram of a reset device provided in accordance with yet another embodiment of the present application;
FIG. 10 shows a corresponding timing diagram of FIG. 9;
FIG. 11 illustrates a method flow diagram of a reset method provided by an embodiment of the present application;
FIG. 12 is a block diagram of a clock system provided by an embodiment of the present application;
FIG. 13 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;
fig. 14 shows a storage unit for storing or carrying program codes for implementing the methods according to the embodiments of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
In a digital integrated circuit chip, a reset circuit is an indispensable part for ensuring the normal operation of the chip. With the increasing scale of chips, the structure of the reset circuit and the access mode of the reset circuit and other circuits are more and more complicated. In particular, in very large scale integrated circuit chips, there are typically multiple clock domains, each having its own reset signal. For example, in a complex System on Ch ip (SOC) design, it is often necessary to integrate multiple circuit designs, wherein the multiple circuits may include modules such as a CPU, a bus, and an accelerator. However, due to different circuit design rules, asynchronous reset and synchronous reset sequential circuits may exist in the SOC at the same time, which puts new requirements on the high-level reset logic design of the SOC.
The asynchronous reset sequential circuit is a circuit which uses a clock and is reset asynchronously. Specifically, the timing circuit may be a register, and the asynchronous reset is implemented by using a register with an asynchronous reset port, as shown in fig. 1, the asynchronous reset register resets the output at the moment when the reset signal is detected to be valid, and the operation is not directly connected with the input of the clock signal CLK.
The synchronous reset timing circuit is a circuit that uses a clock and has a reset mode of synchronous reset. Specifically, the sequential circuit may be a register, the register in the design of the synchronous reset circuit does not have an asynchronous reset port, and when the register of this type is reset, the data port selector is used to input the reset value to the data port of the register when the reset signal is valid. As shown in fig. 2, the register J1 changes the output value of the register to the input value of the register at the time before the clock signal CLK is asserted when the clock signal CLK is asserted, so that the synchronous reset timing circuit shown in fig. 2 needs the input value of the register to be equal to the reset value at the time before the clock signal CLK is asserted, for example, the reset value may be 0. In the embodiment of the present application, when the reset signal is asserted, the output of the selector M1 is the input of the terminal S1 of the selector M1, and when the reset signal is not asserted, the output of the selector M1 is the input of the terminal S2 of the selector M1. As an embodiment, the input signal may be a signal with a normally high level, i.e. the logic value of the input signal is normally 1.
Therefore, the synchronous reset timing circuit shown in fig. 2 needs to have the reset signal active at the time before the clock signal CLK is active. It is assumed that the clock signal CLK is active, that is, the clock signal goes from low to high, that is, a rising edge is triggered, and the reset signal is active, that is, the reset signal is low, so that at the time before the rising edge of the clock signal CLK, the reset signal should be low, so that the output of the selector M1, that is, the input of the register J1Go to low level, i.e. D n0, and further when the rising edge of the clock signal CLK comes, Qn+1＝DnWhere n denotes time. Therefore, the synchronous reset timing circuit requires that the reset signal be synchronized with the input clock.
However, the inventor found in the research that, since the asynchronous reset timing circuit has no requirement for the clock signal CLK, when the asynchronous reset timing circuit is reset, the clock signal CLK may not be generated by the system, so that the asynchronous reset timing circuit is reset, and the synchronous reset timing circuit is not reset. As shown in fig. 3, the gate clock in fig. 3 is the clock signal CLK in fig. 2, wherein the system clock signal, the enable signal, and the gate enable signal are signals for generating the clock signal CLK. Specifically, the system clock signal is a basic clock signal provided by a system (such as a system on a chip) for each chip in the system, and each chip can receive the system clock signal at an appropriate time through an enable signal and a control mode of a logic gate on the basis of the system clock signal according to the requirement of the chip on the clock, and can generate a new clock signal through frequency multiplication, frequency division and latching.
The enable signal is used to enable the clock signal CLK in fig. 2, for example, the enable signal may be used as an instruction for a processor such as a CPU to notify a system to input a clock to a register, the gate enable signal is used to go high when both the enable signal and the system clock signal are high, and the system clock signal is used as the clock signal CLK for the register when the gate enable signal is high.
As can be seen from fig. 3, when the reset signal is active, i.e., the periods of the low level are 2 nd and 3 rd clocks of the system clock signal, and 7 th and 8 th clocks of the system clock signal, respectively, it should be noted that one clock of the system clock signal refers to the time elapsed by one high level and one low level which are adjacent to each other, i.e., the period of one clock signal, and the system clock signal is a clock signal of a plurality of periods.
At the time of the 7 th and 8 th clocks of the system clock signal, the input D of the register is at a low level, i.e., logic 0, at the time of the rising edge between the 7 th to 8 th clocks, when the output value of the output signal is equal to the 7 th clock, so that the output of the register becomes 0, i.e., is reset, at the time of the rising edge between the 7 th to 8 th clocks. In the 2 nd and 3 rd clocks, since the gate clock is not enabled, and is in a normally low state, and the rising edge is not triggered, the synchronous reset timing circuit is not reset, and the asynchronous reset timing circuit is reset, which may cause the system to be unstable. Specifically, assume that the circuitry of the CPU in the SOC uses synchronous reset, while the bus and peripherals use asynchronous reset. During system power-up, the CPU cannot be reset if a reset signal occurs before clock enable. At this time, the internal register of the CPU is in an indeterminate state, and the indeterminate state is transmitted to the peripheral equipment along with the data and the control bus connected with the indeterminate state. When the system clock is started, the peripheral samples the unstable state signals from the CPU bus, and further transmits the unstable states, so that more registers in the SOC system are in the unstable states, and the normal operation of the whole system is influenced.
Therefore, in order to overcome the above-mentioned defects, an embodiment of the present application provides a reset device, which can still be reset when the clock signal CLK of the synchronous reset timing circuit is not enabled, and can effectively avoid the situation that the asynchronous reset timing circuit completes the reset and the synchronous reset timing circuit cannot effectively reset in the SOC design in which the asynchronous reset and the synchronous reset timing circuit coexist.
Specifically, referring to fig. 4, fig. 4 shows a resetting device. The reset device is applied to a clock system which can be the SOC described above, or can be another circuit system using a clock signal, and the clock system includes an asynchronous reset sequential circuit, a synchronous reset sequential circuit, and a system clock circuit, where the asynchronous reset sequential circuit and the system clock circuit are not shown in the figure, and the register J1 and the selector M1 constitute the synchronous reset sequential circuit. Specifically, the reset device includes: the clock generation circuit 410.
In one embodiment, the system clock circuit is connected to a clock signal input terminal (i.e., the clock terminal C of the register J1) of the synchronous reset circuit, and the system clock circuit is configured to provide the synchronous reset circuit with a first clock signal, which is a clock signal provided by a system for triggering the synchronous reset circuit to perform the reset operation, i.e., the first clock signal serves as a trigger signal for the synchronous reset circuit to perform the reset operation. For example, the first clock signal may be the gate clock described above. For the description of the asynchronous reset timing circuit and the synchronous reset timing circuit, reference may be made to the foregoing contents, which are not described herein again.
An output of the clock generation circuit 410 is connected to the clock signal input. Specifically, the output terminal of the clock generation circuit 410 is connected to the clock terminal C of the register J1, the control terminal CN of the selector M1 is configured to receive the asynchronous reset signal, when the asynchronous reset signal is at a high level, the logic value of the output terminal of the selector M1 is the logic value of the input signal at the terminal S2, and when the asynchronous reset signal is at a low level, the logic value of the output terminal of the selector M1 is the logic value of the input signal at the terminal S1. As can be seen from fig. 4, the logic value of the input signal at the terminal S1 is 0, so that when the reset signal is at low level, the logic value of the input terminal D of the input register J1 is 0, so that when the next rising edge of the clock terminal C of the register J1 comes, the output value of the register J1 is equal to the logic value of the input terminal D when the reset signal is at low level, that is, the output value of the register J1 is equal to 0, that is, is reset.
The clock generation circuit 410 is configured to obtain an asynchronous reset signal when detecting that the system clock circuit does not output the first clock signal, where the asynchronous reset signal is used to perform a reset operation on the asynchronous reset sequential circuit. For example, the asynchronous reset signal may be the reset signal in fig. 3 described above, and specifically, the asynchronous reset timing circuit is reset when the asynchronous reset signal is at a low level. Then, the clock generating circuit 410 generates a second clock signal according to the asynchronous reset signal; and inputting the second clock signal to the clock signal input end, wherein the second clock signal is used for triggering the synchronous reset circuit to execute the reset operation, namely the second clock signal is used as a trigger signal for the synchronous reset circuit to execute the reset operation.
In one embodiment, the second clock signal generated by the clock generation circuit 410 is also capable of generating an active level state, which is the same as the active level state that can be generated by the first clock signal provided by the system. For example, taking the first clock signal as the gate clock, if the active level state of the first clock signal is a state in which the low level changes to the high level, i.e., a rising edge, the second clock signal generated by the clock generation circuit 410 can also generate a rising edge.
As an embodiment, the clock generating circuit 410 may generate the second clock signal according to the asynchronous reset signal, specifically, the clock generating circuit 410 is a clock generator, and is capable of receiving a system clock, and generating the second clock signal by performing a preset process on the system clock, where the second clock signal may be identical to the first clock signal, that is, the period and the pulse width are identical, where the preset process may be nothing but an operation manner such as frequency multiplication, frequency division, phase locking, or a logic operation, where the logic operation includes a logical and operation, a logical not operation, for example, inverting the signal so that the high level of the signal becomes the low level, and the low level becomes the high level. The clock generation circuit 410 can monitor the level change of the asynchronous reset signal and generate the second clock signal when the level of the asynchronous reset signal changes to a designated level.
As an embodiment, the clock generation circuit 410 may generate the second clock signal according to the asynchronous reset signal in such a manner that the clock generation circuit 410 can monitor a level change of the asynchronous reset signal and perform a preset process on the asynchronous reset signal to generate the second clock signal when the level of the asynchronous reset signal becomes a designated level. Specifically, the asynchronous reset signal may be directly used as the second clock signal, or may be processed by a logic element such as a flip-flop to obtain the second clock signal, which will be described in the following embodiments.
Therefore, when the system does not output the first clock signal to reset the synchronous reset circuit, the clock generation circuit can generate the second clock signal for triggering the synchronous reset circuit to execute the reset operation according to the asynchronous reset signal, and the output instability of the whole system can be avoided if the asynchronous reset circuit is reset and the synchronous reset circuit is not reset when the synchronous reset circuit does not receive the first clock signal, so that the system disorder is avoided. Specifically, referring to fig. 5, fig. 5 shows a timing diagram of the clock system. As can be seen from comparison of fig. 5 with fig. 3, in a period in which the system clock circuit does not supply the first clock signal to the synchronous reset timing circuit, that is, a period in which the gate clock is not enabled and continues to be in a low level state, that is, a period in which the clock terminal C of the register J1 does not receive the gate clock, in fig. 3, the output signal is not reset, that is, continues to be at a high level, and in fig. 5, the clock terminal C of the register J1 can change the output signal to the logic value of D in the low level stage of the reset signal in response to a transition in which the low level changes to the high level, at the time when the reset signal changes from the low level to the high level.
As can be seen from fig. 3 and 5, the asynchronous reset signal is a signal that alternates between a first level and a second level, and the synchronous reset timing circuit is configured to perform a reset operation when a signal input to the clock signal input terminal is a specified level or a level change occurs, wherein the first level may be a low level or a high level, and if the first level is a low level, the second level is a high level, and if the first level is a high level, the second level is a low level. As an embodiment, the designated level may be a low level or a high level, wherein the level change may be a low level to a high level (i.e., a rising edge) or a high level to a low level (i.e., a falling edge).
Therefore, as an embodiment, the clock generation circuit 410 may directly use the asynchronous reset signal as the second clock signal, and as shown in fig. 4, the clock generation circuit 410 may input the asynchronous reset signal to the clock terminal C of the register J1 when acquiring the asynchronous reset signal, so that as the asynchronous reset signal is alternately changed between the first level and the second level, the signal at the clock terminal C of the register J1 is also alternately changed between the first level and the second level, so as to be able to change to the designated level or change in level, thereby resetting the register J1.
In addition, it is considered that if the asynchronous reset signal is a pulse signal and the width of the pulse is relatively narrow, the time is too short when the high and low levels change, so that the synchronous reset timing circuit does not respond to the asynchronous reset signal, and the synchronous reset timing circuit cannot accurately assign the output value, thereby causing the output result to be in an indeterminate state. Therefore, in order to avoid this problem, the clock generation circuit is further configured to: generating a signal which is kept at a first level for a first time length when the asynchronous reset signal is detected to change from a second level to the first level; and generating a signal which is kept at the second level for a second time length when the asynchronous reset signal is detected to change from the first level to the second level, wherein the signal which is alternately changed between the first level and the second level and generated by the clock generation circuit is used as a second clock signal.
As an implementation manner, the first time length and the second time length may be set according to actual use, and in some embodiments, the signal output by the clock generation circuit is also a periodic signal that alternates between a first level and a second level, and the time length of one period is the sum of the time length T1 when the output signal is at the first level and the time length T2 when the output signal is at the second level, that is, the period T is T1+ T2. As an embodiment, the t1 and the t2 may be different or different, and in the embodiment of the present application, the t1 and the t2 are the same, and the period of the signal output by the clock generation circuit is the same as the period of the first clock signal. In another embodiment, in the case where the pulse width of the asynchronous reset signal is less than a specified width, the first time length is the same as the time length that the asynchronous reset signal is at a first level, the second time length is the same as the time length that the asynchronous reset signal is at a second level, that is, the period of the signal output from the clock generation circuit is the same as that of the asynchronous reset signal, and if the pulse width of the asynchronous reset signal is not less than a prescribed width, the pulse width of the signal output by the clock generation circuit can be made larger than the pulse width of the asynchronous reset signal by reasonably setting the first time length and the second time length, so that when the signal output from the clock generation circuit is used as the second clock signal, the second clock signal can satisfy the requirement of synchronous reset sequential circuit, and the output of the synchronous reset sequential circuit is prevented from being unstable due to the over-narrow pulse width of the second clock signal.
Referring to fig. 6 as an implementation manner, fig. 6 shows that another embodiment of the present application provides a reset apparatus, as shown in fig. 6, the clock generation circuit 410 further includes a flip-flop 411 and an assignment circuit 412, a clock terminal of the flip-flop 411 is used for receiving the asynchronous reset signal, an output terminal of the flip-flop 411 is connected to an input terminal of the clock signal, the assignment circuit 412 is connected to an input terminal of the flip-flop 411, wherein an output terminal of the flip-flop 411 serves as an output terminal of the clock generation circuit 410.
As shown in fig. 6, the synchronous reset timing circuit may be composed of a register J1 and a selector M1, the input terminal of the clock signal is a clock terminal C1 of a register J1, the evaluation circuit 412 and the flip-flop 411 can both receive an asynchronous reset signal, the control terminal CN of the selector M1 also receives an asynchronous reset signal, and the output terminal of the flip-flop 411 is connected to the clock terminal C of the register J1.
The evaluation circuit 412 is configured to output a first signal when the asynchronous reset signal is at a second level, where the first signal is at a first level; the flip-flop 411 is configured to output a signal equal to the first signal when the asynchronous reset signal received by the clock terminal changes from the second level to the first level, and output a signal equal to the inverted signal of the first signal when the asynchronous reset signal received by the clock terminal changes from the first level to the second level. In one embodiment, the first level is a low level and the second level is a high level.
Specifically, as shown in fig. 7, the evaluation circuit 412 includes a first selector M2 and an inverter L1, the first selector M2 includes a first selection input terminal S22, a second selection input terminal S21, a first control terminal CN2 and a first selection output terminal P2, a signal input to the first selection input terminal S22 is at a first level, that is, a logic value of the input S22 in fig. 7 is 0, an output terminal of the flip-flop 411 is connected to the second selection input terminal S21 through the inverter, and the first control terminal CN2 is configured to receive the asynchronous reset signal. In the embodiment of the present application, the flip-flop 411 is the register J2 in fig. 7, and the register J2 may be a double-edge flip-flop, that is, an assignment operation is performed when the signal at the clock terminal is a rising edge and a falling edge.
The first selector M2 is configured to control the output signal of the first selection output terminal P2 to be the signal input to the first selection input terminal S22 when the asynchronous reset signal received by the first control terminal CN2 is at a high level, and control the output signal of the first selection output terminal P2 to be the signal input to the second selection input terminal S21 when the asynchronous reset signal received by the first control terminal CN2 is at a low level. As shown in fig. 7, the first selector M2, the inverter L1 and the register J2 form a double-edge flip-flop, that is, the register J2 performs an assignment operation when the signal at the clock terminal C1 rises (changes from low level to high level) or falls (changes from high level to low level), that is, outputs a value equal to the value at the terminal D1 at the time before the rising edge or the falling edge.
Specifically, the logical value of each port varies as follows:
when the asynchronous reset signal is 1, CN2 is 1, P2 is equal to the value of S22, i.e., P2 is equal to 0, the value of the D1 end of the register J2 is also 0, and since the signal of the clock end C of the register J1 does not generate a rising edge, the value of the output end Q1 of the register J2 keeps unchanged the previous state value, for example, the previous state logic value is 1, and the output end Q1 of the register J2 is also 1.
When the asynchronous reset signal is 0, i.e., the signal at the clock terminal C1 triggers a falling edge, CN2 is 0, P2 is equal to the value of S21, i.e., P2 is equal to the inverted logic value of Q1, i.e., P2 is equal to 0, then the logic value at the D1 terminal of the input register J2 is 0, the output value Q1 is equal to the previous time of the falling edge, i.e., when the previous asynchronous reset signal is 1, the value at the D1 terminal, i.e., the output value Q1 is 0, and at the current time, the value at the S21 terminal is the inverted value of Q1, i.e., equal to 1, i.e., D1 at the current time is equal to 1.
When the asynchronous reset signal is again 1, i.e. the signal at the clock terminal C1 triggers a rising edge, P2 equals the value of S22, i.e. P2 equals 0, the output value Q1 equals the previous time instant of the rising edge, i.e. the previous time instant when the asynchronous reset signal was 0, the value at the terminal D1, i.e. the output value Q1, is 1, and D1 at the current time instant is 0.
Thus, the output Q1 is pulled low at the detection of the falling edge of the asynchronous reset signal and Q1 is pulled high at the detection of the rising edge of the asynchronous reset signal, and thus this process generates a rising edge at Q1, the rising edge of Q1 serving as the reset clock signal for register J1.
As an embodiment, in order to facilitate the synchronous reset timing circuit to perform reset using the first clock signal when the system clock circuit outputs the first clock signal, and to reset using the second clock signal when the system clock circuit does not output the first clock signal, the reset apparatus further includes a selection switch. As shown in fig. 8, assuming that the synchronous reset timing circuit is composed of the above-described register J1 and the selector M1, the system clock circuit 310 and the clock generation circuit 410 are both connected to the clock terminal C of the register J1 through the selection switch 420. The selector switch 420 is used to: when detecting that the system clock circuit 310 does not output the first clock signal, the system clock circuit 310 is turned off from the clock signal input terminal C, and the clock generation circuit 410 is turned on from the clock signal input terminal C; when it is detected that the system clock circuit 310 outputs the first clock signal, the system clock circuit 310 is turned on with the clock signal input terminal C, and the clock generation circuit 410 is turned off with the clock signal input terminal C.
As an embodiment, the selection switch may include two input terminals and an output terminal, the two input terminals are respectively connected to the clock generation circuit 410 and the system clock circuit 310, the output terminal is connected to the clock terminal C of the register J1, and the control terminal is used for detecting whether the system clock circuit outputs the first clock signal, and the specific detection manner may be that the system clock circuit outputs the first clock signal according to a clock enable signal, the clock enable signal may be the aforementioned enable signal or a gate enable signal, when the clock enable signal is at an active level (for example, a high level), the system clock circuit outputs the first clock signal, and when the clock enable signal is at an inactive level, the system clock circuit does not output the first clock signal. The control terminal can receive the clock enable signal and control the connection between the input terminal and the output terminal of the clock generation circuit 410 to be turned on and the other input terminal and the output terminal to be turned off when the clock enable signal is at an inactive level. When the clock enable signal is active, the input terminal and the output terminal of the system clock circuit 310 are controlled to be connected and the other input terminal and the output terminal are controlled to be disconnected.
In the embodiment of the present application, the selectors may be transistors, thyristors, and other electronic devices having a control terminal and two connection terminals.
Specifically, referring to fig. 9, the selection switch 420 may be the selector M3 in fig. 9, the selection switch 420 includes a second selector M3, the second selector M3 includes a third selection input terminal S31, a fourth selection input terminal S32, a second control terminal CN3 and a second selection output terminal P3, and the clock generation circuit is connected to the third selection input terminal S31, that is, the output terminal Q1 of the register J2 is connected to the third selection input terminal S31. The system clock circuit is connected to the fourth selection input terminal S32, the second selection output terminal P3 is connected to the clock signal input terminal, that is, the second selection output terminal P3 is connected to the clock terminal C of the register J1, the second control terminal CN3 is configured to receive a clock enable signal EN, and the system clock circuit 310 is configured to output a first clock signal when the clock enable signal EN is at an active level, where the active level may be a high level. The specific implementation of the clock enable signal EN can refer to the aforementioned enable signal, and is not described herein again.
The selector M3 is used to: when the clock enable signal EN received by the second control terminal CN3 is at an active level, control the output signal of the second selection output terminal P3 to be the first clock signal input by the system clock circuit 310 to the fourth selection input terminal S32; when the clock enable signal EN received by the second control terminal CN3 is not at an active level, the output signal of the second selection output terminal P3 is controlled to be the second clock signal input by the clock generation circuit to the third selection input terminal S31.
The system clock circuit 310 includes a latch J3 and a logic and gate L2, wherein the latch J3 may also be a register, and the latch J3 is active when the clock terminal E is at a low level, unlike the aforementioned register J1. In the embodiment of the present application, the register and the flip-flop may be D flip-flops.
The clock terminal E of the latch J3 is used for receiving the inverted signal of the system clock CLK, the input terminal D3 of the latch J3 is used for receiving the clock enable signal EN, the output terminal Q3 of the latch J3 is connected to one logic input terminal of the logic and gate L2, the other logic input terminal of the logic and gate L2 is used for receiving the system clock CLK, and the output terminal of the logic and gate L2 is connected to the fourth selection input terminal S32.
Specifically, the principle of fig. 9 is described in terms of logical values:
when the asynchronous reset signal is 0, the clock terminal C1 of the register J2 is 0, Q1 holds D1 in the previous state, that is, 0, Q1 becomes 0, Q1 is 1 after inversion, and the output of the selector M2 is equal to the value of Q1 after inversion, so D1 becomes 1.
At this time, the clock enable signal EN is 0, the system clock CLK is 1, the output terminal Q3 of the latch J3 holds the logic value of the clock enable signal EN in the previous state, i.e., the output terminal Q3 of the latch J3 is equal to 0, then the output of the and gate is 0, the output of the selector M3 is equal to Q1 at this time, i.e., the output of the selector M3 is 0, the output of the selector M1 is 0, and the output Q of the register J1 is also 0 at this time.
If the asynchronous reset signal becomes 1, the clock terminal C1 of the register J2 is 1, Q1 is equal to D1, i.e., Q1 is equal to 1, Q1 is 0 after inversion, the output of the M selector M2 is equal to the value of S22 at this time, so D1 becomes 0, then, at this time, the clock enable signal EN is 0, the system clock CLK is 1, the output terminal Q3 of the latch J3 holds EN of the previous state, i.e., Q3 is equal to 0, then, the output of the and gate is 0, the output of the selector M3 is equal to Q1 at this time, the clock signal of the register J1 is high, and the output Q of the register J1 is equal to D at the previous time, i.e., equal to 1 at this time.
When the clock enable signal EN is at an active level, where the clock enable signal EN is at a high level, that is, the logic value is 1, and when the system clock CLK is at a low level, the Gate enable signal Gate EN output by the latch J3 is also at a high level, and when the Gate enable signal Gate EN is also at a high level, the output of the and Gate is equal to the system clock, that is, the Gate clock gated CLK is equal to the system clock CLK, and then the selector M3 inputs the Gate clock gated CLK as the first clock signal to the clock terminal C of the register J1.
As shown in fig. 10, fig. 10 shows that the gate clock continues to be at the low level when the enable signal is at the low level, and the register J1 cannot be reset as the reset clock of the register J1. On the other hand, in the case where the first clock signal, i.e., the gate clock, is not enabled, the output terminal Q1 of the register J2 is also changed from the low level to the high level at the time of the rising edge of the reset signal changed from the low level to the high level, i.e., the rising edge is also triggered, and the input terminal D of the register J1 is at the low level at the time before the rising edge, and the logic value of the output signal of the register J1 is changed to 0 at the time of the rising edge of the output terminal Q1, i.e., is reset. At the time when the enable signal is at the high level, even in a period in which the enable signal is active, the logic value of the output signal of the register J1 becomes 0, i.e., is reset, at the time of the rising edge of the gate clock. That is, in the period of the 7 th clock of the system clock, the asynchronous reset signal is low, which results in the output of the selector M1 being 0, i.e., the input terminal D of the register J1 being 0, at the position of the rising edge of the 8 th clock of the system clock, the output signal of the register J1 is equal to the value of D at the previous time of the rising edge, i.e., in the period of the 7 th clock of the system clock, i.e., equal to 0, and is thus reset.
Therefore, the synchronous reset timing circuit is enabled to reset according to the second clock signal by using the asynchronous reset signal when the enable signal is not enabled, and as can be seen from the above timing chart, the asynchronous reset timing circuit is reset when the asynchronous reset signal is at a low level, and the synchronous reset timing circuit is reset when the asynchronous reset signal is pulled high, so that the asynchronous reset timing circuit and the synchronous reset timing circuit can be successively reset even when the first clock signal is not enabled.
Referring to fig. 11, a reset method provided by an embodiment of the present application is shown, where the reset method is applied to the clock system, and as an implementation manner, the method is applied to the reset apparatus, and specifically, the method includes: s1101 to S1103.
S1101: and acquiring an asynchronous reset signal when detecting that the system clock circuit does not output the first clock signal.
The asynchronous reset signal is used for executing reset operation on the asynchronous reset sequential circuit, and the first clock signal is used for triggering the synchronous reset circuit to execute reset operation.
As an embodiment, when it is detected that the system clock circuit does not output the first clock signal, the asynchronous reset signal may be obtained by turning off the system clock circuit from the clock signal input terminal, turning on the clock generation circuit from the clock signal input terminal, and obtaining the asynchronous reset signal. When the selection switch detects that the system clock circuit outputs a first clock signal, the system clock circuit is conducted with the clock signal input end, and the clock generation circuit is cut off with the clock signal input end.
S1102: and generating a second clock signal according to the asynchronous reset signal.
Wherein the second clock signal is used for triggering the synchronous reset circuit to execute reset operation.
In one embodiment, the asynchronous reset signal is a signal that alternates between a first level and a second level, the synchronous reset timing circuit is configured to perform a reset operation when a signal input to the clock signal input terminal is a specified level or a level change occurs, the specified level is the first level or the second level, and the second clock signal is generated based on the asynchronous reset signal.
In another embodiment, the asynchronous reset signal is a signal that alternates between a first level and a second level, and the synchronous reset timing circuit is configured to perform a reset operation when a signal input to the clock signal input terminal changes from the first level to the second level. An embodiment of generating the second clock signal according to the asynchronous reset signal may be that, upon detecting that the asynchronous reset signal changes from the second level to the first level, a signal that is maintained at the first level for a first length of time is generated; and generating a signal of a second level within a second time length when the asynchronous reset signal is detected to change from the first level to the second level, wherein the signal which is alternately changed between the first level and the second level and generated by the clock generation circuit is used as a second clock signal.
In some embodiments, the evaluation circuit outputs a first signal when the asynchronous reset signal is at a second level, the first signal being at a first level; when the asynchronous reset signal received by the clock end changes from the second level to the first level, the output signal of the trigger is equal to the first signal, and when the asynchronous reset signal received by the clock end changes from the first level to the second level, the output signal of the trigger is equal to the inverted signal of the first signal.
S1103: and inputting the second clock signal to the clock signal input end to trigger the synchronous reset circuit to execute reset operation.
Referring to fig. 12, a clock system 100 according to an embodiment of the present disclosure is shown, where the clock system may be the SOC described above, or may be other circuit systems using a clock signal. As an embodiment, the clock system may be arranged on at least one chip. As shown in fig. 12, the clock system 100 includes an asynchronous reset timing circuit 320, a synchronous reset timing circuit 330, a system clock circuit 310, and a reset device 400, wherein the system clock circuit 310 is connected to a clock signal input terminal of the synchronous reset circuit 330, and a clock generation circuit is connected to the clock signal input terminal.
Specifically, the above embodiments of the asynchronous reset timing circuit 320, the synchronous reset timing circuit 330, the system clock circuit 310 and the reset device 400 can refer to the foregoing embodiments, and are not repeated herein.
Referring to fig. 13, a block diagram of an electronic device according to an embodiment of the present application is shown. The electronic device 10 may be a smart phone, a tablet computer, an electronic book, or other electronic devices capable of running an application. The electronic device 10 in the present application may include a device body 11 and a clock system 100, the clock system 100 being provided in the device body 11. The device body 11 includes a housing and a main display screen disposed on the housing. The housing may be made of metal, such as steel or aluminum alloy. In this embodiment, the main display usually includes a display panel, and may also include a circuit or the like for performing a touch operation on the display panel in response. In some embodiments, the display panel is a touch screen at the same time. In one embodiment, the clock system 100 is disposed within a housing. Specifically, the main board of the electronic device is located in the housing, and the clock system 100 is disposed on the main board of the electronic device.
Additionally, the electronic device may further include a processor, a memory, and one or more applications, where the one or more applications may be stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the methods as described in the foregoing method embodiments.
A processor may include one or more processing cores. The processor, using various interfaces and lines to connect various parts throughout the electronic device 100, performs various functions of the electronic device 100 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in memory, and calling data stored in memory. Alternatively, the processor may be implemented in at least one hardware form of Digital Signal Processing (DSP), field-programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications. It is to be understood that the modem may be implemented by a communication chip without being integrated into the processor.
The Memory may include a Random Access Memory (RAM) or a Read-only Memory (Read-only Memory). The memory may be used to store an instruction, a program, code, a set of codes, or a set of instructions. The memory may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like. The data storage area may also store data created by the electronic device 100 during use (e.g., phone book, audio-video data, chat log data), and the like.
Referring to fig. 14, a block diagram of a computer-readable storage medium according to an embodiment of the present application is shown. The computer-readable medium 1300 has stored therein program code that can be called by a processor to execute the method described in the above-described method embodiments.
The computer-readable storage medium 1300 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer-readable storage medium 1300 includes a non-volatile computer-readable medium (non-volatile computer-readable storage medium). The computer readable storage medium 1300 has storage space for program code 1310 for performing any of the method steps of the method described above. The program code can be read from or written to one or more computer program products. The program code 1310 may be compressed, for example, in a suitable form.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (11)
1. A reset device, applied to a clock system, where the clock system includes an asynchronous reset sequential circuit, a synchronous reset sequential circuit, and a system clock circuit, the system clock circuit is connected to a clock signal input terminal of the synchronous reset circuit, the system clock circuit is configured to input a first clock signal to the clock signal input terminal, the first clock signal is configured to trigger the synchronous reset circuit to perform a reset operation, and the reset device includes:
a clock generation circuit, an output of the clock generation circuit being connected to the clock signal input, the clock generation circuit being configured to:
when detecting that the system clock circuit does not output a first clock signal, acquiring an asynchronous reset signal, wherein the asynchronous reset signal is used for executing reset operation on the asynchronous reset sequential circuit;
and generating a second clock signal according to the asynchronous reset signal, wherein the second clock signal is used for triggering the synchronous reset circuit to execute reset operation.
2. The apparatus of claim 1, wherein the asynchronous reset signal is a signal that alternates between a first level and a second level, wherein the synchronous reset timing circuit is configured to perform a reset operation when the signal input to the clock signal input terminal is a specified level or a level change occurs, and wherein the specified level is the first level or the second level, and wherein the clock generation circuit is further configured to:
and taking the asynchronous reset signal as the second clock signal.
3. The apparatus of claim 1, wherein the asynchronous reset signal is a signal that alternates between a first level and a second level, wherein the synchronous reset timing circuit is configured to perform a reset operation when the signal input to the clock signal input changes from the first level to the second level, and wherein the clock generation circuit is further configured to:
generating a signal which is kept at a first level for a first time length when the asynchronous reset signal is detected to change from a second level to the first level;
and generating a signal which is kept at the second level for a second time length when the asynchronous reset signal is detected to change from the first level to the second level, wherein the signal which is alternately changed between the first level and the second level and generated by the clock generation circuit is used as a second clock signal.
4. The apparatus of claim 3, wherein the clock generation circuit comprises a flip-flop and an evaluation circuit, a clock terminal of the flip-flop is configured to receive the asynchronous reset signal, an output terminal of the flip-flop is connected to the clock signal input terminal, and the evaluation circuit is connected to an input terminal of the flip-flop, wherein an output terminal of the flip-flop is used as an output terminal of the clock generation circuit;
the assignment circuit is used for outputting a first signal when the asynchronous reset signal is at a second level, wherein the first signal is a signal of a first level;
the flip-flop is used for outputting a signal equal to a first signal when the asynchronous reset signal received by the clock terminal changes from a second level to a first level, and outputting a signal equal to a signal obtained by inverting the first signal when the asynchronous reset signal received by the clock terminal changes from the first level to the second level.
5. The apparatus of claim 4, wherein the evaluation circuit comprises a first selector and an inverter, the first selector comprises a first selection input terminal, a second selection input terminal, a first control terminal and a first selection output terminal, a signal input to the first selection input terminal is at a first level, the output terminal of the flip-flop is connected to the second selection input terminal through the inverter, the first control terminal is configured to receive the asynchronous reset signal, and the first selector is configured to:
when the asynchronous reset signal received by the first control end is at a second level, the output signal of the first selection output end is controlled to be the signal input to the first selection input end, and when the asynchronous reset signal received by the first control end is at a first level, the output signal of the first selection output end is controlled to be the signal input to the second selection input end.
6. The apparatus of claim 4, wherein the flip-flop is a D flip-flop.
7. The apparatus of any of claims 1-6, wherein the resetting means further comprises:
the system clock circuit and the clock generating circuit are both connected with the clock signal input end through the selector switch, and the selector switch is used for:
when detecting that the system clock circuit does not output a first clock signal, cutting off the system clock circuit and the clock signal input end, and conducting the clock generation circuit and the clock signal input end;
when detecting that the system clock circuit outputs a first clock signal, the system clock circuit is conducted with the clock signal input end, and the clock generation circuit is cut off with the clock signal input end.
8. The apparatus of claim 7, wherein the selection switch comprises a second selector, the second selector comprises a third selection input terminal, a fourth selection input terminal, a second control terminal, and a second selection output terminal, the clock generation circuit is connected to the third selection input terminal, the system clock circuit is connected to the fourth selection input terminal, the second selection output terminal is connected to the clock signal input terminal, the second control terminal is configured to receive a clock enable signal, the system clock circuit is configured to output a first clock signal when the clock enable signal is at an active level, and the selector is configured to:
when the clock starting signal received by the second control terminal is at an effective level, controlling the output signal of the second selection output terminal to be the first clock signal input by the system clock circuit to the fourth selection input terminal;
and when the clock starting signal received by the second control terminal is not at an effective level, controlling the output signal of the second selection output terminal to be a second clock signal input by the clock generation circuit to the third selection input terminal.
9. A clock system, comprising: an asynchronous reset sequential circuit, a synchronous reset sequential circuit, a system clock circuit and a reset device as claimed in any one of the preceding claims 1 to 8, wherein the system clock circuit is connected to a clock signal input terminal of the synchronous reset circuit, the system clock circuit is configured to input a first clock signal to the clock signal input terminal, the first clock signal is configured to trigger the synchronous reset circuit to perform a reset operation, and an output terminal of the clock generation circuit is connected to the clock signal input terminal.
10. An electronic device comprising a device body and the clock system of claim 9, the clock system being disposed within the device body.
11. A reset method applied to a clock system, the clock system including an asynchronous reset timing circuit, a synchronous reset timing circuit, and a system clock circuit, the system clock circuit being connected to a clock signal input terminal of the synchronous reset circuit, the system clock circuit being configured to input a first clock signal to the clock signal input terminal, the first clock signal being configured to trigger the synchronous reset circuit to perform a reset operation, the method comprising:
when detecting that the system clock circuit does not output a first clock signal, acquiring an asynchronous reset signal, wherein the asynchronous reset signal is used for executing reset operation on the asynchronous reset sequential circuit;
generating a second clock signal according to the asynchronous reset signal;
and inputting the second clock signal to the clock signal input end to trigger the synchronous reset circuit to execute reset operation.
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