CN112165320A - Low-power-consumption digital power-on reset circuit and integrated circuit chip - Google Patents
Low-power-consumption digital power-on reset circuit and integrated circuit chip Download PDFInfo
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- CN112165320A CN112165320A CN202011043444.5A CN202011043444A CN112165320A CN 112165320 A CN112165320 A CN 112165320A CN 202011043444 A CN202011043444 A CN 202011043444A CN 112165320 A CN112165320 A CN 112165320A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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Abstract
The invention relates to the technical field of integrated circuits, in particular to a low-power-consumption digital power-on reset circuit, which comprises: the power-on trigger unit is used for generating a starting trigger signal; the input end of the signal delay unit is connected with the output end of the power-on trigger unit and is used for receiving the starting trigger signal and carrying out time delay processing on the starting trigger signal so as to output a delay signal; the first input end of the latch unit is connected with the output end of the power-on trigger unit, the second input end of the latch unit is connected with the output end of the signal delay unit, the latch unit receives the delay signal for processing and forming a reset trigger signal, and the latch unit outputs the reset signal according to the reset trigger signal. Has the advantages that: the digital power-on reset circuit has a simple structure, does not need modules such as analog sampling, analog comparison and the like in the traditional reset circuit, simplifies the circuit structure and reduces errors caused by process deviation; in addition, the power consumption of the circuit is reduced because the power consumption of the analog module is not available.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-power-consumption digital power-on reset circuit and an integrated circuit chip.
Background
With the rapid development of integrated circuit technology, the requirements of the integrated circuit on working power consumption, standby power consumption and sleep power consumption are higher and higher. The sleep low power design is particularly important because the chip will go to sleep after completing the instruction work. The reset circuit in the prior art is designed to realize a reset function in an analog manner, and fig. 1 and 2 show the reset circuit in the prior art, which not only has a complex circuit, but also has high power consumption and large process deviation. Fig. 1 shows a conventional reset circuit, which has a complex circuit architecture, needs analog modules such as a comparator, a clock, a Bias, and the like, and has a high production cost; the circuit in fig. 2 realizes power supply detection in an analog manner, and the circuit has a high power consumption, is greatly influenced by process variation, and brings large errors due to process deviation.
Disclosure of Invention
In view of the above problems in the prior art, a digital power-on reset circuit and an integrated circuit chip with low power consumption are provided.
The specific technical scheme is as follows:
the invention includes a low power consumption digital power-on reset circuit, comprising:
the power-on trigger unit is used for generating a starting trigger signal;
the input end of the signal delay unit is connected with the output end of the power-on trigger unit and is used for receiving the starting trigger signal and carrying out time delay processing on the starting trigger signal so as to output a delay signal;
the first input end of the latch unit is connected with the output end of the power-on trigger unit and used for receiving the starting trigger signal to reset the latch unit;
the second input end of the latch unit is connected with the output end of the signal delay unit, the latch unit processes the delay signal after receiving the delay signal and forms a reset trigger signal, and the latch unit outputs a reset signal according to the reset trigger signal.
Preferably, the power-on trigger unit includes a first enable buffer, a second enable buffer, a first nor gate, and a second nor gate.
Preferably, a first input terminal of the first nor gate is connected to an output terminal of the first enable buffer, a second input terminal of the first nor gate is connected to an output terminal of the second nor gate, and an output terminal of the first nor gate is connected to an input terminal of the signal delay unit;
the first input end of the second nor gate is connected between the output end of the first nor gate and the input end of the signal delay unit, and the second input end of the second nor gate is connected with the output end of the second enable buffer.
Preferably, the signal delay unit includes a plurality of delay buffers connected in series.
Preferably, the circuit comprises a first flip-flop, a second flip-flop, a not gate and a nand gate;
a first input end of the latch unit is respectively connected with a reset end of the first trigger and a reset end of the second trigger;
a second input end of the latch unit is respectively connected with a clock end of the first flip-flop and a clock end of the second flip-flop, wherein the not gate is arranged between the second input end of the latch unit and the clock end of the first flip-flop;
the first input end of the NAND gate is connected with the output end of the first trigger, the second input end of the NAND gate is connected with the output end of the second trigger, and the output end of the NAND gate is used as the output end of the latch unit.
Preferably, the power supply system further comprises a voltage detection unit connected to an input end of the power-on trigger unit, and configured to detect a power supply voltage in real time and transmit the power supply voltage to the power-on trigger unit, and the power-on trigger unit generates the start trigger signal according to a potential level of the power supply voltage.
Preferably, the power-on trigger unit is an RS trigger.
The invention also comprises an integrated circuit chip comprising the digital power-on reset circuit in any of the above technical schemes.
The technical scheme of the invention has the following advantages or beneficial effects: the digital power-on reset circuit has a simple structure, does not need modules such as analog sampling, analog comparison and the like in the traditional reset circuit, simplifies the circuit structure, reduces errors caused by process deviation, is easy to realize and has lower production cost; in addition, because the power consumption of the analog module is not provided, the module power consumption is basically the leakage power consumption of the logic circuit, and the power consumption of the circuit is reduced.
Drawings
Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.
Fig. 1 is a schematic structural diagram of a first reset circuit in the prior art;
FIG. 2 is a diagram illustrating a second reset circuit in the prior art;
FIG. 3 is a functional block diagram of a digital power-on reset circuit in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a power-on trigger unit in the embodiment of the present invention;
FIG. 5 is a schematic diagram of a delay unit according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating a latch unit according to an embodiment of the present invention;
fig. 7 is a reset timing diagram of the power-on reset circuit in the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
The present invention includes a low power consumption digital power-on reset circuit, as shown in fig. 3, including:
the power-on trigger unit 1 is used for generating a starting trigger signal;
the input end of the signal delay unit 2 is connected with the output end of the power-on trigger unit 1, and is used for receiving the starting trigger signal and carrying out time delay processing on the starting trigger signal so as to output a delay signal;
the first input end of the latch unit 3 is connected with the output end of the power-on trigger unit 1 and is used for receiving a starting trigger signal to reset the latch unit 3;
the second input end of the latch unit 3 is connected with the output end of the signal delay unit 2, the latch unit 3 processes and forms a reset trigger signal after receiving the delay signal, and the latch unit outputs a reset signal according to the reset trigger signal.
Specifically, in this embodiment, fig. 3 is a schematic block diagram of a digital power-on reset circuit provided by the present invention, and mainly includes three parts, namely, a power-on trigger unit 1, a signal delay unit 2, and a latch unit 3. When the circuit is powered on, the power-on trigger unit 1 generates a start trigger signal, the start trigger signal enters the latch unit 3 to reset the latch unit, and the latch unit 3 in the embodiment is a latch; in addition, the signal delay unit 2 delays the start trigger signal for a period of time, and the delayed start trigger signal resets the latch twice in the latch, thereby implementing a reset function.
Specifically, according to the technical scheme, the working principle of the power-on reset circuit in the present invention is as shown in fig. 7, when a power supply is powered on, a reset signal and a power supply voltage are pulled up together, a start trigger signal output by a power-on trigger unit 1 is pulled up and passes through a delay unit 2, the delay unit 2 can generate a delay with a length of Tdelay, after the start trigger signal is pulled up, a delay signal output by the delay unit 2 is pulled up and latched by a delay passing unit 3 to generate a reset trigger signal, and the reset signal is pulled down.
In a preferred embodiment, as shown in fig. 4, the power-up trigger unit 1 includes a first enable register 101, a second enable register 102, a first nor gate 103, and a second nor gate 104. A first input end of the first nor gate 103 is connected with an output end of the first enable buffer 101, a second input end of the first nor gate 103 is connected with an output end of the second nor gate 104, and an output end of the first nor gate 103 is connected with an input end of the signal delay unit 2; a first input terminal of the second nor gate 104 is connected between the output terminal of the first nor gate 103 and the input terminal of the signal delay unit 2, and a second input terminal of the second nor gate 104 is connected to the output terminal of the second enable buffer 102. The first enable buffer 101, the second enable buffer 102, the first nor gate 103, and the second nor gate 104 form an RS flip-flop, which includes two nor gates cross-coupled, and is a high-level flip-flop: the R end is connected with 0, and the S end is connected with 0, the output is unchanged; the R end is connected with 1, and the S end is connected with 0, so that the output is 0; the R end is connected with 0, and the S end is connected with 1, so that the output is 1; and if the R end is 1 and the S end is 1, the output is uncertain.
In a preferred embodiment, as shown in fig. 5, the signal delay unit 2 comprises a plurality of delay buffers connected in series. The larger the number of delay buffers, the longer the delay, and therefore the number of delay buffers is designed according to the delay time required by the integrated circuit.
In a preferred embodiment, as shown in fig. 6, the latch unit 3 comprises a first flip-flop 301, a second flip-flop 302, a not-gate 303 and a nand-gate 304;
a first input end of the latch unit 3 is respectively connected with a reset end of the first flip-flop 301 and a reset end of the second flip-flop 302;
a second input end of the latch unit 3 is connected to the clock end of the first flip-flop 301 and the clock end of the second flip-flop 302, respectively, wherein the not gate 303 is disposed between the second input end of the latch unit 3 and the clock end of the first flip-flop 301;
a first input end of the nand gate 304 is connected to the output end of the first flip-flop 301, a second input end of the nand gate 304 is connected to the output end of the second flip-flop 302, and an output end of the nand gate 304 serves as an output end of the latch unit 3.
Specifically, in the present embodiment, the first flip-flop 301 and the second flip-flop 302 are two D flip-flops with reset triggered by rising edges. The latch unit 3 is reset after power-on triggering, latches the reset time after the delay signal of the delay unit 2 is completed, and then feeds back a signal to turn off the delay unit.
In a preferred embodiment, the power supply system further comprises a voltage detection unit connected to an input end of the power-on trigger unit, and configured to detect the power supply voltage in real time and transmit the power supply voltage to the power-on trigger unit, and the power-on trigger unit generates the start trigger signal according to a potential level of the power supply voltage.
The invention also provides an integrated circuit chip comprising the digital power-on reset circuit in any of the above embodiments. When the circuit is powered on, the power-on trigger unit 1 generates a start trigger signal, the start trigger signal enters the latch unit 3 to reset the latch unit, and the latch unit 3 in the embodiment is a latch; in addition, the signal delay unit 2 delays the start trigger signal for a period of time, and the delayed start trigger signal resets the latch twice in the latch, thereby implementing a reset function. The integrated circuit chip in the embodiment adopts the digital power-on reset circuit with a simpler structure, so that the production cost of the integrated circuit chip is reduced, and the power consumption of the integrated circuit chip is reduced.
The embodiment of the invention has the beneficial effects that: the digital power-on reset circuit has a simple structure, does not need modules such as analog sampling, analog comparison and the like in the traditional reset circuit, simplifies the circuit structure, reduces errors caused by process deviation, is easy to realize and has lower production cost; in addition, because the power consumption of the analog module is not provided, the module power consumption is basically the leakage power consumption of the logic circuit, and the power consumption of the circuit is reduced.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (8)
1. A low power digital power-on-reset circuit, comprising:
the power-on trigger unit is used for generating a starting trigger signal;
the input end of the signal delay unit is connected with the output end of the power-on trigger unit and is used for receiving the starting trigger signal and carrying out time delay processing on the starting trigger signal so as to output a delay signal;
the first input end of the latch unit is connected with the output end of the power-on trigger unit and used for receiving the starting trigger signal to reset the latch unit;
the second input end of the latch unit is connected with the output end of the signal delay unit, the latch unit processes the delay signal after receiving the delay signal and forms a reset trigger signal, and the latch unit outputs a reset signal according to the reset trigger signal.
2. The digital power-on reset circuit of claim 1, wherein the power-on trigger unit comprises a first enable buffer, a second enable buffer, a first nor gate, and a second nor gate.
3. The digital power-on reset circuit according to claim 2, wherein a first input terminal of the first nor gate is connected to an output terminal of the first enable buffer, a second input terminal of the first nor gate is connected to an output terminal of the second nor gate, and an output terminal of the first nor gate is connected to an input terminal of the signal delay unit;
the first input end of the second nor gate is connected between the output end of the first nor gate and the input end of the signal delay unit, and the second input end of the second nor gate is connected with the output end of the second enable buffer.
4. The digital power-on-reset circuit of claim 1, wherein the signal delay unit comprises a plurality of delay buffers connected in series.
5. The digital power-on reset circuit of claim 1, wherein the latch unit comprises a first flip-flop, a second flip-flop, a not-gate and a nand-gate;
a first input end of the latch unit is respectively connected with a reset end of the first trigger and a reset end of the second trigger;
a second input end of the latch unit is respectively connected with a clock end of the first flip-flop and a clock end of the second flip-flop, wherein the not gate is arranged between the second input end of the latch unit and the clock end of the first flip-flop;
the first input end of the NAND gate is connected with the output end of the first trigger, the second input end of the NAND gate is connected with the output end of the second trigger, and the output end of the NAND gate is used as the output end of the latch unit.
6. The digital power-on reset circuit of claim 1, further comprising a voltage detection unit connected to an input terminal of the power-on trigger unit, for detecting a power voltage in real time and transmitting the power voltage to the power-on trigger unit, wherein the power-on trigger unit generates the start trigger signal according to a potential level of the power voltage.
7. The digital power-on-reset circuit of claim 1, wherein the power-on trigger unit is an RS flip-flop.
8. An integrated circuit chip comprising the digital power-on-reset circuit as claimed in any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011043444.5A CN112165320A (en) | 2020-09-28 | 2020-09-28 | Low-power-consumption digital power-on reset circuit and integrated circuit chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011043444.5A CN112165320A (en) | 2020-09-28 | 2020-09-28 | Low-power-consumption digital power-on reset circuit and integrated circuit chip |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055449A (en) * | 2010-12-29 | 2011-05-11 | 西安华芯半导体有限公司 | Low power-consumption time-delay controllable POR (power on reset) method and circuit |
| CN102497181A (en) * | 2011-12-22 | 2012-06-13 | 中国科学院上海微系统与信息技术研究所 | Ultra-low power consumption power-on reset circuit |
| CN108279760A (en) * | 2018-02-28 | 2018-07-13 | 上海顺久电子科技有限公司 | A kind of power on detection circuit, chip and wearable device |
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2020
- 2020-09-28 CN CN202011043444.5A patent/CN112165320A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055449A (en) * | 2010-12-29 | 2011-05-11 | 西安华芯半导体有限公司 | Low power-consumption time-delay controllable POR (power on reset) method and circuit |
| CN102497181A (en) * | 2011-12-22 | 2012-06-13 | 中国科学院上海微系统与信息技术研究所 | Ultra-low power consumption power-on reset circuit |
| CN108279760A (en) * | 2018-02-28 | 2018-07-13 | 上海顺久电子科技有限公司 | A kind of power on detection circuit, chip and wearable device |
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