CN112104369A - Low-power-consumption analog-to-digital converter and control method thereof - Google Patents
Low-power-consumption analog-to-digital converter and control method thereof Download PDFInfo
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Abstract
The invention discloses a low-power consumption analog-to-digital converter and a control method thereof, wherein the low-power consumption analog-to-digital converter comprises a capacitor array digital-to-analog converter and a comparator; the capacitor array digital-to-analog converter comprises an upper capacitor array and a lower capacitor array; the upper capacitor array comprises (N-2) upper capacitor groups and a first starting capacitor, and the lower capacitor array comprises (N-2) lower capacitor groups and a second starting capacitor; the upper plate of the upper capacitor is connected to a reference voltage or ground, and the upper plate of the lower capacitor is connected to a reference voltage or ground. According to the invention, the upper capacitor array and the lower capacitor array are both connected to the reference voltage or both connected to the ground, and further, when the comparator is used for comparison, the capacitance of the capacitor array digital-to-analog converter is only distributed in the capacitor array digital-to-analog converter, so that charges flow in the capacitor array digital-to-analog converter, and the purpose of reducing the power loss of the low-power consumption analog-to-digital converter is realized. The invention can be widely applied to the technical field of electronic circuits.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a low-power-consumption analog-to-digital converter and a control method thereof.
Background
The successive approximation type analog-to-digital converter is an analog-to-digital converter structure with high precision, medium conversion rate and low power consumption, and mainly comprises an analog-to-digital converter, a comparator and a successive approximation register, wherein the structure of the analog-to-digital converter is usually realized by adopting two groups of symmetrical capacitor arrays, each group of capacitor array needs to be selected and connected to reference voltages with different amplitudes, in the process of realizing the successive approximation comparison of input signals, the reference voltages of the two groups of capacitor arrays need to be repeatedly switched for many times, and in the process of repeatedly switching the reference voltages, because the reference voltages connected by the two groups of capacitor arrays are inconsistent, charges can be distributed and flow between the two groups of capacitor arrays, so that the energy consumption is caused.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a low power consumption analog-to-digital converter and a control method thereof.
In a first aspect, an embodiment of the present invention provides a low power consumption analog-to-digital converter, including a capacitor array digital-to-analog converter and a comparator;
the capacitor array digital-to-analog converter comprises an upper capacitor array and a lower capacitor array;
the upper capacitor array comprises (N-2) upper capacitor groups and a first starting capacitor, the capacitance value of the first starting capacitor is C, the ith upper capacitor group comprises (N-1-i) upper capacitors, the capacitance value of the 1 st upper capacitor is 2C, and the capacitance value of the jth upper capacitor is 2j-1C, wherein N is the digit of the low-power-consumption analog-to-digital converter, N is more than or equal to 3, i is more than or equal to 1 and less than or equal to N-2, j is more than or equal to 2 and less than or equal to N-1-i, C represents a unit capacitor, and i and j are natural numbers;
the lower capacitor array comprises (N-2) lower capacitor groups and a second initial capacitor, the capacitance value of the second initial capacitor is C, the ith lower capacitor group comprises (N-1-i) upper capacitors, the capacitance value of the 1 st upper capacitor is 2C, and the jth upper capacitorHas a capacitance value of 2j-1C, wherein i is more than or equal to 1 and less than or equal to N-2, and j is more than or equal to 2 and less than or equal to N-1-i;
the upper plate of the upper capacitor is connected to a reference voltage or ground, the upper plate of the lower capacitor is connected to the reference voltage or ground, the upper plate of the first starting capacitor is connected to the reference voltage or ground, and the upper plate of the second starting capacitor is connected to the reference voltage or ground;
the lower pole plate of the upper capacitor is connected with the lower pole plate of the lower capacitor to form the input end of the capacitor array digital-to-analog converter, the lower pole plate of the first starting capacitor is connected with the lower pole plate of the second starting capacitor to form the output end of the capacitor array digital-to-analog converter, the input end of the capacitor array digital-to-analog converter is connected with the output end of the capacitor array digital-to-analog converter, the output end of the capacitor array digital-to-analog converter is further connected to the in-phase input end of the comparator, and the reverse phase input end of the comparator is connected to.
Furthermore, the low-power consumption analog-to-digital converter further comprises a sampling switch, one end of the sampling switch is connected with an input signal, and the other end of the sampling switch is connected with the input end of the capacitor array digital-to-analog converter.
Further, the upper capacitor array comprises a first selection switch and a plurality of first switches;
one end of the first switch is connected with the upper pole plate of the upper capacitor, the other end of the first switch is connected with the first end of the first selection switch, the second end of the first selection switch is connected with a reference voltage, and the third end of the first selection switch is connected with the ground.
Further, the lower capacitor array also comprises a second selection switch and a plurality of second switches;
one end of the second switch is connected to the upper pole plate of the lower capacitor, the other end of the second switch is connected to the first end of the selection switch, the second end of the second selection switch is connected to a reference voltage, and the third end of the second selection switch is connected to the ground.
In a second aspect, the present application provides a control method applied to the above low power consumption analog-to-digital converter, including the following steps:
A. sampling: controlling the upper plate of the upper capacitor to be connected to the ground and controlling the upper plate of the lower capacitor to be connected to a reference voltage;
an input signal enters the capacitor array digital-to-analog converter from the input end of the capacitor array digital-to-analog converter, an in-phase holding signal is obtained at the output end of the capacitor array digital-to-analog converter, and the first switches and the second switches are controlled to be switched off;
B. comparison 1: the comparator compares the in-phase holding signal with the ground for the first time and outputs a first comparison result D (1);
C. comparison at the 2 nd time: according to the result of the first comparison D (1),
when D (1) =1, controlling the second selection switch to be connected to the ground;
when D (1) =0, controlling a first selection switch to be connected to the reference voltage;
the comparator performs the 2 nd comparison and outputs a 2 nd comparison result D (2);
the k comparison: according to the k-1 comparison result D (k-1), wherein k is more than or equal to 3 and less than or equal to N-1 is taken as a constraint condition,
when D (k-1) =1, controlling the second switches of the lower capacitors in the 1 st to (k-2) th lower capacitor groups to be turned on;
when D (k-1) =0, controlling the first switch of the upper capacitor in the 1 st to (k-2) th upper capacitor groups to be turned on;
the comparator carries out the kth comparison and outputs the kth comparison result D (k);
E. and k is increased by 1, step D is executed, the constraint condition is determined to be not satisfied, and the step D is finished.
Further, the step D specifically includes:
when D (k-1) =1, controlling a first switch of a (k-1-i) th lower capacitor in the ith lower capacitor group to be turned on;
and when D (k-1) =0, controlling the first switch of the (k-1-i) th upper capacitor in the ith upper capacitor group to be switched on, wherein i is more than or equal to 1 and less than or equal to k-2.
The invention has the beneficial effects that:
the upper capacitor array and the lower capacitor array can be selectively connected to the reference voltage or the ground, so that the upper capacitor array and the lower capacitor array are both connected to the reference voltage or the ground, and the capacitance of the capacitor array digital-to-analog converter is only distributed in the capacitor array digital-to-analog converter when the comparator compares, so that the charge flows in the capacitor array digital-to-analog converter, and the purpose of reducing the power loss of the low-power consumption analog-to-digital converter is achieved.
Drawings
FIG. 1 is a schematic circuit diagram of a low power consumption analog-to-digital converter according to an embodiment of the present invention;
FIG. 2 is a sampling schematic diagram of a 4-bit low power analog-to-digital converter according to an embodiment of the present invention;
FIG. 3 is a first comparison diagram of a 4-bit low power analog-to-digital converter according to an embodiment of the present invention;
FIG. 4 is a second comparison diagram of a 4-bit low power analog-to-digital converter according to an embodiment of the present invention;
fig. 5 is a schematic diagram comparing a third time and a fourth time of a 4-bit low-power consumption analog-to-digital converter according to an embodiment of the invention.
Detailed Description
Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.
In the present invention, if directions (up, down, left, right, front, and rear) are described, it is only for convenience of describing the technical solution of the present invention, and it is not intended or implied that the technical features referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, it is not to be construed as limiting the present invention.
In the invention, the meaning of "a plurality" is one or more, the meaning of "a plurality" is more than two, and the terms of "more than", "less than", "more than" and the like are understood to exclude the number; the terms "above", "below", "within" and the like are understood to include the instant numbers. In the description of the present invention, if there is description of "first" and "second" only for the purpose of distinguishing technical features, it is not to be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the precedence of the indicated technical features.
In the present invention, unless otherwise specifically limited, the terms "disposed," "mounted," "connected," and the like are to be understood in a broad sense, and for example, may be directly connected or indirectly connected through an intermediate; can be fixedly connected, can also be detachably connected and can also be integrally formed; may be mechanically coupled, may be electrically coupled or may be capable of communicating with each other; either as communication within the two elements or as an interactive relationship of the two elements. The specific meaning of the above-mentioned words in the present invention can be reasonably determined by those skilled in the art in combination with the detailed contents of the technical solutions.
The invention will be further explained and explained with reference to the drawings and the embodiments in the description.
Referring to fig. 1, an embodiment of the present invention provides a low power consumption analog-to-digital converter, including a capacitor array digital-to-analog converter and a comparator;
the capacitor array digital-to-analog converter comprises an upper capacitor array and a lower capacitor array;
the upper capacitor array comprises (N-2) upper capacitor groups and a first starting capacitor C1First starting capacitance C1The capacitance value of (1) th upper capacitor group comprises (N-1-i) upper capacitors, the capacitance value of the 1 st upper capacitor is 2C, and the capacitance value of the jth upper capacitor is 2j-1C, wherein N is the digit of the low-power-consumption analog-to-digital converter, N is more than or equal to 3, i is more than or equal to 1 and less than or equal to N-2, j is more than or equal to 2 and less than or equal to N-1-i, C represents a unit capacitor, and i and j are natural numbers;
the lower capacitor array comprises (N-2) lower capacitor groups and a second initial capacitor C2Second initial capacitance C2Has a capacitance value of C, the ith lower capacitor groupComprises (N-1-i) upper capacitors, wherein the capacitance value of the 1 st upper capacitor is C, and the capacitance value of the jth upper capacitor is 2j-1C, wherein i is more than or equal to 1 and less than or equal to N-2, j is more than or equal to 2 and less than or equal to N-1-i, i is more than or equal to 1 and less than or equal to N-2, and j is more than or equal to 2 and less than or equal to N-1-i;
it should be noted that, when the value of N is 3, the upper capacitor array only includes 1 upper capacitor group, that is, the 1 st upper capacitor group, and the capacitance value of the 1 st upper capacitor (i is 1) of the 1 st upper capacitor group is 2C, because the value range of j is not established when the value of N is 3 and the value of i is 1, the capacitance value of the jth upper capacitor in the 1 st upper capacitor group cannot be calculated, and actually, the 1 st upper capacitor group only includes 1 upper capacitor, and the capacitance values of other upper capacitors except the 1 st upper capacitor cannot be calculated.
When the value of N is greater than 3, for example, when the value of N is 4, the upper capacitor array includes 2 upper capacitor groups and a first start capacitor C1First starting capacitance C1The capacitance value of (1) is C, the capacitance value of (1) the first upper capacitor group includes 2 upper capacitors, the capacitance value of (1) the first upper capacitor is 2C, the capacitance value of (2) the second upper capacitor is 2C (N is 4, i is 1, j is 2), the capacitance value of (2) the second upper capacitor group includes (1) the capacitance value of (1) the first upper capacitor is 2C (N is 4, i is 2, j is not true, so the capacitance value of (j) the first upper capacitor cannot be calculated).
In the same manner as described above, the capacitance value of the upper capacitor in the upper capacitor array in the N-bit analog-to-digital low-power analog-to-digital converter is calculated.
Similarly, the capacitance value of the lower capacitor in the lower capacitor array is calculated according to the manner of calculating the capacitance value of the upper capacitor in the upper capacitor array in the N-bit analog-to-digital low-power analog-to-digital converter, which is not described herein again.
The upper plate of the upper capacitor is connected to a reference voltageV refOr ground gnd, the upper plate of the lower capacitor being connected to a reference voltageV refOr ground gnd, first starting capacitance C1Is connected to a reference voltageV refOr ground gnd, a second starting capacitance C2Is connected to a reference voltageV refOr gnd;
the lower plate of the upper capacitor is connected with the lower plate of the lower capacitor to form the input end of the capacitor array digital-to-analog converter, and the first starting capacitor C1The lower pole plate is connected with a second initial capacitor C2The lower electrode plate of the capacitor array digital-to-analog converter forms the output end of the capacitor array digital-to-analog converter, the input end of the capacitor array digital-to-analog converter is connected with the output end of the capacitor array digital-to-analog converter, the output end of the capacitor array digital-to-analog converter is also connected to the non-inverting input end of the comparator, and the inverting input end of the comparator is connected to ground gnd.
Specifically, in the present embodiment, the upper capacitor array is selectively connected to the reference voltageV refOr gnd, having the lower capacitor array selectively connected to the reference voltageV refOr gnd, such that both the upper and lower capacitor arrays are connected to a reference voltageV refThe capacitors are all connected to the ground gnd, and when the comparator compares, the capacitance of the capacitor array digital-to-analog converter is only distributed in the capacitor array digital-to-analog converter, so that charges flow in the capacitor array digital-to-analog converter, and the purpose of reducing the power loss of the low-power-consumption analog-to-digital converter is achieved.
Further as an optional implementation, the low power consumption analog-to-digital converter further includes a sampling switch S3, and one end of the sampling switch S3 is connected to the input signalV inAnd the other end of the sampling switch S3 is connected with the input end of the capacitor array digital-to-analog converter.
Specifically, the application is also provided with a sampling switch S3, and the input signal is controlled by the sampling switch S3V inWhen inputting a signalV inInputting into the capacitor array D/A converter, turning off the sampling switch S3, inputting signalV inThe in-phase holding signal can be obtained at the output end of the capacitor array digital-to-analog converter through the capacitor array digital-to-analog converter, and the in-phase holding signal can enter the positive phase input end of the comparator.
As a further alternative embodiment, the upper capacitor array includes a first selection switch S1 and a plurality of first switches;
one end of the first switch is connected with the upper pole plate of the upper capacitor, and the other end of the first switch is connected with the first selectorA first terminal of a selection switch S1, a second terminal of the first selection switch S1 connected to a reference voltageV refThe third terminal of the first selector switch S1 is connected to ground gnd.
Specifically, the present embodiment provides a method for connecting the upper capacitor to the reference voltageV refOr ground gnd, the reference voltage is controlled by a first selection switch S1V refOr the ground gnd, since the first switch connects the first selection switch S1 and the upper capacitor, the reference voltage can be flexibly switched by controlling the on and off states of the first switchV refOr ground gnd, into the upper plate of the upper capacitor.
As a further optional implementation, the lower capacitor array further includes a second selection switch S2 and a plurality of second switches;
one end of the second switch is connected to the upper plate of the lower capacitor, the other end of the second switch is connected to the first end of the selection switch, and the second end of the second selection switch S2 is connected to the reference voltageV refAnd the third terminal of the second selector switch S2 is connected to ground gnd.
Specifically, the present embodiment provides a method for connecting a lower capacitor to a reference voltageV refOr ground gnd, and the upper capacitor connected to the reference voltage in the previous embodimentV refOr the working principle of gnd is the same, and the description is omitted here.
For the low-power consumption analog-to-digital converter, the scheme also provides a control method for controlling the low-power consumption analog-to-digital converter, which comprises the following steps:
A. sampling: the upper plate of the upper capacitor is controlled to be connected to ground gnd, and the upper plate of the lower capacitor is controlled to be connected to a reference voltageV ref；
Input signalV inThe control method comprises the steps that the signals enter a capacitor array digital-to-analog converter from the input end of the capacitor array digital-to-analog converter, in-phase maintaining signals are obtained at the output end of the capacitor array digital-to-analog converter, a plurality of first switches are controlled to be switched off, and a plurality of second switches are controlled to be switched off;
B. comparison 1: the comparator compares the in-phase holding signal with the ground gnd for the first time and outputs a first comparison result D (1);
C. comparison at the 2 nd time: on the basis of the first comparison result D (1),
when D (1) =1, the second selection switch S2 is controlled to be connected to ground gnd, so that the voltage of the upper capacitor array connection and the voltage of the lower capacitor array connection are the same, that is, both are ground gnd;
when D (1) =0, the first selection switch S1 is controlled to be connected to the reference voltageV refSo that the voltages connected with the upper capacitor array and the lower capacitor array are the same, namely, the voltages are reference voltagesV ref；
The comparator carries out the 2 nd comparison and outputs a 2 nd comparison result D (2);
the k comparison: according to the k-1 comparison result D (k-1), wherein k is more than or equal to 3 and less than or equal to N-1 is taken as a constraint condition,
when D (k-1) =1, controlling the second switches of the lower capacitors in the 1 st to (k-2) th lower capacitor groups to be turned on;
when D (k-1) =0, controlling the first switch of the upper capacitor in the 1 st upper capacitor group to the (k-2) th upper capacitor group to be turned on;
the comparator carries out the kth comparison and outputs the kth comparison result D (k);
E. and k is increased by 1, step D is executed, the constraint condition is determined to be not satisfied, and the step D is finished.
As can be seen from the above embodiments, in the present application, when the comparator performs the 2 nd comparison, the voltage of the upper capacitor array and the voltage of the lower capacitor array are adjusted to be the same according to the comparison result D (1) of the first comparison, that is, the upper capacitor array and the lower capacitor array are both connected to ground gnd or both connected to the reference voltageV refAnd the subsequent voltage device is compared, the first switch or the second switch is closed, the capacitance of the capacitor in the capacitor array digital-to-analog converter is only distributed in the capacitor array digital-to-analog converter, so that the charge flows in the capacitor array digital-to-analog converter, and the aim of reducing the power loss of the low-power consumption analog-to-digital converter is fulfilled.
As a further optional implementation manner, step D specifically includes:
when D (k-1) =1, controlling a first switch of a (k-1-i) th lower capacitor in an ith lower capacitor group to be turned on;
and when D (k-1) =0, controlling the first switch of the (k-1-i) th upper capacitor in the ith upper capacitor group to be switched on, wherein k is more than or equal to 3 and less than or equal to N, and i is more than or equal to 1 and less than or equal to k-2.
Specifically, this embodiment provides a specific implementation manner for switching the first switch and the second switch, and when the kth comparison is performed, if the (k-1) th comparison result D (k-1) is 1, the lower capacitors of the (N-k) th lower capacitor bank sequentially turn on the second switch after the kth to (N-1) th comparisons; and if the (k-1) th comparison result D (k-1) is 0, sequentially switching on the first switch after the upper capacitors of the (N-k) th upper capacitor group are compared from the kth time to the N-1 th time, and outputting the comparison result by the comparator after the first switch or the second switch is adjusted every time.
Referring to fig. 2 to 5, the present application provides a control method of a 4-bit low-power consumption analog-to-digital converter to more clearly illustrate the implementation principle of the present application.
Referring to fig. 2, sampling: the upper plate of the upper capacitor is controlled to be connected to ground gnd, and the upper plate of the lower capacitor is controlled to be connected to a reference voltageV ref；
Input signalV inThe control method comprises the steps that the signals enter a capacitor array digital-to-analog converter from the input end of the capacitor array digital-to-analog converter, in-phase maintaining signals are obtained at the output end of the capacitor array digital-to-analog converter, a plurality of first switches are controlled to be switched off, and a plurality of second switches are controlled to be switched off;
referring to fig. 3, comparison 1: the comparator compares the in-phase holding signal with the ground gnd for the first time and outputs a first comparison result D (1);
referring to fig. 4, comparison 2: on the basis of the first comparison result D (1),
when D (1) =1, the second selection switch S2 is controlled to be connected to ground gnd, so that the voltage of the upper capacitor array connection and the voltage of the lower capacitor array connection are the same and are both ground gnd;
when D (1) =0, the first selection switch S1 is controlled to be connected to the reference voltageV refTherefore, the voltages connected with the upper capacitor array and the lower capacitor array are the same and are reference voltagesV ref；
The comparator carries out the 2 nd comparison and outputs a 2 nd comparison result D (2);
referring to fig. 5, comparison 3: according to the 2 nd comparison result D (2),
when D (2) =1, controlling a first switch of a 1 st lower capacitor in a 1 st lower capacitor group to be turned on;
when D (2) =0, controlling a first switch of a 1 st upper capacitor in a 1 st upper capacitor group to be turned on;
wherein k =3, i = 1;
referring to fig. 5, comparison 4: according to the 3 rd comparison result D (3),
when D (3) =1, controlling a first switch of a 2 nd lower capacitor in a 1 st lower capacitor group to be turned on; controlling the first switch of the 1 st lower capacitor in the 2 nd lower capacitor group to be conducted;
when D (3) =0, controlling a first switch of a 2 nd upper capacitor in a 1 st upper capacitor group to be conductive; a first switch for controlling the 1 st upper capacitor in the 2 nd upper capacitor group;
wherein k =4, i is more than or equal to 1 and less than or equal to 2.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. A low-power consumption analog-to-digital converter is characterized by comprising a capacitor array digital-to-analog converter and a comparator;
the capacitor array digital-to-analog converter comprises an upper capacitor array and a lower capacitor array;
the upper capacitor array comprises (N-2) upper capacitor groups and a first starting capacitor, the capacitance value of the first starting capacitor is C, the ith upper capacitor group comprises (N-1-i) upper capacitors, the capacitance value of the 1 st upper capacitor is 2C, and the capacitance value of the jth upper capacitor is 2C2j-1C, wherein N is the digit of the low-power-consumption analog-to-digital converter, N is more than or equal to 3, i is more than or equal to 1 and less than or equal to N-2, j is more than or equal to 2 and less than or equal to N-1-i, C represents a unit capacitor, and i and j are natural numbers;
the lower capacitor array comprises (N-2) lower capacitor groups and a second initial capacitor, the capacitance value of the second initial capacitor is C, the ith lower capacitor group comprises (N-1-i) upper capacitors, the capacitance value of the 1 st upper capacitor is 2C, and the capacitance value of the jth upper capacitor is 2j-1C, wherein i is more than or equal to 1 and less than or equal to N-2, and j is more than or equal to 2 and less than or equal to N-1-i;
the upper plate of the upper capacitor is connected to a reference voltage or ground, the upper plate of the lower capacitor is connected to the reference voltage or ground, the upper plate of the first starting capacitor is connected to the reference voltage or ground, and the upper plate of the second starting capacitor is connected to the reference voltage or ground;
the lower pole plate of the upper capacitor is connected with the lower pole plate of the lower capacitor to form the input end of the capacitor array digital-to-analog converter, the lower pole plate of the first starting capacitor is connected with the lower pole plate of the second starting capacitor to form the output end of the capacitor array digital-to-analog converter, the input end of the capacitor array digital-to-analog converter is connected with the output end of the capacitor array digital-to-analog converter, the output end of the capacitor array digital-to-analog converter is further connected to the in-phase input end of the comparator, and the reverse phase input end of the comparator is connected to.
2. The low-power analog-to-digital converter according to claim 1, further comprising a sampling switch, wherein one end of the sampling switch is connected to the input signal, and the other end of the sampling switch is connected to the input end of the capacitor array analog-to-digital converter.
3. A low power consumption analog-to-digital converter according to claim 1, characterized in that said upper capacitor array comprises a first selection switch and a plurality of first switches;
one end of the first switch is connected with the upper pole plate of the upper capacitor, the other end of the first switch is connected with the first end of the first selection switch, the second end of the first selection switch is connected with a reference voltage, and the third end of the first selection switch is connected with the ground.
4. A low power consumption analog-to-digital converter according to claim 3, characterized in that said lower capacitor array further comprises a second selection switch and a plurality of second switches;
one end of the second switch is connected to the upper pole plate of the lower capacitor, the other end of the second switch is connected to the first end of the selection switch, the second end of the second selection switch is connected to a reference voltage, and the third end of the second selection switch is connected to the ground.
5. A control method applied to a low power consumption analog-to-digital converter according to claim 4, comprising the steps of:
sampling: controlling the upper plate of the upper capacitor to be connected to the ground and controlling the upper plate of the lower capacitor to be connected to a reference voltage;
an input signal enters the capacitor array digital-to-analog converter from the input end of the capacitor array digital-to-analog converter, an in-phase holding signal is obtained at the output end of the capacitor array digital-to-analog converter, and the first switches and the second switches are controlled to be switched off;
B. comparison 1: the comparator compares the in-phase holding signal with the ground for the first time and outputs a first comparison result D (1);
C. comparison at the 2 nd time: according to the result of the first comparison D (1),
when D (1) =1, controlling the second selection switch to be connected to the ground;
when D (1) =0, controlling a first selection switch to be connected to the reference voltage;
the comparator performs the 2 nd comparison and outputs a 2 nd comparison result D (2);
the k comparison: according to the k-1 comparison result D (k-1), wherein k is more than or equal to 3 and less than or equal to N-1 is taken as a constraint condition,
when D (k-1) =1, controlling the second switches of the lower capacitors in the 1 st to (k-2) th lower capacitor groups to be turned on;
when D (k-1) =0, controlling the first switch of the upper capacitor in the 1 st to (k-2) th upper capacitor groups to be turned on;
the comparator carries out the kth comparison and outputs the kth comparison result D (k);
E. and k is increased by 1, step D is executed, the constraint condition is determined to be not satisfied, and the step D is finished.
6. The control method according to claim 5, wherein the step D specifically comprises:
when D (k-1) =1, controlling a first switch of a (k-1-i) th lower capacitor in the ith lower capacitor group to be turned on;
and when D (k-1) =0, controlling the first switch of the (k-1-i) th upper capacitor in the ith upper capacitor group to be switched on, wherein i is more than or equal to 1 and less than or equal to k-2.
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