CN112087404A - SOC-based RapidIO switch error processing method - Google Patents
SOC-based RapidIO switch error processing method Download PDFInfo
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- CN112087404A CN112087404A CN202010999191.2A CN202010999191A CN112087404A CN 112087404 A CN112087404 A CN 112087404A CN 202010999191 A CN202010999191 A CN 202010999191A CN 112087404 A CN112087404 A CN 112087404A
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- rapidio
- switch
- rapidio switch
- error detection
- communication port
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
- H04L49/555—Error detection
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
- H04L49/557—Error correction, e.g. fault recovery or fault tolerance
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a method for processing errors of a RapidIO switch based on SOC, which comprises the following steps: establishing an error detection process of a RapidIO switch communication port on an SOC processor through a RapidIO interface; establishing a RapidIO switch fault recovery process on the SOC processor through an i2c physical interface; and the RapidIO switch communication port error detection process and the RapidIO switch fault recovery process are independent. The invention can obviously improve the processing efficiency of the RapidIO switch fault of avionic network communication.
Description
Technical Field
The invention belongs to the technical field of aviation airborne electronics, and particularly relates to a method for processing errors of a RapidIO switch based on SOC.
Background
RapidIO is used as the most common serial data bus in the prior art, and is widely applied to the field of avionics due to high transmission speed, small transmission delay and flexible topological structure. The switch serves as the core of RapidIO, and the stability of the switch plays a very important role in the whole system. However, in some special cases, a RapidIO switch may be blocked at a port, so that a RapidIO network is broken down, thereby causing a failure of the whole system and bringing disastrous consequences to the flight safety of an aircraft.
Disclosure of Invention
Therefore, in order to overcome the defects of the prior art, the invention provides a method for processing errors of a RapidIO switch based on an SOC, so as to improve the processing efficiency of failures of the RapidIO switch of avionic network communication.
In order to achieve the above object, an error handling method for a RapidIO switch based on an SOC is provided, which includes:
establishing an error detection process of a RapidIO switch communication port on an SOC processor through a RapidIO interface;
establishing a RapidIO switch fault recovery process on the SOC processor through an i2c physical interface;
and the RapidIO switch communication port error detection process and the RapidIO switch fault recovery process are independent.
Further, the RapidIO switch communication port error detection process further includes:
and detecting signals of the switch according to the highest priority and a periodic detection mode, and starting the RapidIO switch fault recovery process if a signal fault is detected.
Further, the signal comprises a switch build chain signal.
Further, the RapidIO switch communication port error detection process further includes: the packet in each port of the switch is released.
Further, the RapidIO switch communication port error detection process further includes: clearing the sending and receiving enable of each port of the RapidIO switch, and closing the data transmission service.
Further, the RapidIO switch communication port error detection process further includes: and carrying out soft reset operation on the RapidIO switch.
Further, the RapidIO switch communication port error detection process further includes: the routing table of the RapidIO switch is reconfigured.
Further, the sending and receiving enabling of each port of the RapidIO switch is recovered, and the data transmission service is started.
Further, the loading of configuration data into registers is accomplished through address mapping and data mapping via the i2c interface.
Further, the RapidIO switch communication port error detection process detects the link state of each port of the RapidIO switch in a polling mode, and immediately starts the RapidIO switch fault recovery process to perform fault recovery after detecting that the link state is abnormal.
Compared with the prior art, the method can effectively solve the problem that the RapidIO switch in the field of aviation airborne electronics cannot be recovered from the abnormity under the condition of network failure, and obviously improves the robustness of the aviation communication network.
Drawings
Fig. 1 is a schematic diagram of a network topology structure of an airborne RapidIO switch.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
The network topology structure of the RapidIO switch is shown in fig. 1, the data communication nodes are realized by SOC, and the RapidIO IP core is used for managing the switch.
The error handling mechanism of the RapidIO switch is divided into two steps, namely fault detection and fault recovery. The fault detection of the switch can be completed through the RapidIO IP core, the communication state of the link can be detected by using a detection signal provided by the RapidIO IP core, once the communication link of the switch has a problem, the communication service of the switch is stopped immediately, and the fault recovery processing process is started. When the switch fails, the switch cannot be restored to a normal communication state by software reset and hardware reset, and error recovery of the switch needs to be completed by continuous detection and a series of configuration operations.
The invention uses an SOC processor XC7Z045 of Xilinx company as a platform, and configures the switch based on RapidIO IP core.
In an embodiment of the present invention, an error handling method for a RapidIO switch based on an SOC includes:
establishing an error detection process of a RapidIO switch communication port on an SOC processor through a RapidIO interface;
establishing a RapidIO switch fault recovery process on the SOC processor through an i2c physical interface;
and the RapidIO switch communication port error detection process and the RapidIO switch fault recovery process are independent.
The invention realizes the fault detection and fault processing of each port of the RapidIO switch through the i2c interface, and realizes the loading of the configuration data to the corresponding register through the address mapping and data mapping during the operation.
In one embodiment, the error detection process continuously detects the link state of each port of the RapidIO switch in a polling mode, and once a problem occurs, the error recovery process is started immediately to perform fault recovery.
In one embodiment of the invention, an SOC processor XC7Z045 is used as a platform, and the platform has two important conditions of RapidIO switch error recovery processing, wherein the processor has a RapidIO interface and supports an interconnection specification of RapidIO 1.3 or above, and the processor has an i2c physical interface, and when the switch fails, the switch can be recovered by using the physical interface.
The specific implementation process is as follows:
and a RapidIO switch error recovery step:
a) establishing an error detection process of a communication port of the switch on the SOC processor, detecting a link establishment signal of the switch according to the highest priority and a periodic detection mode, and starting a RapidIO switch fault recovery process if the link establishment signal fails;
b) starting a RapidIO switch fault recovery process, firstly releasing a data packet in each port of the switch by the process, and avoiding the port of the switch from being blocked;
c) clearing the sending and receiving enabling of each port of the RapidIO switch, and closing the data transmission service;
d) performing soft reset operation on the RapidIO switch to clear the error state of each port;
e) reconfiguring a routing table of the RapidIO switch;
f) and re-enabling the sending and receiving operation of each port, and recovering the data transmission service of the RapidIO switch.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. An error processing method of a RapidIO switch based on SOC is characterized by comprising the following steps:
establishing an error detection process of a RapidIO switch communication port on an SOC processor through a RapidIO interface;
establishing a RapidIO switch fault recovery process on the SOC processor through an i2c physical interface;
and the RapidIO switch communication port error detection process and the RapidIO switch fault recovery process are independent.
2. The method of claim 1 wherein the RapidIO switch communication port error detection process further comprises:
and detecting signals of the switch according to the highest priority and a periodic detection mode, and starting the RapidIO switch fault recovery process if a signal fault is detected.
3. The method of claim 2, wherein the signal comprises a switch link setup signal.
4. The method of claim 1 wherein the RapidIO switch communication port error detection process further comprises: the packet in each port of the switch is released.
5. The method of claim 4 wherein the RapidIO switch communication port error detection process further comprises: clearing the sending and receiving enable of each port of the RapidIO switch, and closing the data transmission service.
6. The method of claim 5 wherein the RapidIO switch communication port error detection process further comprises: and carrying out soft reset operation on the RapidIO switch.
7. The method of claim 6 wherein the RapidIO switch communication port error detection process further comprises: the routing table of the RapidIO switch is reconfigured.
8. The method of claim 7 wherein the data transfer traffic is turned on with the transmit and receive enable of each port of the RapidIO switch restored.
9. The method of claim 1, wherein loading configuration data into registers is accomplished through address mapping and data mapping via an i2c interface.
10. The method of claim 1 wherein the RapidIO switch communication port error detection process detects link status of each port of the RapidIO switch by polling, and immediately initiates a RapidIO switch failure recovery process for failure recovery upon detection of a link status anomaly.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010999191.2A CN112087404B (en) | 2020-09-22 | 2020-09-22 | SOC-based RapidIO switch error processing method |
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| CN202010999191.2A CN112087404B (en) | 2020-09-22 | 2020-09-22 | SOC-based RapidIO switch error processing method |
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| CN112087404A true CN112087404A (en) | 2020-12-15 |
| CN112087404B CN112087404B (en) | 2023-04-07 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114095462A (en) * | 2021-11-05 | 2022-02-25 | 中国航空工业集团公司雷华电子技术研究所 | Fault tolerance method and system for SRIO communication system of radar processor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6137801A (en) * | 1998-05-05 | 2000-10-24 | Excel Switching Corporation | Telecommunication switching system administrative and management tools |
| CN1773959A (en) * | 2005-10-25 | 2006-05-17 | 杭州华为三康技术有限公司 | Central router based on serial Rapid 10 bus |
| US20060143492A1 (en) * | 2001-11-28 | 2006-06-29 | Leduc Douglas E | System and method for fault detection and recovery |
| CN104915289A (en) * | 2015-05-12 | 2015-09-16 | 中国工商银行股份有限公司 | Anomaly detection method and device for background process of financial application system |
| CN110928684A (en) * | 2019-11-14 | 2020-03-27 | 苏宁云计算有限公司 | Method and system for realizing connection pool in multi-HiveServer 2 server scene |
-
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6137801A (en) * | 1998-05-05 | 2000-10-24 | Excel Switching Corporation | Telecommunication switching system administrative and management tools |
| US20060143492A1 (en) * | 2001-11-28 | 2006-06-29 | Leduc Douglas E | System and method for fault detection and recovery |
| CN1773959A (en) * | 2005-10-25 | 2006-05-17 | 杭州华为三康技术有限公司 | Central router based on serial Rapid 10 bus |
| CN104915289A (en) * | 2015-05-12 | 2015-09-16 | 中国工商银行股份有限公司 | Anomaly detection method and device for background process of financial application system |
| CN110928684A (en) * | 2019-11-14 | 2020-03-27 | 苏宁云计算有限公司 | Method and system for realizing connection pool in multi-HiveServer 2 server scene |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114095462A (en) * | 2021-11-05 | 2022-02-25 | 中国航空工业集团公司雷华电子技术研究所 | Fault tolerance method and system for SRIO communication system of radar processor |
| CN114095462B (en) * | 2021-11-05 | 2024-02-27 | 中国航空工业集团公司雷华电子技术研究所 | Fault-tolerant method and system for SRIO communication system of radar processor |
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| CN112087404B (en) | 2023-04-07 |
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