CN112084736A - USB3.0 physical layer transceiver based on FPGA - Google Patents
USB3.0 physical layer transceiver based on FPGA Download PDFInfo
- Publication number
- CN112084736A CN112084736A CN202010828228.5A CN202010828228A CN112084736A CN 112084736 A CN112084736 A CN 112084736A CN 202010828228 A CN202010828228 A CN 202010828228A CN 112084736 A CN112084736 A CN 112084736A
- Authority
- CN
- China
- Prior art keywords
- module
- serdes
- core
- physical layer
- fpga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001914 filtration Methods 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000006243 chemical reaction Methods 0.000 claims abstract description 14
- 239000000872 buffer Substances 0.000 claims abstract description 12
- 230000005540 biological transmission Effects 0.000 claims description 20
- 238000013461 design Methods 0.000 abstract description 7
- 238000004891 communication Methods 0.000 description 9
- 230000008054 signal transmission Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- VNFVKWMKVDOSKT-LREBCSMRSA-N (2r,3r)-2,3-dihydroxybutanedioic acid;piperazine Chemical compound C1CNCCN1.OC(=O)[C@H](O)[C@@H](O)C(O)=O VNFVKWMKVDOSKT-LREBCSMRSA-N 0.000 description 2
- ATHVAWFAEPLPPQ-VRDBWYNSSA-N 1-stearoyl-2-oleoyl-sn-glycero-3-phosphocholine Chemical compound CCCCCCCCCCCCCCCCCC(=O)OC[C@H](COP([O-])(=O)OCC[N+](C)(C)C)OC(=O)CCCCCCC\C=C/CCCCCCCC ATHVAWFAEPLPPQ-VRDBWYNSSA-N 0.000 description 2
- 101100041816 Homo sapiens SCD gene Proteins 0.000 description 2
- 101100309604 Homo sapiens SCD5 gene Proteins 0.000 description 2
- 101150097713 SCD1 gene Proteins 0.000 description 2
- 101100101423 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UBI4 gene Proteins 0.000 description 2
- 101150042597 Scd2 gene Proteins 0.000 description 2
- 102100028897 Stearoyl-CoA desaturase Human genes 0.000 description 2
- 102100033930 Stearoyl-CoA desaturase 5 Human genes 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/347—Physical level, e.g. placement or routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/08—Intellectual property [IP] blocks or IP cores
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Communication Control (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention discloses a USB3.0 physical layer transceiver device and a method based on FPGA, wherein the device is configured with a physical layer interface module, a Serdes IP core module, an initialization management module, a parameter configuration module, a data conversion module, an Rx filtering module, an Elastic buffer module and an LFPS generation module; after the initial reset operation is finished, performing parameter initial configuration on the Serdes IP core; generating an LFPS signal and sending the LFPS signal to opposite-end USB equipment, converting the LFPS signal of the opposite-end USB equipment and then carrying out filtering operation to generate the LFPS signal which can be identified by a USB3.0 controller; the data packet sent by the USB equipment at the opposite terminal is cached, compensated and corrected, and then the data format is converted and sent to the USB3.0 controller, or the data packet sent by the USB3.0 controller is converted into the data format and then sent to the USB equipment at the opposite terminal; the device executes the method, and the USB3.0 physical layer transceiver is realized by each module in the FPGA, so that the complexity of PCB hardware system design is simplified, the stability of a high-speed system is improved, and the cost is reduced.
Description
Technical Field
The invention relates to the technical field of high-speed data signal transmission, in particular to a USB3.0 physical layer transceiver based on an FPGA.
Background
USB (Universal Serial Bus), which is an external Bus standard, is used to standardize the connection and communication USB standards between computers and external devices. USB-IF formulation and maintenance by USB official organizations; the USB1.1, the USB2.0, the USB3.0, the USB3.1 and the USB3.2 have five versions, and the new version is compatible with the old version in the forward direction. The maximum transmission rate distribution supported by each version is: USB 1.1: 12 Mbps; USB 2.0: 480 Mbps; USB 3.0: 5 Gbps; USB 3.1: 10 Gbps; USB 3.2: 20 Gbps.
With the USB3.0 technology being widely applied, more and more embedded devices with USB3.0 interfaces are available, such as surveillance cameras, multimedia handheld devices, smart phones, digital cameras, portable media players, and personal navigation devices. The FPGA contains abundant high-speed transceiver resources, has high data processing speed and has great advantages in the field of data transmission; at present, the USB3.0 communication scheme based on FPGA, such as the SOPC processor implements 32-bit RISC (Reduced Instruction Set) processing, and is connected to the USB3.0 controller through the AXI interconnect bus, and the USB3.0 controller is generally connected to an externally mounted USB3.0 physical layer transceiver chip, such as the TUSB1310A chip of TI company, through a PIPE interface to construct a complete USB3.0 communication scheme.
The defects of the prior art are as follows: the plug-in USB3.0 physical layer transceiver chip needs to be connected to a PCB (Printed Circuit Board) through 40 high-speed signal lines of 250Mhz, so that the development complexity of a PCB hardware system is increased, the stability of the system is reduced, and the cost is increased.
Disclosure of Invention
The invention provides a USB3.0 physical layer transceiver based on FPGA (field programmable gate array), aiming at the technical problem that the design of a hardware system is more complex in the prior art.
The technical scheme for solving the technical problems is as follows:
in one aspect, an embodiment of the present invention provides a USB3.0 physical layer transceiver based on an FPGA, where the configuration includes:
the physical layer interface module is used for data transmission with the USB3.0 controller;
the LFPS generation module is used for coding the control signal generated by the USB3.0 controller and converting the control signal to generate an LFPS signal;
the Serdes IP core module is used for converting the output high-speed parallel data into serial data to be sent, and converting the received high-speed serial data of the USB equipment at the opposite end into parallel data;
the Rx filtering module is used for carrying out filtering operation on the control signal fed back by the Serdes IP core module to generate an LFPS signal which can be identified by the USB3.0 controller; the control signal fed back by the Serdes IP core module is obtained by converting an LFPS signal sent by the USB equipment at the opposite end;
the initialization management module is used for performing initial reset operation on each module before data transmission and performing control management on the parameter configuration module;
the parameter configuration module is used for the initial configuration of the Serdes IP core module parameters; the Serdes IP core parameters include, but are not limited to, SSC parameters and CDR parameters;
the Elastic buffer module is used for caching the data packet sent by the opposite-end USB device and automatically adaptively inserting and deleting the SKP Order set;
and the data format conversion module is used for performing data format conversion on the data packet sent by the opposite-end USB device and the data packet sent by the USB3.0 controller.
On the other hand, the embodiment of the invention provides a USB3.0 physical layer transceiving method based on FPGA, which comprises the following steps:
and 5, caching the data packet sent by the opposite-end USB equipment, automatically adaptively inserting and deleting SKP Order set, converting the data format and sending the data packet to the USB3.0 controller, or converting the data format of the data packet sent by the USB3.0 controller and sending the data packet to the opposite-end USB equipment.
The embodiment of the invention provides a USB3.0 physical layer transceiving device and method based on an FPGA (field programmable gate array). Each module is directly integrated in the FPGA in an IP (Internet protocol) core mode, so that the complete USB3.0 physical layer transceiving process is realized, a USB3.0 physical layer transceiving chip is not required to be mounted externally, the complexity of the design of a PCB (printed circuit board) hardware system is simplified, the stability of a high-speed system is improved, and the cost is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a USB3.0 physical layer transceiver based on FPGA according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the overall structure of the embodiment of the present invention;
fig. 3 is a schematic flowchart illustrating a flow chart of a USB3.0 physical layer transceiving method based on FPGA according to an embodiment of the present invention when executed;
reference numerals:
1. an initialization management module 3, a Serdes IP core module 2 and a parameter configuration module
4. Physical layer interface module 5, LFPS generation module 6 and Rx filtering module
7. A data format conversion module 8 and an Elastic buffer module.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
Fig. 1 is a schematic structural diagram of a USB3.0 physical layer transceiver based on FPGA according to an embodiment of the present invention; as shown in fig. 1, the configuration:
the physical layer interface module 4 is used for data transmission with the USB3.0 controller;
the LFPS generation module 5 encodes the control signal generated by the USB3.0 controller and converts the control signal to generate an LFPS signal;
the Serdes IP core module 3 is used for converting the output high-speed parallel data into serial data to be sent, and converting the received high-speed serial data of the USB equipment at the opposite end into parallel data;
the Rx filtering module 6 is used for carrying out filtering operation on the control signal fed back by the Serdes IP core module 3 and generating an LFPS signal which can be identified by the USB3.0 controller; the control signal fed back by the Serdes IP core module 3 is obtained by converting an LFPS signal sent by the USB equipment at the opposite end;
the initialization management module 1 is used for the initial reset operation of each module before data transmission and the control management of the parameter configuration module 2;
the parameter configuration module 2 is used for initial configuration of parameters of the Serdes IP core module 3; the Serdes IP core Module 3 parameters include, but are not limited to, SSC parameters and CDR parameters;
the Elastic buffer module 8 is used for caching the data packet sent by the USB equipment at the opposite end and automatically adaptively inserting and deleting the SKP Order set;
and the data format conversion module 7 is used for performing data format conversion on the data packet sent by the opposite-end USB equipment and the data packet sent by the USB3.0 controller.
Specifically, the physical layer interface module 4 is connected with the USB3.0 controller through the PIPE32 interface, and the physical layer interface module 4 is integrated into the USB3.0 communication system in the form of an IP core, so as to implement communication of a data link and communication of management control signals related to the USB3.0 physical layer transceiver. The Serdes IP core module 3 is a high-speed transceiver resource in the FPGA, when data are output and input, high-speed parallel data are converted into serial data and high-speed serial data are converted into parallel data through the internal Serdes IP core, and the serial data and the parallel data are connected with opposite-end USB equipment through two pairs of high-speed differential signal lines TxP/N and RxP/N. The parameter configuration module 2 initially configures the SSC (spread spectrum clock) parameter, the CDR (clock data recovery circuit) parameter, and other parameters required by the Serdes IP core module 3 to meet the high-speed signal transmission requirement specified by the USB3.0 protocol, thereby implementing stable high-speed signal transceiving and preventing the EMI (Electromagnetic Interference) problem. The initialization management module 1 performs initial reset operation on each module of the USB3.0 physical layer transceiver, and resets and initializes each module to a default state before use, so as to guarantee the working function of the USB3.0 transceiver; the initialization management module 1 performs control management on the parameter configuration module 2, and the control parameter configuration module 2 writes configuration values such as the SSC parameter and the CDR parameter into the Serdes IP core module 3. The LFPS generation module 5 is used for implementing a bypass Low-speed negotiation protocol specified by the USB3.0 protocol, the USB3.0 controller inputs txeletdle and txdetctrrxloopbk control signals through a PIPE32 interface of the physical layer interface module 4, the LFPS generation module 5 encodes the txeletdle and txdetctrrxloopbk control signals and converts the signals into signals inside the Serdes IP core module, and hardware generates an LFPS (Low Frequency periodic signal) signal. The Rx filtering module 6 is used for filtering the control signal fed back by the SerdesIP core module 3 to generate an LFPS signal which can be identified by the USB3.0 controller; specifically, the Serdes IP core module 3 receives an LFPS signal sent by an opposite-end USB device, and converts the LFPS signal into an rxelecdle signal through an internal Serdes IP core, and since the rxelecdle signal cannot be directly used, the Rx filtering module 6 is required to perform filtering operation on the rxelecdle signal, so as to generate an LFPS signal that can be identified by the USB3.0 controller. An Elastic buffer module 8 buffers the received data packet of the opposite-end USB device, and inserts and deletes the SKP ordered Set, so as to solve the problem of data asynchronism between the USB3.0 physical layer transceiver and the opposite-end USB device caused by the offset and jitter of the local clock, and prevent the received data from overflowing upwards and downwards. The data format conversion module 7 converts the data packet sent by the USB3.0 controller through the physical layer interface module 4 and the data packet data format of the USB device at the receiving end according to the requirement of the data transmission format of the Serdes IP core module 3.
Fig. 2 is a schematic diagram of the overall structure of the embodiment of the present invention, and as shown in fig. 2, the embodiment of the present invention preferably employs XC7K325T of the Kintex-7 series produced by Xilinx corporation to implement a complete USB3.0 communication scheme inside the FPGA; the SOPC processor is connected with the USB3.0 controller through an AXI interconnection bus, and the USB3.0 controller is connected to the USB3.0 physical layer transceiver device through a physical layer interface 4; the USB3.0 physical layer transceiver is directly integrated into the FPGA in an IP core mode, wherein a physical layer Interface 4 is a PIPE (the Phy Interface for the USB architecture) bus Interface connected with a USB3.0 controller, and the PIPE bus Interface supports a 32Bit SDR mode working under 125 Mhz. The invention preferably maps the GTX high-speed serial transceiver of Xilinx to the Serdes IP core module 3 in the USB3.0 physical layer transceiver, and two pairs of high-speed differential signal lines of TxP/N and RxP/N are connected with the opposite end USB device through a standard USB3.0 connector.
Further, the serdes ip core module 3 includes several types; such as Xilinx's GTH IP core, GTY's IP core, GTX's IP core, etc.; the type of the SerdesIP core module 3 is specifically configured according to the type of the FPGA.
Further, according to the type of the Serdes IP core module 3, the parameter configuration module completes the initial configuration of the corresponding Serdes IP core module 3 parameter; and configuring parameters such as SSC parameters and CDR parameters of the corresponding Serdes IP core modules 3 in different types of FPGAs to meet the high-speed signal transmission requirements of the Serdes IP core modules 3 in different types under the regulation of the USB3.0 protocol.
Further, initializing the management module, and further comprising a switching operation for a data transmission rate; USB3.0 currently supports only 5Gbps, while USB3.2 supports 10 Gbps; the switching of the data transmission rate makes the transceiver device upgraded to USB3.2 without redesign. Specifically, upgrading to the USB3.2 data transceiving function includes:
the initialization management module 1 starts a reset operation to reset the apparatus of the present invention. Receiving the pipe _ rate control signal, starting the rate switching function, adjusting the SSC parameter configuration value and the CDR parameter configuration value to 10Gbps mode by the parameter configuration module 2, and configuring the relevant parameters to the corresponding SerdesIP core module 3.
The LFPS generating module 5 receives the TxElecidle and TxDetectRxLoopbk signal control signals, generates an LFPS signal of SCD1/SCD2 type and an LBPM (SuperSpeedplus LFPS Based PWM Message Based on PWM information of ultra-high speed LFPS) signal, and carries out-of-band low-speed negotiation of USB 3.2; the serdes ip core module 3 converts the LBPM signal of the peer device into a corresponding control signal and sends the control signal to the Rx filtering module 6 for filtering operation, thereby completing information negotiation of the channel and rate of the USB 3.2. If the LFPS generation module 5 does not successfully perform the out-of-band low-speed negotiation of the USB3.2, the initialization management module 1 restarts the rate switching function, adjusts the SSC number configuration value and the CDR parameter configuration value to the 5Gbps mode, and configures the relevant parameters to the Serdes IP core module 3, and the LFPS generation module 5 generates an LFPS signal to enter the out-of-band low-speed negotiation of the USB 3.0.
The data format conversion module 7 carries out 128b/132b coding according to the data required to be sent by the Serdes ip core module 3, sends the data of the USB device at the opposite end received by the Serdes ip core module 3 to the Elastic buffer module 8 for buffer correction, and then sends the data to the data format conversion module 7, and the data format conversion module 7 carries out 128b/132b decoding on the corrected data, thereby upgrading to the data communication of the USB 3.2.
The embodiment of the invention provides a USB3.0 physical layer transceiver based on FPGA, which integrates all modules inside FPGA directly in an IP core mode, realizes a complete USB3.0 physical layer transceiving process, does not need to mount a USB3.0 physical layer transceiving chip externally, simplifies the complexity of PCB hardware system design, improves the stability of a high-speed system and reduces the cost; the high-speed signal transmission requirement of different types of Serdes IP cores under the regulation of the USB3.0 protocol can be met; the transceiver does not need to be redesigned when being upgraded to the USB3.2, so that the design work difficulty is reduced.
Based on the above embodiments, fig. 3 is a schematic flowchart illustrating a flow chart of the USB3.0 physical layer transceiving method based on FPGA according to an embodiment of the present invention when executed; as shown in fig. 3, the method comprises the following steps:
and 5, caching the data packet sent by the opposite-end USB equipment, automatically adaptively inserting and deleting the SKP Order set, converting the data format and sending the data packet to the USB3.0 controller, or converting the data format of the data packet sent by the USB3.0 controller and sending the data packet to the opposite-end USB equipment. Specifically, when data is sent, the USB3.0 controller transmits a data packet to be sent through the PIPE32 interface in a 32-bit wide manner; converting the data format of the data packet into an internal 32-bit wide data format according to the data transmission format requirement of the Serdes IP core, completing the conversion from parallel to serial through the Serdes IP core, and outputting the data to an opposite-end USB device through a TxP/N differential line; when receiving data, the SerdesIP core completes serial-to-parallel conversion on RxP/N differential line input signals, then converts a data format of the received data packet into a data format with a bit width of 32, writes the received data packet into an Elastic buffer cache, and corrects the received data packet by automatically adaptively inserting SKP ordered Set and deleting SKP ordered Set so as to prevent data receiving errors. The controller reads the valid received data packet from the Elastic buffer cache through the PIPE32 interface, and converts the valid received data packet into the 32-bit wide data format of the PIPE32 interface.
Further, Serdes IP cores include several types, such as Xilinx's GTH IP core, GTY's IP core, GTX's IP core, and so on; the type of the SerdesIP core is specifically configured according to the type of the FPGA.
Further, according to the type of the Serdes IP core, the initial configuration of the corresponding Serdes IP core parameter is completed. And according to the corresponding Serdes IP cores in the FPGAs of different types, completing the configuration of parameters such as the corresponding SSC parameter, CDR parameter and the like so as to meet the high-speed signal transmission requirement of the Serdes IP cores of different types under the regulation of the USB3.0 protocol.
Further, a switching operation for a data transmission rate is also included; USB3.0 currently supports only 5Gbps, while USB3.2 supports 10 Gbps; the switching of the data transmission rate makes the transceiver device upgraded to USB3.2 without redesign. Specifically, the step flow of upgrading to the USB3.2 data transceiving function:
a. starting reset operation to reset the device;
b. receiving a pipe _ rate control signal, starting a rate switching function, adjusting an SSC parameter configuration value and a CDR parameter configuration value to be in a 10Gbps mode, and configuring related parameters to corresponding SerdesIP cores;
c. receiving TxElecidle and TxDetectRxLoopbk signals to generate SCD1/SCD2 type LFPS signals and LBPM (SuperSpeedplus LFPS Based PWM Message Based on PWM information of ultra high speed LFPS) signals;
d. converting an LBPM out-of-band modulation signal of opposite-end USB equipment into a corresponding control signal to carry out filtering operation, and finishing information negotiation of a channel and a rate of USB 3.2; if the out-of-band low-speed negotiation of the USB3.2 is not successful, restarting a rate switching function, adjusting an SSC (sequence side sequence) number configuration value and a CDR (complementary digital Signal) parameter configuration value to be in a 5Gbps mode, configuring related parameters to a Serdes IP (Internet protocol) core, and performing the out-of-band low-speed negotiation of the USB3.0 with an opposite-end USB device through an LFPS (Long frequency packet switch) signal;
e. the data sent by the transmission data format according to the requirements of the Serdes ip core module 3 is encoded by 128b/132b, and the Serdes ip core module 3 receives the data buffer correction of the opposite end USB device and then decodes the data by 128b/132b, thereby upgrading to the data communication of USB 3.2.
The embodiment of the invention provides a USB3.0 physical layer transceiving method based on FPGA, which is executed on the device, and all modules are directly integrated in the FPGA in an IP core mode, so that the complete USB3.0 physical layer transceiving process is realized, a USB3.0 physical layer transceiving chip is not required to be mounted outside, the complexity of PCB hardware system design is simplified, the stability of a high-speed system is improved, and the cost is reduced; the high-speed signal transmission requirement of different types of Serdes IP cores under the regulation of the USB3.0 protocol can be met; the transceiver does not need to be redesigned when being upgraded to the USB3.2, so that the design work difficulty is reduced.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (8)
1. The USB3.0 physical layer transceiver based on FPGA is characterized by comprising the following configuration steps: the physical layer interface module is used for data transmission with the USB3.0 controller;
the LFPS generation module is used for coding the control signal generated by the USB3.0 controller and converting the control signal to generate an LFPS signal;
the Serdes IP core module is used for converting the output high-speed parallel data into serial data to be sent, and converting the received high-speed serial data of the USB equipment at the opposite end into parallel data;
the Rx filtering module is used for carrying out filtering operation on the control signal fed back by the Serdes IP core module to generate an LFPS signal which can be identified by the USB3.0 controller; the control signal fed back by the Serdes IP core module is obtained by converting an LFPS signal sent by the USB equipment at the opposite end;
the initialization management module is used for performing initial reset operation on each module before data transmission and performing control management on the parameter configuration module;
the parameter configuration module is used for the initial configuration of the Serdes IP core module parameters; the Serdes IP core parameters include, but are not limited to, SSC parameters and CDR parameters;
the Elastic buffer module is used for caching the data packet sent by the opposite-end USB device and automatically adaptively inserting and deleting the SKP Order set;
and the data format conversion module is used for performing data format conversion on the data packet sent by the opposite-end USB equipment and the data packet sent by the USB3.0 controller.
2. The FPGA-based USB3.0 physical layer transceiver of claim 1, wherein said serdes ip core module comprises a plurality of types; the type of the SerdesIP core module is specifically configured according to the type of the FPGA.
3. The FPGA-based USB3.0 physical layer transceiver of claim 2, wherein the parameter configuration module completes initial configuration of parameters of the Serdes IP core module according to the type of the Serdes IP core module.
4. The FPGA-based USB3.0 physical layer transceiver device of any one of claims 1 to 3, wherein the initialization management module further comprises a switching operation for a data transmission rate.
5. A USB3.0 physical layer transceiving method based on FPGA is characterized by comprising the following steps:
step 1, performing initial reset operation before data transmission;
step 2, completing the initial configuration of the Serdes IP core parameters; the Serdes IP core parameters include, but are not limited to, SSC parameters and CDR parameters;
step 3, coding a control signal input by the USB3.0 controller, converting the control signal to generate an LFPS signal and sending the LFPS signal to the USB equipment at the opposite end;
step 4, receiving the LFPS signal of the opposite-end USB device, converting the LFPS signal of the opposite-end USB device, and then performing filtering operation to generate the LFPS signal which can be identified by the USB3.0 controller;
and 5, caching the data packet sent by the opposite-end USB equipment, automatically adaptively inserting and deleting SKP Order set, converting the data format and sending the data packet to the USB3.0 controller, or converting the data format of the data packet sent by the USB3.0 controller and sending the data packet to the opposite-end USB equipment.
6. The FPGA-based USB3.0 physical layer transceiving method of claim 5, wherein the SerdesIP core comprises several types; the type of the SerdesIP core is specifically configured according to the type of the FPGA.
7. The FPGA-based USB3.0 physical layer transceiving method of claim 6, wherein initial configuration of corresponding Serdes IP core parameters is completed according to the type of the Serdes IP core.
8. The USB3.0 physical layer transceiving method based on FPGA of any one of claims 5 to 7, further comprising a data transmission rate switching operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010828228.5A CN112084736B (en) | 2020-08-17 | 2020-08-17 | USB3.0 physical layer transceiver based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010828228.5A CN112084736B (en) | 2020-08-17 | 2020-08-17 | USB3.0 physical layer transceiver based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112084736A true CN112084736A (en) | 2020-12-15 |
| CN112084736B CN112084736B (en) | 2024-04-05 |
Family
ID=73729432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010828228.5A Active CN112084736B (en) | 2020-08-17 | 2020-08-17 | USB3.0 physical layer transceiver based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112084736B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113193914A (en) * | 2021-03-09 | 2021-07-30 | 长芯盛（武汉）科技有限公司 | Sending unit, receiving unit, active transmission device and active transmission system suitable for USB signals |
| CN117056259A (en) * | 2023-08-08 | 2023-11-14 | 广东高云半导体科技股份有限公司 | Data processing device and method |
| CN117539818A (en) * | 2024-01-10 | 2024-02-09 | 富瀚微电子(成都)有限公司 | Interface based on PHY model, chip integrating interface and chip simulation system |
Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101039148A (en) * | 2007-02-07 | 2007-09-19 | 华为技术有限公司 | Optical module and method and network equipment for supporting GE optical connector and FE optical connector |
| CN102141795A (en) * | 2011-03-23 | 2011-08-03 | 中国地质大学（武汉） | Hierarchically reconstructed NURBS curve interpolator and configuration method thereof |
| CN102262435A (en) * | 2010-05-28 | 2011-11-30 | Lsi公司 | Methods and apparatus for low power out-of-band communications |
| CN104866447A (en) * | 2015-06-12 | 2015-08-26 | 哈尔滨工业大学 | Image injection module applied to flight scene simulation |
| CN106303759A (en) * | 2016-08-30 | 2017-01-04 | 北京赛博兴安科技有限公司 | A kind of high speed serialization transceiver interface based on FPGA and method of work thereof |
| CN107656882A (en) * | 2016-07-25 | 2018-02-02 | 深圳市中兴微电子技术有限公司 | A kind of USB controller verification method, system and equipment |
| WO2018132595A1 (en) * | 2017-01-13 | 2018-07-19 | A.T.E. Solutions, Inc. | Systems and methods for dynamically reconfiguring automatic test equipment |
| CN108924027A (en) * | 2018-09-19 | 2018-11-30 | 武汉库迪智能技术有限公司 | A kind of EtherCAT main station controller based on ARM kernel |
| CN109194679A (en) * | 2018-09-25 | 2019-01-11 | 北京航空航天大学 | A kind of multi-protocol interface data acquisition device and acquisition method based on SpaceFibre interface |
| CN109542815A (en) * | 2018-09-28 | 2019-03-29 | 天津市英贝特航天科技有限公司 | A kind of high-speed d/a system and working method based on USB3.0 interface |
| CN109889268A (en) * | 2019-01-28 | 2019-06-14 | 山东超越数控电子股份有限公司 | A kind of USB distance transmission system and method based on FPGA |
| CN110190876A (en) * | 2013-03-15 | 2019-08-30 | 凯萨股份有限公司 | Physical layer and virtualization physical layer suitable for EHF contactless communication |
| US20190386682A1 (en) * | 2018-06-13 | 2019-12-19 | Realtek Semiconductor Corporation | Serializer/Deserializer physical layer circuit |
| US20200033409A1 (en) * | 2018-07-27 | 2020-01-30 | Advantest Corporation | Integrated protocol analyzer configured within automated test equipment (ate) hardware |
| CN110941583A (en) * | 2019-12-10 | 2020-03-31 | 云南大学 | USB3.0 data transmission system control method based on FPGA |
| CN110955622A (en) * | 2019-12-19 | 2020-04-03 | 威创集团股份有限公司 | Data transmission device and USB optical fiber extender |
-
2020
- 2020-08-17 CN CN202010828228.5A patent/CN112084736B/en active Active
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101039148A (en) * | 2007-02-07 | 2007-09-19 | 华为技术有限公司 | Optical module and method and network equipment for supporting GE optical connector and FE optical connector |
| CN102262435A (en) * | 2010-05-28 | 2011-11-30 | Lsi公司 | Methods and apparatus for low power out-of-band communications |
| CN102141795A (en) * | 2011-03-23 | 2011-08-03 | 中国地质大学（武汉） | Hierarchically reconstructed NURBS curve interpolator and configuration method thereof |
| CN110190876A (en) * | 2013-03-15 | 2019-08-30 | 凯萨股份有限公司 | Physical layer and virtualization physical layer suitable for EHF contactless communication |
| CN104866447A (en) * | 2015-06-12 | 2015-08-26 | 哈尔滨工业大学 | Image injection module applied to flight scene simulation |
| CN107656882A (en) * | 2016-07-25 | 2018-02-02 | 深圳市中兴微电子技术有限公司 | A kind of USB controller verification method, system and equipment |
| CN106303759A (en) * | 2016-08-30 | 2017-01-04 | 北京赛博兴安科技有限公司 | A kind of high speed serialization transceiver interface based on FPGA and method of work thereof |
| WO2018132595A1 (en) * | 2017-01-13 | 2018-07-19 | A.T.E. Solutions, Inc. | Systems and methods for dynamically reconfiguring automatic test equipment |
| US20190386682A1 (en) * | 2018-06-13 | 2019-12-19 | Realtek Semiconductor Corporation | Serializer/Deserializer physical layer circuit |
| US20200033409A1 (en) * | 2018-07-27 | 2020-01-30 | Advantest Corporation | Integrated protocol analyzer configured within automated test equipment (ate) hardware |
| CN108924027A (en) * | 2018-09-19 | 2018-11-30 | 武汉库迪智能技术有限公司 | A kind of EtherCAT main station controller based on ARM kernel |
| CN109194679A (en) * | 2018-09-25 | 2019-01-11 | 北京航空航天大学 | A kind of multi-protocol interface data acquisition device and acquisition method based on SpaceFibre interface |
| CN109542815A (en) * | 2018-09-28 | 2019-03-29 | 天津市英贝特航天科技有限公司 | A kind of high-speed d/a system and working method based on USB3.0 interface |
| CN109889268A (en) * | 2019-01-28 | 2019-06-14 | 山东超越数控电子股份有限公司 | A kind of USB distance transmission system and method based on FPGA |
| CN110941583A (en) * | 2019-12-10 | 2020-03-31 | 云南大学 | USB3.0 data transmission system control method based on FPGA |
| CN110955622A (en) * | 2019-12-19 | 2020-04-03 | 威创集团股份有限公司 | Data transmission device and USB optical fiber extender |
Non-Patent Citations (2)
| Title |
|---|
| 尹旭东: "基于FPGA的USB3.0扰码及解扰码电路研究与设计", 《中国优秀硕士学位论文全文数据库》, no. 2, pages 135 - 931 * |
| 黄凯;林威;蒋进松;胡腾;修思文;严晓浪;: "低功耗可配置的USB3.0设备控制器IP核设计", 计算机工程, vol. 41, no. 12, pages 1 - 8 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113193914A (en) * | 2021-03-09 | 2021-07-30 | 长芯盛（武汉）科技有限公司 | Sending unit, receiving unit, active transmission device and active transmission system suitable for USB signals |
| CN113193914B (en) * | 2021-03-09 | 2022-03-25 | 长芯盛（武汉）科技有限公司 | Sending unit, receiving unit, active transmission device and active transmission system suitable for USB signals |
| US11494328B2 (en) | 2021-03-09 | 2022-11-08 | Everpro (Wuhan) Technologies Company Limited | Transmitting unit, receiving unit, active transmission device and active transmission system suitable for USB signals |
| CN117056259A (en) * | 2023-08-08 | 2023-11-14 | 广东高云半导体科技股份有限公司 | Data processing device and method |
| CN117539818A (en) * | 2024-01-10 | 2024-02-09 | 富瀚微电子(成都)有限公司 | Interface based on PHY model, chip integrating interface and chip simulation system |
| CN117539818B (en) * | 2024-01-10 | 2024-04-02 | 富瀚微电子(成都)有限公司 | Interface based on PHY model, chip integrating interface and chip simulation system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112084736B (en) | 2024-04-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112084736A (en) | USB3.0 physical layer transceiver based on FPGA | |
| US8990460B2 (en) | CPU interconnect device | |
| CN110837486B (en) | FlexRay-CPCIe communication system based on FPGA | |
| US11467909B1 (en) | Peripheral component interconnect express interface device and operating method thereof | |
| US20100014566A1 (en) | Method and apparatus for a 10gbase-t small form factor pluggable (sfp+) module | |
| KR20120011430A (en) | Usb connector for wireless communication device | |
| CN108462620B (en) | Gilbert-level SpaceWire bus system | |
| CN115296965A (en) | Method, system and device for reducing delay and achieving timer balance configuration | |
| CN102917213A (en) | System and method for transmitting optical fiber video images | |
| CN203643598U (en) | Radar data recording device | |
| CN206907017U (en) | Usb signal extender, usb signal transmission system | |
| CN114442514B (en) | USB3.0/3.1 control system based on FPGA | |
| CN105024756A (en) | Optical transmission system based on IEEE1394b data | |
| CN103034610A (en) | Methods and devices for transmission and reception of advanced extensible interface (AXI) bus signal between split modules | |
| CN114244909B (en) | Protocol conversion circuit and related device | |
| CN212647461U (en) | Synchronous or asynchronous serial communication control circuit based on PCI bus | |
| CN112350916A (en) | PCIE low-frequency optical fiber bridging system and method based on FPGA | |
| CN111258946A (en) | Communication method of GTX and TLK2711 series chips | |
| EP4116835A1 (en) | Spread spectrum clock negotiation method, and peripheral component interconnect express device and system | |
| CN103914421A (en) | Data terminal, data transmission system and hot-swap control method | |
| CN200980133Y (en) | A hidden communication interface circuit and television with such interface | |
| CN217821596U (en) | SDR heterogeneous prototype system based on FPGA | |
| CN115543908B (en) | Aurora bus data interaction system based on FPGA | |
| CN215452948U (en) | Optical fiber trigger pulse transmission device | |
| CN115209483B (en) | AAU (advanced architecture unit) forward interface, AAU and AAU forward interface rate adjustment method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |