CN112083310A - Intelligent plate testing system - Google Patents

Intelligent plate testing system Download PDF

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Publication number
CN112083310A
CN112083310A CN202010745366.7A CN202010745366A CN112083310A CN 112083310 A CN112083310 A CN 112083310A CN 202010745366 A CN202010745366 A CN 202010745366A CN 112083310 A CN112083310 A CN 112083310A
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CN
China
Prior art keywords
unit
connection
board
plate
array switch
Prior art date
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Pending
Application number
CN202010745366.7A
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Chinese (zh)
Inventor
陈永伟
索凌平
谢永靖
胥籽任
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
China General Nuclear Power Corp
CGN Power Co Ltd
China Nuclear Power Operation Co Ltd
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China General Nuclear Power Corp
CGN Power Co Ltd
China Nuclear Power Operation Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by China General Nuclear Power Corp, CGN Power Co Ltd, China Nuclear Power Operation Co Ltd filed Critical China General Nuclear Power Corp
Priority to CN202010745366.7A priority Critical patent/CN112083310A/en
Publication of CN112083310A publication Critical patent/CN112083310A/en
Priority to PCT/CN2021/076109 priority patent/WO2022021838A1/en
Pending legal-status Critical Current

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2803Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • G01R1/0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention relates to an intelligent testing system for plates, which comprises: the device comprises a plate socket which can be installed in a pluggable manner with a plate to be tested, a plate working circuit which can be electrically connected with the plate socket, an array switch which is connected with the plate socket and/or the plate working circuit, a control unit which is connected with the array switch, a communication unit which is connected with the control unit and a display unit which is connected with the communication unit; the display unit displays virtual nodes corresponding to the connecting nodes of the array switch, generates or clears connecting lines among the virtual nodes when the virtual nodes are triggered, and the control unit triggers the corresponding connecting nodes in the array switch to be connected or disconnected when the virtual nodes are triggered. The invention is convenient to operate and can reduce the workload of the plate testing process.

Description

Intelligent plate testing system
Technical Field
The invention relates to the technical field of plate testing, in particular to an intelligent plate testing system.
Background
The number of plates for each round of overhaul verification of the nuclear power station in Bay, Ridge and Australia is huge and is close to 300, and the main defects and defects existing in the traditional plate verification mode are as follows: the wiring mode is realized by wiring cables with dozens of pins or even hundreds of pins, so that the wiring mode is not intuitive and messy, and the wiring error probability is increased; meanwhile, when the plate is checked, more signal sources and measuring instruments need to be connected externally, and the difficulty of field layout management is increased in the testing process; meanwhile, due to the complex wiring, the fault point is difficult to find when the abnormity occurs, and the fault point is difficult to quickly and accurately position.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide an intelligent board testing system, aiming at some technical defects in the prior art.
The technical scheme adopted by the invention for solving the technical problems is as follows: constructing a panel intelligent test system comprising: the device comprises a plate socket which can be installed in a pluggable mode with a plate to be tested, a plate working circuit which can be electrically connected with the plate socket, an array switch which is connected with the plate socket and/or the plate working circuit, a control unit which is connected with the array switch, a communication unit which is connected with the control unit and a display unit which is connected with the communication unit; wherein the content of the first and second substances,
the display unit displays virtual nodes corresponding to the connection nodes of the array switch, the display unit generates or clears connection lines between the virtual nodes when the virtual nodes are triggered, and the control unit triggers the connection nodes corresponding to the array switch to be connected or disconnected when the virtual nodes are triggered.
Preferably, the panel working circuit includes a power supply unit, a reference signal output unit, and an output detection unit;
the array switch includes:
a first array switch that connects the first attribute pins of the board socket to form a connection relationship between the first attribute pins;
a second array switch for connecting the second attribute pin of the board socket and the power supply unit to form a connection relationship of the power supply unit to the second attribute pin;
a third array switch for connecting a third attribute pin of the board socket and the reference signal output unit to form a connection relationship between the reference signal output unit and the third attribute pin; and/or
And the fourth array switch is used for connecting the fourth attribute pin of the plate socket with the output detection unit to form the connection relationship of the fourth attribute pin and the output detection unit.
Preferably, the communication unit is connected to the reference signal output unit and is configured to control the reference signal output unit to output a reference signal; and/or
The communication unit is connected with the output detection unit and used for acquiring the detection signal of the output detection unit.
Preferably, the display unit includes a first trigger unit;
the display unit clears the connection lines among all the virtual nodes when the first trigger unit is triggered, and the control unit triggers all the connection nodes in the array switch to be disconnected when the first trigger unit is triggered.
Preferably, the display unit includes a first storage unit and a second trigger unit;
and the display unit stores the connection state corresponding to the current operation of the virtual node to the first storage unit when the second trigger unit is triggered.
Preferably, the display unit includes a third trigger unit;
the display unit acquires and generates or clears the connection between the virtual nodes according to the connection state corresponding to the last operation of the virtual nodes when the third trigger unit is triggered, and the control unit acquires and triggers the connection or disconnection of the corresponding connection nodes in the array switch according to the connection state corresponding to the last operation when the third trigger unit is triggered.
Preferably, the display unit includes a panel information input unit;
the plate information input unit is used for inputting plate information of the plate to be detected;
and the display unit acquires and stores plate information of the plate to be detected when the connection state corresponding to the current operation of the virtual node is stored to the first storage unit.
Preferably, the display unit further comprises a second storage unit and a fourth trigger unit;
the second storage unit is used for storing a preset connection state corresponding to the plate to be tested;
the display unit acquires the corresponding preset connection state according to the plate information of the plate to be detected when the fourth trigger unit is triggered, and generates or clears the connection between the virtual nodes according to the preset connection state, and the control unit triggers the connection or disconnection corresponding to the connection nodes in the array switch according to the preset connection state when the fourth trigger unit is triggered.
Preferably, the plate information of the plate to be tested includes a plate name of the plate to be tested and/or a plate test case of the plate to be tested.
Preferably, the array switch is composed of a contactless photoelectric relay, and/or
The display unit is a touch display screen.
The intelligent board testing system has the following beneficial effects: convenient operation can significantly reduce the workload of the plate testing process.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a logic block diagram of an embodiment of an intelligent board testing system according to the present invention;
FIG. 2 is a logic block diagram of another embodiment of an intelligent board testing system according to the present invention;
FIG. 3 is a diagram of a display unit displaying an interface according to an embodiment of the present invention.
Detailed Description
For a more clear understanding of the technical features, objects and effects of the present invention, embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
As shown in fig. 1, in a first embodiment of the intelligent testing system for boards of the present invention, the system includes: the board socket 110 which can be installed in a pluggable manner with a board to be tested, the board working circuit 120 which can be electrically connected with the board socket 110, the array switch 130 which is connected with the board socket 110 and/or the board working circuit 120, the control unit 140 which is connected with the array switch 130, the communication unit 150 which is connected with the control unit 140, and the display unit 160 which is connected with the communication unit 150; the display unit 160 displays virtual nodes 161 corresponding to the connection nodes of the array switch 130, the display unit 160 generates or clears the connection between the virtual nodes 161 when the virtual nodes 161 are triggered, and the control unit 140 triggers the connection or disconnection of the corresponding connection nodes in the array switch 130 when the virtual nodes 161 are triggered. Specifically, in the test system, the board to be tested is matched with the board socket 110 and is installed in a manner that the board to be tested and the board socket 110 can be plugged, and when the board to be tested needs to be tested, the board to be tested is placed on the board socket 110 to form a test circuit of the board to be tested. The board working circuit 120 corresponds to a working circuit for realizing various application functions of the board during testing of the board. An array switch may be disposed between the pins of the board socket 110 or between the board socket 110 and the board working circuit 120, and the connection nodes of the array switch may be turned on and off by disposing each switch in the array switch, so as to finally form different electrical connection relationships between the pins of the board socket 110 or between the board socket 110 and the board working circuit 120. The different electrical connection relations correspond to the tests of different functions or indexes of the plate to be tested. The control of the array switch 130 may be controlled by control instructions of the control unit 140. The control unit 140 is connected to the display unit 160 through the communication unit 150, and the display unit 160 displays a virtual node 161, where the virtual node 161 and the connection node of the array switch 130 are in a one-to-one correspondence relationship. The connection node of the array switch 130 is understood to be a connection node of the array switch 130 for external circuit. When a connection relationship between the end points of the board socket 110 and/or the board working circuit 120 is determined, it may trigger the virtual node 161 corresponding to the connection node of the array switch 130 corresponding to the end point, for example, sequentially click on two virtual nodes 161, and when the two virtual nodes 161 are in an unlined state, a connection line between the two virtual nodes 161 is generated on the display unit 160. Meanwhile, when the virtual node 161 is triggered and the two virtual nodes 161 are disconnected, the control unit 140 triggers the connection node of the array switch 130 corresponding to the triggered virtual node to connect, so as to form an electrical connection relationship in the actual test circuit corresponding to the connection of the virtual node 161 on the display unit 160. When a connection relationship between the end points of the board socket 110 and/or the board working circuit 120 is to be disconnected, the virtual nodes 161 corresponding to the connection nodes corresponding to the end points may be sequentially triggered, for example, two virtual nodes 161 are sequentially clicked, and when the two virtual nodes 161 are connected, the connection between the two virtual nodes 161 is cleared on the display unit 160. Meanwhile, when the virtual node 161 is triggered and the two virtual nodes 161 are connected, the control unit 140 triggers the connection node corresponding to the triggered virtual node in the array switch 130 to disconnect, so as to disconnect the electrical connection relationship in the actual test circuit corresponding to the connection of the virtual node 161 on the display unit 160. It can be understood that, when the control unit 140 and the display unit 160 receive the triggering instruction triggered by the virtual node 161, both of them may first determine whether the current virtual node 161 has a connection, so as to respectively trigger the actual array switch action and the action of generating or clearing the connection on the display unit 160 according to the determination result, thereby implementing the consistency between the display state of the display unit 160 and the electrical connection relationship in the actual test system.
Alternatively, as shown in fig. 2, the board working circuit 120 includes a power supply unit 121, a reference signal output unit 122, and an output detection unit 123; the array switch 130 includes: a first array switch 131 connecting the first attribute pins of the board socket 110 to form a connection relationship between the first attribute pins; a second array switch 132 connecting the second attribute pin of the board socket 110 with the power supply unit 121 to form a connection relationship of the power supply unit 121 to the second attribute pin; a third array switch 133 connecting the third attribute pin of the board socket 110 with the reference signal output unit 122 to form a connection relationship of the reference signal output unit 122 with the third attribute pin; and/or a fourth array switch 134 connecting the fourth property pin of board socket 110 with output detection unit 123 to form a connection relationship of the fourth property pin with output detection unit 123. Specifically, according to the working principle of each specific circuit in the working and testing processes of the board, the board working circuit 120 corresponding to the board to be tested can be divided into a power supply unit 121, a reference signal output unit 122 and an output detection unit 123. For convenience of control, different array switches 130 are arranged to form different circuit connections for different circuit connections. The power supply unit 121 is configured to supply power to a board to be tested, and may be connected to a power supply pin of the board to be tested through a second attribute pin of the board socket 110, and the power supply unit 121 and the second attribute pin are turned on or off by setting the second array switch 132; the reference signal output unit 122 is configured to provide a test input signal of the board to be tested, which is also understood as a reference signal, and may be connected to the reference signal input pin of the board to be tested through the third attribute pin of the board socket 110, and the reference signal output unit 122 is connected to or disconnected from the third attribute pin by setting the third array switch 133; the output detection unit 123 is configured to obtain a test output signal of the board to be tested, and may be connected to the test signal output pin of the board to be tested through the fourth attribute pin of the board socket 110, and the output detection unit 123 is turned on or off with the fourth attribute pin through the fourth array switch 134. In the testing process of the plate to be tested, the virtual node 161 corresponding to the second array switch 132 is triggered, so that the power supply unit 121 supplies power to the plate to be tested, the virtual node 161 corresponding to the third array switch 133 is triggered, a reference signal is input to the plate to be tested, the virtual node 161 corresponding to the fourth array switch 134 is triggered, so that the output detection unit 123 obtains an output signal of the plate to be tested, and the performance index of the plate to be tested is determined according to the relation between the test output signal or the test output signal and the reference signal. Meanwhile, in the working process of some plates to be tested, part of pins of the plates to be tested need to be connected, at this time, the first attribute pins of the plate socket 110 are connected with the corresponding pins of the plates to be tested, and the first array switch 131 is arranged to realize the connection or disconnection between the first attribute pins. By triggering the virtual node 161 corresponding to the first array switch 131, the connection or disconnection relationship between the internal working pins of the board to be tested can be realized. The corresponding relationship between each array switch and the dummy node 161 is the corresponding relationship between the dummy node 161 and the connection node of the array switch described above. The first array switch 131, the second array switch 132, the third array switch 133, and the fourth array switch 134 may be selectively set as needed.
Optionally, the communication unit 150 is connected to the reference signal output unit 122, and is configured to control the reference signal output unit 122 to output the reference signal; and/or the communication unit 150 is connected to the output detection unit 123 for acquiring and outputting the detection signal of the detection unit 123. That is, the display unit 160 may control the reference signal output unit 122 to output a required reference signal through the communication unit 150, and the display unit 160 may also receive the detection signal acquired by the output detection unit 123 through the communication unit 150 and confirm the test result of the board to be tested.
Alternatively, as shown in fig. 3, the display unit 160 includes a first trigger unit; the display unit 160 clears the connection between all the virtual nodes 161 when the first trigger unit is triggered, and the control unit 140 triggers all the connection nodes in the array switch 130 to be disconnected when the first trigger unit is triggered. That is, the first trigger unit may be triggered to generate a clear instruction, the display unit 160 clears the connecting lines between all the currently displayed virtual nodes 161 according to the clear instruction, and after the clear instruction is executed, all the virtual nodes 161 displayed on the display unit 160 have no connecting line relationship. Meanwhile, when the first trigger unit is triggered and generates a clear instruction, the control unit 140 triggers all the connection nodes in the array switches to be disconnected according to the received clear instruction, that is, disconnects the connection relationships among the connection nodes of all the array switches. The clear instruction may be generated by activating a clear button 162 provided in the display unit 160.
Optionally, the display unit 160 includes a first storage unit and a second trigger unit; the display unit 160 stores the connection state corresponding to the current operation of the virtual node 161 to the first storage unit when the second trigger unit is triggered. That is, the second triggering unit may be triggered to generate a storage instruction, the display unit 160 stores the links between all the currently displayed virtual nodes 161 according to the storage instruction, the execution of the storage instruction may not affect the displayed links of the display unit 160, and the control unit 140 may not respond to the storage instruction and does not trigger the array switch action. The storage instruction may be generated by activating a save key provided by the display unit 160.
Optionally, the display unit 160 includes a third trigger unit; the display unit 160 acquires the connection state corresponding to the previous operation of the virtual node 161 when the third trigger unit is triggered, and generates or clears the connection between the virtual nodes 161 according to the connection state corresponding to the previous operation of the virtual node 161, and the control unit 140 acquires the connection state corresponding to the previous operation of the virtual node 161 when the third trigger unit is triggered, and triggers the connection or disconnection of the corresponding connection node in the array switch 130 according to the connection state corresponding to the previous operation. That is, the third trigger unit may be triggered to generate a return instruction, and the display unit 160 acquires and generates or clears the connection line between the virtual nodes 161 according to the connection line state corresponding to the previous operation of the virtual node 161, that is, the display connection line of the display unit 160 is displayed as the connection line relationship corresponding to the previous virtual node 161. Meanwhile, when the third trigger unit is triggered and generates a return instruction, the control unit 140 triggers the connection or disconnection of the corresponding connection node in the array switch 130 according to the connection state corresponding to the previous operation of the virtual node 161, so as to form a connection relationship between the connection nodes of the array switch formed after the previous connection node action. The return instruction may be generated by activating a return key 163 provided in the display unit 160.
Alternatively, the display unit 160 includes a panel information input unit; the plate information input unit is used for inputting plate information of a plate to be detected; when the connection state corresponding to the current operation of the virtual node 161 is stored in the first storage unit, the display unit 160 acquires and stores the plate information of the plate to be tested. When saving the connection state corresponding to the current operation of the virtual node 161, the display unit 160 may acquire the board information through the board information input unit to correspond the current connection state to the board related information. The panel information input unit may perform input of related information by providing a corresponding information input window at the display unit 160.
Optionally, the display unit 160 further includes a second storage unit and a fourth trigger unit; the second storage unit is used for storing a preset connection state corresponding to the plate to be tested; when the fourth trigger unit is triggered, the display unit 160 obtains a corresponding preset connection state according to the plate information of the plate to be tested, and generates or clears a connection between the virtual nodes 161 according to the preset connection state, and when the fourth trigger unit is triggered, the control unit 140 triggers connection or disconnection corresponding to the connection nodes in the array switch 130 according to the preset connection state. When the connection relationship between the virtual nodes 161 is generated, the connection relationship between the virtual nodes 161 may be preset and stored according to the plate information of the plate to be tested, and when the plate to be tested is tested, the connection relationship between the virtual nodes 161 may be generated or some connection between the virtual nodes 161 may be eliminated by triggering the fourth trigger unit to generate a call instruction, and directly calling the pre-stored corresponding connection state according to the acquired plate information of the plate to be tested. Meanwhile, when the fourth trigger unit is triggered and generates a call instruction, the control unit 140 triggers connection or disconnection corresponding to the connection node in the array switch 130 according to the acquired preset connection state, so as to form a connection relationship between the connection nodes of the array switch. The call instruction may be generated by triggering a call key provided by the display unit 160.
Optionally, the plate information of the plate to be tested includes a plate name of the plate to be tested and/or a plate test case of the plate to be tested. When the plate to be tested is saved or called in a connection state, the plate to be tested can be distinguished according to the plate name of the plate to be tested, can also be distinguished according to a plate test case corresponding to the plate to be tested, and can also be distinguished through the combination of the plate to be tested and the plate test case.
Optionally, the array switch 130 is composed of contactless photoelectric relays, and the array switch is composed of contactless photoelectric relays with low thermoelectric potential and low on-resistance, so that the system reliability can be improved, the power consumption can be reduced, and the space can be saved.
Optionally, the display unit 160 is a touch display screen. In order to facilitate operation, the virtual contact can be directly triggered through the touch display screen, and the connection relation of the test circuit is rapidly realized.
According to the plate intelligent test system, the connection relation between the virtual nodes is formed by triggering the virtual nodes, the corresponding connecting lines are generated, and meanwhile, the array switch acts according to the triggering instruction of the virtual nodes to form the connection relation between the corresponding connecting nodes, so that the final connection relation of the connecting circuit is formed. And under the circuit connection relation, obtaining a test result of the plate to be tested, and completing the test of the plate to be tested. The method specifically comprises the step of carrying out various operations according to the intelligent plate testing system so as to test different plates to be tested.
It is to be understood that the foregoing examples, while indicating the preferred embodiments of the invention, are given by way of illustration and description, and are not to be construed as limiting the scope of the invention; it should be noted that, for those skilled in the art, the above technical features can be freely combined, and several changes and modifications can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention; therefore, all equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the claims of the present invention.

Claims (10)

1. An intelligent testing system for plates, comprising: the device comprises a plate socket which can be installed in a pluggable mode with a plate to be tested, a plate working circuit which can be electrically connected with the plate socket, an array switch which is connected with the plate socket and/or the plate working circuit, a control unit which is connected with the array switch, a communication unit which is connected with the control unit and a display unit which is connected with the communication unit; wherein the content of the first and second substances,
the display unit displays virtual nodes corresponding to the connection nodes of the array switch, the display unit generates or clears connection lines between the virtual nodes when the virtual nodes are triggered, and the control unit triggers the connection nodes corresponding to the array switch to be connected or disconnected when the virtual nodes are triggered.
2. The board intelligent test system of claim 1, wherein the board working circuit comprises a power supply unit, a reference signal output unit and an output detection unit;
the array switch includes:
a first array switch that connects the first attribute pins of the board socket to form a connection relationship between the first attribute pins;
a second array switch for connecting the second attribute pin of the board socket and the power supply unit to form a connection relationship of the power supply unit to the second attribute pin;
a third array switch for connecting a third attribute pin of the board socket and the reference signal output unit to form a connection relationship between the reference signal output unit and the third attribute pin; and/or
And the fourth array switch is used for connecting the fourth attribute pin of the plate socket with the output detection unit to form the connection relationship of the fourth attribute pin and the output detection unit.
3. The intelligent board testing system according to claim 2,
the communication unit is connected with the reference signal output unit and is used for controlling the reference signal output unit to output a reference signal; and/or
The communication unit is connected with the output detection unit and used for acquiring the detection signal of the output detection unit.
4. The intelligent board testing system according to claim 1, wherein the display unit includes a first triggering unit;
the display unit clears the connection lines among all the virtual nodes when the first trigger unit is triggered, and the control unit triggers all the connection nodes in the array switch to be disconnected when the first trigger unit is triggered.
5. The intelligent board testing system according to claim 1, wherein the display unit comprises a first storage unit and a second trigger unit;
and the display unit stores the connection state corresponding to the current operation of the virtual node to the first storage unit when the second trigger unit is triggered.
6. The intelligent board testing system according to claim 5, wherein the display unit includes a third triggering unit;
the display unit acquires and generates or clears the connection between the virtual nodes according to the connection state corresponding to the last operation of the virtual nodes when the third trigger unit is triggered, and the control unit acquires and triggers the connection or disconnection of the corresponding connection nodes in the array switch according to the connection state corresponding to the last operation when the third trigger unit is triggered.
7. The board intelligent test system of claim 5, wherein the display unit comprises a board information input unit;
the plate information input unit is used for inputting plate information of the plate to be detected;
and the display unit acquires and stores plate information of the plate to be detected when the connection state corresponding to the current operation of the virtual node is stored to the first storage unit.
8. The intelligent board testing system according to claim 7, wherein the display unit further comprises a second storage unit and a fourth trigger unit;
the second storage unit is used for storing a preset connection state corresponding to the plate to be tested;
the display unit acquires the corresponding preset connection state according to the plate information of the plate to be detected when the fourth trigger unit is triggered, and generates or clears the connection between the virtual nodes according to the preset connection state, and the control unit triggers the connection or disconnection corresponding to the connection nodes in the array switch according to the preset connection state when the fourth trigger unit is triggered.
9. The board intelligent test system according to claim 7, wherein the board information of the board to be tested comprises a board name of the board to be tested and/or a board test case of the board to be tested.
10. The intelligent board testing system according to claim 1,
the array switch is composed of a contactless photoelectric relay, and/or
The display unit is a touch display screen.
CN202010745366.7A 2020-07-29 2020-07-29 Intelligent plate testing system Pending CN112083310A (en)

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CN202010745366.7A CN112083310A (en) 2020-07-29 2020-07-29 Intelligent plate testing system
PCT/CN2021/076109 WO2022021838A1 (en) 2020-07-29 2021-02-08 Intelligent plate test system

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Cited By (4)

* Cited by examiner, † Cited by third party
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WO2022021839A1 (en) * 2020-07-29 2022-02-03 中广核核电运营有限公司 Intelligent panel testing system having checking function
WO2022021838A1 (en) * 2020-07-29 2022-02-03 中广核核电运营有限公司 Intelligent plate test system
WO2022021837A1 (en) * 2020-07-29 2022-02-03 中广核核电运营有限公司 Intelligent test system and method for memory panel
CN113625600A (en) * 2021-07-19 2021-11-09 中广核核电运营有限公司 Intelligent connection device, system and method for switch array pins

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Application publication date: 20201215