CN112073354B - High-speed mobile wireless communication system based on FPGA - Google Patents
High-speed mobile wireless communication system based on FPGA Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2657—Carrier synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/001—Synchronization between nodes
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a high-speed mobile wireless communication system based on FPGA, a base station is arranged at intervals of preset distance along an optical fiber, a 2.5G synchronous ring network is formed between the base stations, and the base stations are connected with a monitoring center, and broadband communication is carried out between a mobile terminal and the base stations; the timing and carrier synchronization is realized between the mobile terminal and the base station, the uplink rate and the downlink rate adopt an asymmetric mode with configurable uplink-downlink rate ratio, and the communication rate is automatically configured according to the number of the mobile terminals which are simultaneously accessed into the base station; the base station coordinates with the adjacent base station to determine the communication modes of the downlink channel and the uplink channel, so that the mobile terminal can be smoothly switched between different base stations; both the base station and the mobile terminal include modems. By the technical scheme of the invention, the asymmetric rates of the upper and lower channels are realized, and the base station can automatically adjust the communication rate of each terminal according to the number of the terminals which can be accessed, so that the problem of seamless switching of the mobile terminal in the high-speed mobile communication process is solved.
Description
Technical Field
The invention relates to the technical field of communication systems, in particular to a high-speed mobile wireless communication system based on an FPGA.
Background
In recent years, with rapid development of science, technology and economy, traffic construction in China is rapidly developed, so that more and more people select high-speed rails or automobiles as travel modes, and the frequency of occurrence of mobile terminals in a high-speed moving scene is increased. The mobile terminal can cause Doppler frequency shift in a high-speed moving state, so that the synchronous receiving difficulty of a OFDM (Orthogonal Frequency Division Multiplexing) system is increased, and the quality of a communication link cannot be ensured.
At present, partial scholars focus on realizing synchronization by using redundant information of cyclic prefix, consider the defect of the cyclic prefix, and propose a new timing measurement function and a new detection function by using sampling in an inter-symbol interference-free interval. In order to improve the anti-interference capability under the low signal-to-noise ratio, a time offset blind estimation algorithm based on distance measurement is provided by combining with a cut-off CP technology. However, the algorithm is complex and is not suitable for mobile terminals with real-time requirements. Therefore, partial scholars combine pilot frequency or preamble symbol to realize the synchronization of OFDM system, and a preamble symbol composed of ZC (Zadoff-Chu) sequence is proposed. The synchronization result is ensured not to be affected by frequency by constructing a training sequence with a conjugate repetition relation structure. In order to avoid the problems of timing ambiguity and the like, a weighted (Constant Amplitude Zero Auto-Correlation, CAZAC) training sequence is provided, and a synchronization algorithm for joint estimation of symbol timing and carrier frequency offset is provided on the basis. With fewer auxiliary sequences, an autocorrelation estimation Auto Correlation Estimation, ACE) time-frequency synchronization algorithm is proposed, and frequency offset estimation is completed by combining the ideas of autocorrelation function and weighted average. To determine the symbol synchronization point, a Schmidl & Cox algorithm is adopted to determine the symbol synchronization range, and then a Park algorithm is combined to determine the symbol synchronization point. Although synchronization algorithms incorporating pilot or preamble symbols enable synchronization of OFDM systems, they pass through algorithm verification mainly by simulation systems and do not actually test in conjunction with specific hardware devices.
Disclosure of Invention
In view of the above problems, the present invention provides a high-speed mobile wireless communication system based on FPGA and OFDM technology, and designs a downlink channel, an uplink channel and a modem system for a communication process between a mobile terminal and a base station based on PN synchronization, so as to implement asymmetric rates of the uplink and downlink channels, and the base station can automatically adjust a communication rate of each terminal according to the number of terminals that can be accessed, and under two conditions of moving towards the base station and moving away from the base station, a high-gain omni-directional antenna has advantages over a low-gain omni-directional antenna, and a single-tone signal can more accurately reflect fading depth than a bandwidth signal.
To achieve the above object, the present invention provides a high-speed mobile wireless communication system based on FPGA, comprising: the system comprises a base station, a mobile terminal, a monitoring center and an optical fiber ring network; setting a base station at intervals of a preset distance along an optical fiber, forming a 2.5G synchronous ring network between the base stations through the optical fiber, connecting the base stations with the monitoring center, and performing broadband communication between the mobile terminal and the base stations; the timing synchronization and the carrier synchronization are realized between the mobile terminal and the base station, and an asymmetric mode capable of configuring uplink and downlink rate ratios is adopted for uplink and downlink rates between the mobile terminal and the base station, and the communication rate of each mobile terminal is automatically configured according to the number of mobile terminals simultaneously connected to the base station; the base station coordinates with the adjacent base station to determine the communication modes of the downlink channel and the uplink channel between the base station and the mobile terminal, so as to realize smooth switching of the mobile terminal between different base stations; the base station and the mobile terminal both comprise modems, the modems of the base station are connected with external equipment through an IP exchanger, and the modems of the mobile terminal are connected with the external equipment through a WiFi module.
In the above technical solution, preferably, according to the sequence from near to far between the base station and the monitoring center, the base station with the odd sequence number is defined as an odd base station, and the base station with the even sequence number is defined as an even base station; the data format of the downlink channel comprises a synchronous head, a control 0 bit, a control 1 bit, a class 1 channel and a class 2 channel, the timing synchronization and the carrier synchronization between the mobile terminal and the base station are realized through the synchronous head, the even base station transmits control information and controls 1 bit time slot idling by using the control 0 bit time slot, and the odd base station transmits control information and controls 0 bit time slot idling by using the control 1 bit time slot; all time slots of the class 1 channel can be utilized by the base station, even base stations can only use even ordinal time slots and odd ordinal time slots of the class 2 channel to be empty, and odd base stations can only use odd ordinal time slots and even ordinal time slots of the class 2 channel to be empty.
In the above technical solution, preferably, the monitoring center sends a reset command to all base stations, the monitoring center and the base stations start counting with a standard clock, when the monitoring center counts to a preset time, a message is sent to the base stations, when the base stations receive the message, the count of the own counter at the moment is recorded as an uplink count, when the base stations count to the preset time, a message is sent to the monitoring center, when the monitoring center receives the message, the count of the own counter at the moment is recorded as a downlink count, the downlink count is sent to the corresponding base stations, and the base stations adjust the base number of the own counter according to the difference between the uplink count and the downlink count until the downlink count and the uplink count reach the same value, so as to realize time calibration of the current base station.
In the above technical solution, preferably, the mobile terminal performs clock synchronization and carrier frequency synchronization with the base station through a synchronization header of the downlink channel, and after synchronization is completed, the mobile terminal controls an instruction of the uplink channel through a clock counter synchronized with the base station to perform a corresponding action at a corresponding time; according to the difference of the distances between the mobile terminal and the base station, the mobile terminal sends data to the base station through a class 1 channel which does not need to avoid the time slot of the mobile terminal connected with the adjacent base station in an uplink channel when in a class 1 region, and sends data to the base station through a class 2 channel which does not need to avoid the time slot of the mobile terminal connected with the adjacent base station in the uplink channel when in a class 2 region; the uplink channel starts with a network access application channel, and when one base station and the adjacent base station do not accept the network access application of a new mobile terminal any more, the time slot occupied by the network access application channel can be removed from the uplink channel.
In the above technical solution, preferably, the modem includes an ARM CPU, an address attribute controller, a transmit time slot controller, a receive time slot controller, a control register, a memory, a digital modulator, a digital demodulator, and a radio frequency module; the ARM CPU, the transmitting time slot controller, the receiving time slot controller and the control register are connected with the memory through a data bus, the address attribute controller controls the attribution right of the memory, the ARM CPU stores received data in the memory, the transmitting time slot controller reads the data from the memory at a specific moment and sends the data to the digital modulator, and the digital modulator carries out OFDM modulation on the received data and sends the modulated data to the radio frequency module; the receiving time slot controller sends the data received by the radio frequency module to the digital demodulator, OFDM demodulation is carried out by the digital demodulator, the demodulated data is stored in the memory, and the ARM CPU reads the data from the memory and sends the data to the IP exchanger.
In the above technical solution, preferably, the digital modulator includes a PN Generator module, a Mapper module, a Carrier Control module, a Differential Encoder module, an iFFT module, a CP module, a MUX module, an FIR HB Filter module, a Farrow Filter module, a DUC module, and a Gain module;
when the transmitting time slot controller executes TxPN instruction, the PN Generator module generates synchronous header information, otherwise other time is in idle state, the Mapper module loads Tx_data Data to a modulation signal according to the requirement of Tx_Mod, the Carrier Control module determines whether to insert PILOT frequency subcarriers according to whether the number of the sub_CAR in the transmitting instruction is the same as the setting of an effective subcarrier number register, the Differential Encoder module is a differential encoder of a differential OFDM system, the iFFT module is used for inverse fast Fourier transform and is responsible for converting a frequency domain signal to a time domain to form an OFDM symbol, the CP module is responsible for adding cyclic prefix of OFDM symbols, when the instruction is TxPN instruction, the MUX module selects Data of a synchronous head circuit to be transmitted to a later module, when the instruction is OFDM or PILOT instruction, the FIR HB Filter module is used for increasing the Data sampling rate from 76MHz to 152MHz, the fall Filter module is used for interpolating and up-sampling a 152MHz clock sampling signal to 156.25MHz sampling rate, the DUC module is used for up-converting a baseband signal to an intermediate frequency signal, and finally the Gain module adjusts the Gain of a transmitting signal.
In the above technical solution, preferably, the digital demodulator includes an AGC module, a DCC module, a Farrow Filter module, an FIR HB Filter module, a DeMUX1 module, a PN core module, a PLL module, a coreformer module, an FFT module, a DeMUX2 module, a Differential Decoder module, a Channel & Carrier Estimation module, an equalzer module, a PHASOR module, a DeMapper module, a Post Proc module, and a Pilot Drop module;
the AGC module is a pulse width modulation generating circuit and is used for providing gain automatic control for a radio frequency receiving amplifier and adjusting a receiving signal to a preset amplitude, the DCC module is used for shifting the receiving signal to a fundamental frequency from the receiving signal, the Farrow Filter module and the FIR HB Filter module are respectively used for interpolating and downsampling a 156.25MHz clock sampling signal to a 152MHz sampling rate and reducing a data sampling rate to 76MHz, the DeMUX1 module selects different processing circuits according to the received instructions, the receiving data are transmitted to the PN processing circuits when the instructions are RxPN Start and RxPN Stop, the OFDM processing circuits are selected when the instructions are OFDM or PILOT, and in the PN processing circuits, the PN Correlate module is mainly responsible for synchronous head searching, and the module starts or ends synchronous head searching when the receiving time slot controller executes RxPN Start or RxPN Stop instructions; the PLL module provides a near working clock for the system, the PN corelate module synchronizes the working clock with the working clock of the base station at the later stage, and the corelate module in the OFDM circuit carries out correlation operation aiming at the first pilot symbol of the differential OFDM so as to eliminate ambiguity in the OFDM signal; the FFT module converts an OFDM signal in a time domain into a frequency domain, the DeMUX2 module and the Differential Decoder module respectively complete difference and decoding of the OFDM signal, the DeMUX3 module is a data separation controller, when the module executes PILOT, the Channel & Carrier Estimation module is selected to complete Channel and carrier frequency estimation, and when the module executes an OFDM instruction, the equizer module is selected to complete Channel equalization; considering that a certain carrier frequency deviation exists in the signal, the PHAOR module, the DeMapper module and the Post Proc module respectively complete phase rotation, judge received data to constellation points of a modulation signal and extract the task of frequency deviation information according to the phase difference of data before and after judgment, and finally the Pilot Drop module decides the insertion position of a Pilot subcarrier according to whether the sub_CAR value in a receiving instruction is the same as the setting of an effective subcarrier number register.
In the above technical solution, preferably, the specific process of clock synchronization and carrier frequency synchronization by the synchronization head includes a search process and a tracking process; in the searching process, setting the period of a frame length counter in a software setting mode before the position of the synchronous head is locked, recording the position of the maximum correlation peak and the amplitude of the corresponding correlation peak when the amplitude of the correlation peak is larger than a preset threshold, sending an interrupt request to an ARM CPU, and setting the zero clearing point of the frame length counter as the sum value position of the time interval between the maximum correlation peak and the time interval between the end point of the synchronous head and the end point of the frame after the ARM CPU receives the interrupt request; when the frame length counter reaches the zero clearing point, an interrupt request is sent to the ARM CPU, and the period of the frame length counter is set after the ARM CPU receives the interrupt request, so that the zero clearing point of the frame length counter is positioned at the position of the frame end point;
the tracking process comprises timing tracking and carrier frequency tracking, wherein in the timing tracking process, a main correlation peak and two side correlation peaks are obtained through a PN correlator, the timing error of a system clock is obtained through calculation, and the timing error is corrected through NCO adjustment; in carrier frequency tracking, carrier frequency offset information is detected by a PN correlator, an offset is calculated according to the carrier frequency offset information, and a correction amount is set back to a hardware circuit to correct carrier frequency offset.
Compared with the prior art, the invention has the beneficial effects that: based on PN synchronization, the FPGA and OFDM technology is utilized, a downlink channel, an uplink channel and a modem system are designed for the communication process between the mobile terminal and the base station, the asymmetric rates of the uplink and downlink channels are realized, the base station can automatically adjust the communication rate of each terminal according to the number of terminals which can be accessed, under the two conditions of moving towards the base station and moving away from the base station, the high-gain omnidirectional antenna has more advantages than the low-gain omnidirectional antenna, the single-tone signal can reflect fading depth more accurately than the bandwidth signal, and the seamless switching problem of the mobile terminal in the high-speed mobile communication process is solved.
Drawings
Fig. 1 is a schematic diagram of the overall structure of an FPGA-based high-speed mobile wireless communication system according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a data format of a downlink channel according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a data format of an uplink channel according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a frame format of an uplink channel according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a system design of a modem according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the basic structure of a digital modulator according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a basic structure of a digital demodulator according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a synchronization head according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of system correlation peaks disclosed in one embodiment of the present invention;
FIG. 10 is a schematic diagram illustrating the positions of test points of a foreign base station and a mobile terminal according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a mobile terminal side RSSI value moving towards a base station according to an embodiment of the present invention;
fig. 12 is a schematic diagram of a mobile terminal side RSSI value moving away from a base station according to an embodiment of the present invention;
fig. 13 is a schematic diagram of a base station side RSSI value moving toward a base station according to an embodiment of the present invention;
fig. 14 is a schematic diagram of a base station side RSSI value moving away from a base station according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention is described in further detail below with reference to the attached drawing figures:
as shown in fig. 1, a high-speed mobile wireless communication system based on FPGA according to the present invention includes: the system comprises a base station, a mobile terminal, a monitoring center and an optical fiber ring network; setting a base station at intervals of a preset distance along the optical fiber, forming a 2.5G synchronous ring network between the base stations through the optical fiber, connecting the base stations with a monitoring center, and performing broadband communication between the mobile terminal and the base stations; the timing synchronization and carrier synchronization are realized between the mobile terminal and the base station, the uplink rate and the downlink rate between the mobile terminal and the base station adopt an asymmetric mode with configurable uplink-downlink rate ratio, and the communication rate of each mobile terminal is automatically configured according to the number of mobile terminals which are simultaneously accessed into the base station; the base station coordinates with the adjacent base station to determine the communication modes of the downlink channel and the uplink channel between the base station and the mobile terminal, so that the mobile terminal can be smoothly switched between different base stations; the base station and the mobile terminal both comprise modems, the modems of the base station are connected with external equipment through an IP exchanger, and the modems of the mobile terminal are connected with the external equipment through a WiFi module.
In this embodiment, using an expressway as a typical case, an FPGA-based high-speed mobile wireless communication system is designed using FPGA and OFDM technology. Based on PN synchronization, the system designs a downlink channel, an uplink channel and a modem system specifically for the communication process between the mobile terminal and the base station, realizes asymmetric rates of the uplink and downlink channels, and the base station can automatically adjust the communication rate of each terminal according to the number of terminals which can be accessed.
Preferably, one wireless access device, i.e. a base station, is arranged every 2 km along the deployment scenario. The base stations form a 2.5G synchronous ring network through optical fibers and are connected with the road section monitoring center, each base station can simultaneously carry out broadband communication with a plurality of mobile terminals, and the mobile terminals can carry out seamless switching among coverage areas of base station equipment in the high-speed moving process. The communication between the mobile terminal and the base station adopts a 5.8G frequency band. The uplink (from terminal to base station) rate and the downlink (from base station to terminal) rate adopt asymmetric modes, the uplink is low, the downlink is high, and the uplink-downlink rate ratio can be configured. The number of terminals that each base station can access simultaneously is at most N, where N can be configured to be 32, 64, 128, etc., and the communication rate with each terminal can be automatically adjusted based on the number of terminals that are simultaneously accessed.
In the above embodiment, preferably, the base stations with odd numbers are defined as odd base stations and the base stations with even numbers are defined as even base stations according to the sequence from near to far between the base stations and the monitoring center. As shown in fig. 2, the data format of the downlink channel includes a synchronization header, a control 0 bit, a control 1 bit, a class 1 channel and a class 2 channel, and firstly, the timing synchronization and the carrier synchronization between the mobile terminal and the base station are realized through the synchronization header, and the control 0 bit and the control 1 bit not only indicate where the corresponding mobile terminal should extract data on the downlink channel, but also indicate where the corresponding mobile terminal should transmit data on the uplink channel. Specifically, even base stations transmit control information by using a control 0-bit time slot and control 1-bit time slot to be idle, and odd base stations transmit control information by using a control 1-bit time slot and control 0-bit time slot to be idle. If the mobile terminal is connected to an even base station, it is not only necessary to extract control information controlling the 0-bit slot, but also to monitor the 1-bit slot to determine whether it has entered the range of the next base station. The mobile terminal connected to the odd base station is associated with the even base station as described above. All time slots of the class 1 channel can be utilized by the base station, even base stations can only use even ordinal time slots and odd ordinal time slots of the class 2 channel to be empty, and odd base stations can only use odd ordinal time slots and even ordinal time slots of the class 2 channel to be empty. Each base station coordinates with the left and right two adjacent base stations to determine its allocation of class 1 and class 2 channels.
In the above embodiment, preferably, in order to achieve smooth handover of the mobile terminal between different base stations, good time synchronization needs to be maintained between the base stations, and the time calibration process is as follows: the monitoring center sends a reset command to all the base stations, the monitoring center and the base stations start to count by a standard clock, the monitoring center sends a message to the base stations when counting to 20 milliseconds, the base stations record the count of the own counter at the moment as an uplink count when receiving the message, the base stations send the message to the monitoring center when counting to 20 milliseconds, the monitoring center records the count of the own counter at the moment as a downlink count when receiving the message, the downlink count is sent to the corresponding base stations, and the base stations adjust the base numbers of the own counter according to the difference between the uplink count and the downlink count until the downlink count and the uplink count reach the same value, so that the time calibration of the current base stations is realized. The base station that completes the time calibration can transmit data through the downlink channel.
In the above embodiment, preferably, before transmitting data through an uplink channel, the mobile terminal performs clock synchronization and carrier frequency synchronization with the base station through a synchronization header of a downlink channel, and after synchronization is completed, the mobile terminal controls an instruction of the uplink channel through a clock counter synchronized with a frame period of the base station to perform a corresponding action at a corresponding time; according to the difference of the distance between the mobile terminal and the base station, the time delay of receiving the base station information is different, so that the base station needs to reserve a 6.7us interval when making uplink channel time slots of different mobile terminals. Similar to the class 1 and class 2 channels of the downlink channel, the uplink channel can also be divided into two classes: when a mobile terminal is in a class 1 region, it may transmit data to the base station using a class 1 channel, i.e., a channel whose time slot does not need to avoid the time slot of a mobile terminal connected to a neighboring base station. When a mobile terminal is in a class 2 region, it must transmit data to the base station using a class 2 channel, i.e., a time slot in which it needs to avoid the time slot of a mobile terminal connected to a neighboring base station.
As shown in fig. 3, the data format of the uplink channel may be different for each mobile terminal, and the uplink channel of each mobile terminal needs to have a synchronization header as a start, so that the base station can lock the position of the data segment by the synchronization header. The frame format of the uplink channel is shown in fig. 4, the uplink channel starts with the network access application channel, and when one base station and its adjacent base stations no longer accept the network access application of a new mobile terminal, the time slot occupied by the network access application channel can be removed from the uplink channel. The information carried by one frame of uplink channel is completely determined by the control information of the downlink channel, and contains uplink data of at most 64 mobile terminals.
As shown in fig. 5, in the above embodiment, preferably, the modem includes an ARM CPU, an address attribute controller, a transmission slot controller, a reception slot controller, a control register, a memory, a digital modulator, a digital demodulator, and a radio frequency module; the ARM CPU, the transmitting time slot controller, the receiving time slot controller and the control register are connected with the memory through a data bus, the address attribute controller controls the attribution right of the memory, the ARM CPU stores the data received through the 2.5G network at a certain position in the memory, the transmitting time slot controller reads the data from the memory at a specific moment and sends the data to the digital modulator, the digital modulator carries out OFDM modulation on the received data, and sends the modulated data to the radio frequency module to be transmitted through the antenna; the receiving time slot controller sends the data received by the radio frequency module to the digital demodulator, OFDM demodulation is carried out by the digital demodulator, the demodulated data is stored in the memory, and the ARM CPU reads the data from the memory and sends the data to the IP exchanger. The action instruction followed by the transmitting time slot controller and the receiving time slot controller is that the ARM CPU firstly puts the action instruction into a specific position of the memory. The transmit and receive slot controllers then sequentially read the instructions from memory and execute. Wherein the transmit time slot controller directs data to the digital modulator and thus to the antenna via the radio frequency module. And the receiving time slot controller receives the data demodulated by the digital demodulator and sends the data to the IP exchange module through the ARM CPU.
The difference between the mobile terminal modem and the base station modem is that the base station modem is connected with an IP switch, and the mobile terminal modem is connected with a WIFI device. Meanwhile, the standard clock of the base station is provided by a 2.5G network, the working clock of the mobile terminal is generated by the modem, and is adjusted according to the received synchronization head of the downlink channel, and finally synchronized to the standard clock of the base station. The IP exchange module (the mobile terminal is a WIFI module) and the modem are connected together through the ARM CPU via a bus.
As shown in fig. 6, in the above embodiment, the digital modulator preferably includes a PN Generator module, a Mapper module, a Carrier Control module, a Differential Encoder module, an iFFT module, a CP module, a MUX module, a FIR HB Filter module, a Farrow Filter module, a DUC module, and a Gain module;
when the TxPN instruction is executed by the transmitting time slot controller, the PN Generator module generates synchronous header information, otherwise, other time is in an idle state, the Mapper module loads Tx_Data Data to a modulation signal according to the requirement of Tx_Mod, the Carrier controller module determines whether PILOT subcarriers are inserted according to whether the sub_CAR value in the transmitting instruction is the same as the setting of an effective subcarrier number register, the Differential Encoder module is a differential encoder of a differential OFDM system, the iFFT module is used for fast Fourier inverse transformation and is responsible for converting a frequency domain signal to a time domain to form OFDM symbols, the CP module is responsible for adding a cyclic prefix of the OFDM symbols, when the instruction is TxPN instruction, the MUX module selects Data of the synchronous header circuit to be transmitted to a later module, when the instruction is OFDM or PILOT instruction, the FIR Filter module is used for increasing the Data sampling rate from 76MHz to 152MHz,Farrow Filter module and is used for interpolating and sampling 152MHz clock sampling signals to 156.25MHz sampling rate, the DUC module is used for up-converting signals to intermediate frequency signals, and finally the Gain of the transmitting module is adjusted to the baseband of the signal.
As shown in fig. 7, in the above embodiment, the digital demodulator preferably includes an AGC module, DCC module, farrow Filter module, FIR HB Filter module, deMUX1 module, PN corelate module, PLL module, coreactor module, FFT module, deMUX2 module, differential Decoder module, channel & Carrier Estimation module, equalzer module, PHAOR module, deMapper module, post Proc module, and Pilot Drop module;
the AGC module is a pulse width modulation generating circuit and is used for providing gain automatic control for a radio frequency receiving amplifier and adjusting a receiving signal to a preset amplitude, the DCC module is used for shifting the receiving signal to a fundamental frequency from the receiving signal, the Farrow Filter module and the FIR HB Filter module are respectively used for interpolating and downsampling a 156.25MHz clock sampling signal to 152MHz sampling rate and reducing the data sampling rate from 152MHz to 76MHz, the DeMUX1 module selects different processing circuits according to the received instructions, if the instructions are RxPN Start and RxPN Stop, the receiving data are transmitted to the PN processing circuits, when the instructions are OFDM or PILOT, the OFDM processing circuits are selected, in the PN processing circuits, the PN Correlate module is mainly responsible for synchronous head searching, and when a receiving time slot controller executes RxPN Start or RxPN Stop instructions, the module starts or ends synchronous head searching; the PLL and other modules provide a near working clock for the system, the working clock is synchronized with the working clock of the base station by the PN corelate module at the later stage, and the corelate module in the OFDM circuit carries out correlation operation on the first pilot symbol of the differential OFDM, so that the ambiguity in the OFDM signal is eliminated; the FFT module converts the OFDM signal in the time domain into the frequency domain, the DeMUX2 module and the Differential Decoder module respectively finish the difference and decoding of the OFDM signal, the DeMUX3 module is a data separation controller, when the module executes PILOT, the Channel & Carrier Estimation module is selected to finish Channel and carrier frequency estimation, but when the module executes an OFDM instruction, the Equalizer module is selected to finish Channel equalization; considering that a certain carrier frequency deviation exists in the signal, the PHAOR module, the DeMapper module and the Post Proc module respectively complete phase rotation, judge received data to constellation points of a modulation signal and extract the task of frequency deviation information according to the phase difference of data before and after judgment, and finally the Pilot Drop module decides the insertion position of a Pilot subcarrier according to whether the sub_CAR value in a receiving instruction is the same as the setting of an effective subcarrier number register.
In the above embodiment, it is preferable that the specific process of clock synchronization and carrier frequency synchronization by the synchronization head include a search process and a tracking process.
As shown in fig. 8, a frame structure of 20ms (1520000 clock widths) length based on a 76MHz clock is schematically shown. The data frame uses PN synchronous head as initial mark. The counter with a frame period of 76MHz clock counts from 0 to 1519999.
As shown in fig. 8, the time interval between the end point of the PN sync header and the end point of one frame is d=1519999-3079. To ensure that the hardware will always encounter a PN sync head within a period of time, the period of the frame length counter is set to 30ms by a software set method before the position of the PN sync head is locked. When the hardware judges that the amplitude value of the correlation peak is larger than the preset threshold, the hardware records the position x of the maximum correlation peak and the amplitude value of the corresponding correlation peak, and sends an interrupt request to the ARM CPU, and the ARM CPU sets the zero clearing point of the frame length counter as the sum value position of the time interval between the maximum correlation peak and the time interval between the synchronous head end point and the frame end point, namely x+d after receiving the interrupt request. When the frame length counter reaches the zero clearing point, an interrupt request is sent to the ARM CPU, the period of the frame length counter is set to be 20ms after the ARM CPU receives the interrupt request, namely, the zero clearing point of the frame length counter is set at the position of a frame end point 1519999, so that the PN synchronization head is structured as shown in fig. 8.
The tracking process comprises timing tracking and carrier frequency tracking, wherein the purpose of the timing tracking is to synchronize the working clock of the mobile terminal with the working clock of the base station; the carrier frequency tracking aims to synchronize the carrier frequency of the mobile terminal with the operating carrier frequency of the base station.
A schematic diagram of the system correlation peak during timing tracking is shown in fig. 9. Two non-zero points are respectively arranged at two sides of the main correlation peak, wherein the main correlation peak is a P (pulse) point; the correlation peak earlier than the P point is the E (early) point; the correlation peak later than point P is the point L (late). The correlation peak at P, E, L point is obtained by PN correlator and is recorded into corresponding register. The timing error of the system clock is calculated, and if the correlation peaks of the three points are respectively expressed as Punc_Corr, early_Corr and late_Corr, the timing error Terr of the system clock can be expressed as:
the timing error of the system clock can be converted to hertz Terr hz as follows:
Terr_hz＝Terr×(1/TF)×(RS/FS) (2)
where TF denotes the frame period, RS denotes the PN sequence symbol rate, and FS denotes the system clock frequency. Upon detection of a timing error, the software may correct the systematic deviation by adjusting the NCO.
In the carrier frequency tracking process, carrier frequency offset information is detected through a PN correlator, then software calculates offset according to the carrier frequency offset information, and correction amount is set back to a hardware circuit to correct carrier frequency offset. The software calculation process is as follows:
Assume that
And->
Then
Therefore, the phase difference α is
For small angle cases, the phase difference calculation may be approximated as
Assuming Δf is the carrier frequency offset, rs is the PN symbol rate, Δp is the phase per PN symbol, then
Since Lpn is the total length of the PN sequence, and α is +.>
The phase difference of the accumulation of the PN symbols, and thus the carrier frequency offset, can be calculated as follows:
considering that alpha needs not to exceed in order for the carrier frequency offset to be estimated with a certain accuracy
Thus->
In order to verify the reliability of the FPGA-based high-speed mobile wireless communication system proposed in the above embodiment, the base station is installed on the roof of the large roof building with the antenna aligned with the terminal test point selected in advance at 500m, and the location of the terminal test point is shown in fig. 10. The mobile cabinet terminal equipment, the antenna, the monitoring computer and the battery are placed on the bicycle to form a mobile test platform. Firstly, performing static alignment debugging on an antenna at a preset test point, enabling the maximum gain direction of the antenna of a base station to be aligned with the test point of the preset terminal, and then performing dynamic testing, namely, a tester circles back and forth along the riding cycle of a road, and simultaneously, in the process of the circle, the base station and the terminal respectively print RSSI values continuously (the RSSI values are separated by intervals not more than 0.1 ms). In the test environment, RSSI analysis is completed for the gain antenna and the signal of the terminal.
The antenna is set as a high-gain omnidirectional antenna, and meanwhile, fading depth test is carried out under the excitation of a bandwidth signal, and analysis is carried out by combining the two conditions of movement towards a base station and movement back to the base station.
As shown in fig. 11 and 12, the mobile terminal side data is analyzed, the linear trend of the RSSI value is gradually rising when moving toward the base station, and the trend is gradually falling when moving away from the base station, while the back movement is larger than the front movement in terms of standard deviation and maximum swing, and the back movement is smaller than the front movement in terms of average value.
As shown in fig. 13 and 14, the data on the base station side is analyzed, and the data trend is basically the same as the data trend on the mobile terminal side in fig. 11 and 12, but due to the RSSI data in the running steering process in fig. 14, the data has relatively large average value recess.
In order to analyze the influence of the gain antenna of the terminal, under the condition of ensuring the excitation of the bandwidth signal, a high-gain omni-directional antenna is selected to be compared with a low-gain omni-directional antenna, and the result is shown in the following table 1. In the aspect of average value, the signal intensity is larger in the direction away from the base station than in the direction towards the base station, and the difference is obvious, and the main reason is caused by the difference of the included angle between the maximum gain direction of the antenna and the incoming wave direction. In the aspect of standard deviation and swing amplitude, the value of the back motion direction is larger than that of the motion direction towards the base station, and the main reason is that when the back motion direction moves towards the base station, the included angle between the maximum gain direction of the omnidirectional antenna and the line-of-sight incoming wave direction is small, the gain of the line-of-sight incoming wave signal is high, and multipath scattered waves in other directions are restrained. The line-of-sight energy is much stronger than the multipath scattered wave, so the signal strength fluctuations due to fast fading are smaller. When the base station moves back, the included angle between the maximum gain direction of the omnidirectional antenna and the incoming wave direction is larger, the maximum gain direction is deviated, the gain is reduced, and the total signal intensity of the heat dissipation path is increased due to the fact that part of the heat dissipation path is in the maximum gain direction. The line-of-sight incoming wave main signal strength is reduced and the heat dissipation path signal is enhanced as compared to moving toward the base station, the strong difference between the main signal and the signal of the scattering path becomes smaller, resulting in a larger fluctuation in the signal strength of the fast fading. In contrast to the two types of antennas, the standard deviation of the high gain antenna is slightly larger than that of the low gain antenna on the base station side in the case of movement toward the base station, but the standard deviation of the low gain antenna is significantly larger than that of the high gain antenna on the terminal side. In the case of movement away from the base station, the standard deviation of the two types of antennas on the base station side is not greatly different, but the standard deviation of the low-gain antenna on the terminal side is significantly larger than that of the high-gain antenna. Thus, in combination, a high gain antenna is slightly superior to a low gain antenna, and the main reason is that the angle change is severe due to the swing of the antenna during the motion process, and the gain change caused by the angle change is added, so that the received energy is changed.
Table 1 comparison of different gain antenna dynamic RSSI
In order to analyze the influence of the signal selection of the terminal, the bandwidth signal is selected to be compared with the bass signal while ensuring a low gain antenna, and the results are shown in table 2 below. In terms of standard deviation and swing, the value of the back-to-motion direction is larger than that of the motion direction of the base station, and specific reasons are described in the above-mentioned analysis of the gain antenna of the mobile terminal. The maximum swing and standard deviation of the single-tone signal are larger than those of the bandwidth signal, so that the single-tone signal can measure the actual fading depth more. The main reason for this is that for a bandwidth signal, at a certain time, the different frequency fades are not identical. Whereas RSSI is the energy in the statistical band (the density product of all frequency components in the band), thus masking the actual frequency selective fading depth. However, the single-tone signal has more concentrated energy than the wide-tone signal, so that once the deep fading of the frequency point occurs, the RSSI can be accurately reflected.
Table 2 comparison of single tone bandwidth signal RSSI
According to the FPGA-based high-speed mobile wireless communication system provided in the above embodiment, the above test shows that not only can simultaneous access of a plurality of terminals be achieved, but also the communication rate of the terminals can be automatically adjusted according to the number of the accessed terminals. In the system test stage, the maximum swing, standard deviation and average value of the two conditions of the movement of the terminal towards the base station and the movement of the terminal back to the base station are analyzed, the single-tone bandwidth signal RSSI is compared, and the problem of seamless switching of the mobile terminal in the high-speed mobile communication process is solved.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A FPGA-based high-speed mobile wireless communications system, comprising: the system comprises a base station, a mobile terminal, a monitoring center and an optical fiber ring network;
setting a base station at intervals of a preset distance along an optical fiber, forming a 2.5G synchronous ring network between the base stations through the optical fiber, connecting the base stations with the monitoring center, and performing broadband communication between the mobile terminal and the base stations;
the timing synchronization and the carrier synchronization are realized between the mobile terminal and the base station, and an asymmetric mode capable of configuring uplink and downlink rate ratios is adopted for uplink and downlink rates between the mobile terminal and the base station, and the communication rate of each mobile terminal is automatically configured according to the number of mobile terminals simultaneously connected to the base station;
the base station coordinates with the adjacent base station to determine the communication modes of the downlink channel and the uplink channel between the base station and the mobile terminal, so as to realize smooth switching of the mobile terminal between different base stations;
The base station and the mobile terminal both comprise modems, the modems of the base station are connected with external equipment through an IP exchanger, and the modems of the mobile terminal are connected with the external equipment through a WiFi module;
according to the sequence from near to far of the distance between the base station and the monitoring center, defining odd-numbered base stations as odd base stations and even-numbered base stations as even base stations;
the data format of the downlink channel comprises a synchronous head, a control 0 bit, a control 1 bit, a class 1 channel and a class 2 channel, the timing synchronization and the carrier synchronization between the mobile terminal and the base station are realized through the synchronous head, the even base station transmits control information and controls 1 bit time slot idling by using the control 0 bit time slot, and the odd base station transmits control information and controls 0 bit time slot idling by using the control 1 bit time slot;
all time slots of the class 1 channel can be utilized by the base station, even base stations can only use even ordinal time slots and odd ordinal time slots of the class 2 channel to be empty, and odd base stations can only use odd ordinal time slots and even ordinal time slots of the class 2 channel to be empty.
2. The FPGA-based high-speed mobile wireless communication system according to claim 1, wherein the monitoring center issues a reset command to all base stations, the monitoring center and the base stations start counting with a standard clock, the monitoring center transmits a message to the base stations when counting up to a preset time, the base stations record the count of own counter at this time as an up count when receiving the message, the base stations transmit a message to the monitoring center when counting up to a preset time, the monitoring center records the count of own counter at this time as a down count when receiving the message, and transmits the down count to the corresponding base stations, and the base stations adjust the base number of own counter according to the difference between the up count and the down count until the down count and the up count reach the same value, so as to realize the time calibration of the current base station.
3. The FPGA-based high-speed mobile wireless communication system according to claim 2, wherein the mobile terminal performs clock synchronization and carrier frequency synchronization with the base station through the synchronization header of the downlink channel, and after synchronization is completed, the mobile terminal controls an instruction of an uplink channel through a clock counter synchronized with the base station to perform a corresponding action at a corresponding time;
according to the difference of the distances between the mobile terminal and the base station, the mobile terminal sends data to the base station through a class 1 channel which does not need to avoid the time slot of the mobile terminal connected with the adjacent base station in an uplink channel when in a class 1 region, and sends data to the base station through a class 2 channel which does not need to avoid the time slot of the mobile terminal connected with the adjacent base station in the uplink channel when in a class 2 region;
the uplink channel starts with a network access application channel, and when one base station and the adjacent base station do not accept the network access application of a new mobile terminal any more, the time slot occupied by the network access application channel can be removed from the uplink channel.
4. The FPGA-based high-speed mobile wireless communication system of claim 1, wherein the modem comprises an ARM CPU, an address attribute controller, a transmit slot controller, a receive slot controller, a control register, a memory, a digital modulator, a digital demodulator, and a radio frequency module;
The ARM CPU, the transmitting time slot controller, the receiving time slot controller and the control register are connected with the memory through a data bus, the address attribute controller controls the attribution right of the memory, the ARM CPU stores received data in the memory, the transmitting time slot controller reads the data from the memory at a specific moment and sends the data to the digital modulator, and the digital modulator carries out OFDM modulation on the received data and sends the modulated data to the radio frequency module;
the receiving time slot controller sends the data received by the radio frequency module to the digital demodulator, OFDM demodulation is carried out by the digital demodulator, the demodulated data is stored in the memory, and the ARM CPU reads the data from the memory and sends the data to the IP exchanger.
5. The FPGA-based high-speed mobile wireless communication system of claim 4, wherein the digital modulator comprises a PN Generator module, a Mapper module, a Carrier Control module, a Differential Encoder module, an ift module, a CP module, a MUX module, a FIR HB Filter module, a Farrow Filter module, a DUC module, and a Gain module;
When the transmitting time slot controller executes a TxPN instruction, the PN Generator module generates synchronous header information, otherwise, other time is in an idle state, the Mapper module loads Tx_Data Data to a modulation signal according to the requirement of Tx_Mod, the Carrier Control module determines whether pilot frequency subcarriers are inserted or not according to the fact that the number of the sub_CAR in the transmitting instruction is the same as the setting of an effective subcarrier number register, the Differential Encoder module is a differential encoder of a differential OFDM system, and the iFFT module is used for performing inverse fast Fourier transform and is responsible for converting a frequency domain signal to a time domain to form an OFDM symbol;
the CP module is responsible for adding a cyclic prefix of an OFDM symbol, when the instruction is a TxPN instruction, the MUX module selects data of a synchronous head circuit to be transmitted to a later module, and when the instruction is an OFDM or PILOT instruction, the MUX module selects data of the OFDM circuit;
the FIR HB Filter module is used for increasing the data sampling rate from 76MHz to 152MHz, the Farrow Filter module is used for interpolating and up-sampling the 152MHz clock sampling signal to 156.25MHz sampling rate, the DUC module is used for up-converting the baseband signal to the intermediate frequency signal, and finally the Gain module adjusts the Gain of the transmitting signal.
6. The FPGA-based high-speed mobile wireless communication system of claim 4, wherein the digital demodulator comprises an AGC module, DCC module, farrow Filter module, FIR HB Filter module, deMUX1 module, PN corelate module, PLL module, corelate module, FFT module, deMUX2 module, differential Decoder module, channel & Carrier Estimation module, equalzer module, PHAOR module, deMapper module, post Proc module, and Pilot Drop module;
the AGC module is a pulse width modulation generating circuit and is used for providing gain automatic control for a radio frequency receiving amplifier and adjusting a receiving signal to a preset amplitude, the DCC module is used for shifting the receiving signal to a fundamental frequency from the receiving signal, the Farrow Filter module and the FIR HB Filter module are respectively used for interpolating and downsampling a 156.25MHz clock sampling signal to a 152MHz sampling rate and reducing a data sampling rate to 76MHz, the DeMUX1 module selects different processing circuits according to the received instructions, the receiving data are transmitted to the PN processing circuits when the instructions are RxPN Start and RxPN Stop, the OFDM processing circuits are selected when the instructions are OFDM or PILOT, and in the PN processing circuits, the PN Correlate module is mainly responsible for synchronous head searching, and the module starts or ends synchronous head searching when the receiving time slot controller executes RxPN Start or RxPN Stop instructions;
The PLL module provides a near working clock for the system, the PN corelate module synchronizes the working clock with the working clock of the base station at the later stage, and the corelate module in the OFDM circuit carries out correlation operation aiming at the first pilot symbol of the differential OFDM so as to eliminate ambiguity in the OFDM signal;
the FFT module converts an OFDM signal in a time domain into a frequency domain, the DeMUX2 module and the Differential Decoder module respectively complete difference and decoding of the OFDM signal, the DeMUX3 module is a data separation controller, when the module executes PILOT, the Channel & Carrier Estimation module is selected to complete Channel and carrier frequency estimation, and when the module executes an OFDM instruction, the equizer module is selected to complete Channel equalization;
considering that a certain carrier frequency deviation exists in the signal, the PHAOR module, the DeMapper module and the Post Proc module respectively complete phase rotation, judge received data to constellation points of a modulation signal and extract the task of frequency deviation information according to the phase difference of data before and after judgment, and finally the Pilot Drop module decides the insertion position of a Pilot subcarrier according to whether the sub_CAR value in a receiving instruction is the same as the setting of an effective subcarrier number register.
7. A FPGA-based high speed mobile radio communication system according to claim 1 or 3, wherein the specific process of clock synchronization and carrier frequency synchronization by the synchronization head comprises a search process and a tracking process;
in the searching process, setting the period of a frame length counter in a software setting mode before the position of the synchronous head is locked, recording the position of the maximum correlation peak and the amplitude of the corresponding correlation peak when the amplitude of the correlation peak is larger than a preset threshold, sending an interrupt request to an ARM CPU, and setting the zero clearing point of the frame length counter as the sum value position of the time interval between the maximum correlation peak and the time interval between the end point of the synchronous head and the end point of the frame after the ARM CPU receives the interrupt request;
when the frame length counter reaches the zero clearing point, an interrupt request is sent to the ARM CPU, and the period of the frame length counter is set after the ARM CPU receives the interrupt request, so that the zero clearing point of the frame length counter is positioned at the position of the frame end point;
the tracking process comprises timing tracking and carrier frequency tracking, wherein in the timing tracking process, a main correlation peak and two side correlation peaks are obtained through a PN correlator, the timing error of a system clock is obtained through calculation, and the timing error is corrected through NCO adjustment;
in carrier frequency tracking, carrier frequency offset information is detected by a PN correlator, an offset is calculated according to the carrier frequency offset information, and a correction amount is set back to a hardware circuit to correct carrier frequency offset.
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Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1197358A (en) * | 1997-01-21 | 1998-10-28 | 诺基亚流动电话有限公司 | Apparatus and method for configuring data channel for symmetric/asymmetric data transmission |
| CN1750702A (en) * | 2004-09-13 | 2006-03-22 | 大唐移动通信设备有限公司 | Method for flexibly supporting asymmetric service of multiple carrier time division duplex mobiole communication system |
| KR20060032466A (en) * | 2004-10-12 | 2006-04-17 | 삼성전자주식회사 | System and method for hand-over of mobile terminal in broadbnad wireless access communication system |
| CN101051858A (en) * | 2007-05-21 | 2007-10-10 | 中兴通讯股份有限公司 | Method for realizing asymmetric service in broad band radio communication system |
| CN101378343A (en) * | 2008-03-07 | 2009-03-04 | 华中科技大学 | System and method for implementing speedway vehicle wideband communication |
| CN101485135A (en) * | 2006-07-05 | 2009-07-15 | 皇家飞利浦电子股份有限公司 | Bandwidth asymmetric communication system based on OFDM and TDMA |
| CN101594653A (en) * | 2008-04-14 | 2009-12-02 | 日立通讯技术株式会社 | Method for handover control in wireless terminal and base station control station and the wireless communication system |
| JP2010130494A (en) * | 2008-11-28 | 2010-06-10 | Toshiba Corp | Mobile communication terminal and base station switching method |
| CN101754477A (en) * | 2008-11-28 | 2010-06-23 | 北京大学 | Communication system volume expansion method |
| CN101868054A (en) * | 2010-05-07 | 2010-10-20 | 武汉邮电科学研究院 | Improved distribution-type base station architecture and realization method |
| CN103051385A (en) * | 2013-01-06 | 2013-04-17 | 北京邮电大学 | Integral wired-wireless optical fiber asymmetric full-duplex access method and system |
| CN103220739A (en) * | 2013-04-22 | 2013-07-24 | 深圳格兰泰克科技有限公司 | System and method of rail transport vehicle ground wireless communication |
| WO2013151158A1 (en) * | 2012-04-06 | 2013-10-10 | 株式会社エヌ・ティ・ティ・ドコモ | Communication system, local area base station device, mobile communication terminal, and communication method |
| CN103873418A (en) * | 2014-03-21 | 2014-06-18 | 西安电子科技大学 | Full-duplex orthogonal frequency division communication method for large-scale antenna system |
| CN106888467A (en) * | 2017-02-20 | 2017-06-23 | 电子科技大学 | A kind of high ferro WIFI systems based on millimeter wave |
-
2020
- 2020-09-09 CN CN202010940778.6A patent/CN112073354B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1197358A (en) * | 1997-01-21 | 1998-10-28 | 诺基亚流动电话有限公司 | Apparatus and method for configuring data channel for symmetric/asymmetric data transmission |
| CN1750702A (en) * | 2004-09-13 | 2006-03-22 | 大唐移动通信设备有限公司 | Method for flexibly supporting asymmetric service of multiple carrier time division duplex mobiole communication system |
| KR20060032466A (en) * | 2004-10-12 | 2006-04-17 | 삼성전자주식회사 | System and method for hand-over of mobile terminal in broadbnad wireless access communication system |
| CN101485135A (en) * | 2006-07-05 | 2009-07-15 | 皇家飞利浦电子股份有限公司 | Bandwidth asymmetric communication system based on OFDM and TDMA |
| CN101051858A (en) * | 2007-05-21 | 2007-10-10 | 中兴通讯股份有限公司 | Method for realizing asymmetric service in broad band radio communication system |
| CN101378343A (en) * | 2008-03-07 | 2009-03-04 | 华中科技大学 | System and method for implementing speedway vehicle wideband communication |
| CN101594653A (en) * | 2008-04-14 | 2009-12-02 | 日立通讯技术株式会社 | Method for handover control in wireless terminal and base station control station and the wireless communication system |
| JP2010130494A (en) * | 2008-11-28 | 2010-06-10 | Toshiba Corp | Mobile communication terminal and base station switching method |
| CN101754477A (en) * | 2008-11-28 | 2010-06-23 | 北京大学 | Communication system volume expansion method |
| CN101868054A (en) * | 2010-05-07 | 2010-10-20 | 武汉邮电科学研究院 | Improved distribution-type base station architecture and realization method |
| WO2013151158A1 (en) * | 2012-04-06 | 2013-10-10 | 株式会社エヌ・ティ・ティ・ドコモ | Communication system, local area base station device, mobile communication terminal, and communication method |
| CN103051385A (en) * | 2013-01-06 | 2013-04-17 | 北京邮电大学 | Integral wired-wireless optical fiber asymmetric full-duplex access method and system |
| CN103220739A (en) * | 2013-04-22 | 2013-07-24 | 深圳格兰泰克科技有限公司 | System and method of rail transport vehicle ground wireless communication |
| CN103873418A (en) * | 2014-03-21 | 2014-06-18 | 西安电子科技大学 | Full-duplex orthogonal frequency division communication method for large-scale antenna system |
| CN106888467A (en) * | 2017-02-20 | 2017-06-23 | 电子科技大学 | A kind of high ferro WIFI systems based on millimeter wave |
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