CN112072916A - Buck-boost controller based on current mode - Google Patents
Buck-boost controller based on current mode Download PDFInfo
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- CN112072916A CN112072916A CN202011275952.6A CN202011275952A CN112072916A CN 112072916 A CN112072916 A CN 112072916A CN 202011275952 A CN202011275952 A CN 202011275952A CN 112072916 A CN112072916 A CN 112072916A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1582—Buck-boost converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/1566—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
A buck-boost controller based on current mode, comprising: the drain electrode of the first switching tube is connected with a VIN input signal, the grid electrode of the first switching tube is connected with a DRV1 signal of the controller, and the source electrode of the first switching tube is connected with the drain electrode of the second switching tube; the drain electrode of the third switching tube is connected with a VOUT output signal, the gate electrode of the third switching tube is connected with a DRV3 signal of the controller, and the source electrode of the third switching tube is connected with the drain electrode of the fourth switching tube; the source electrode of the second switch tube and the source electrode of the fourth switch tube are connected with a current sampling resistor, and the grid electrode of the second switch tube is connected with a DRV2 signal of the controller; the grid electrode of the fourth switching tube is connected with a DRV4 signal of the controller, and smooth seamless switching from boosting to buck-boost to boosting modes is achieved.
Description
Technical Field
The invention relates to the field of buck-boost converters, in particular to a buck-boost controller based on a current mode.
Background
A typical configuration of a four-switch buck-boost converter is: the controller provides periodic PWM control signals and the driver drives the four switches and the inductor and output capacitor, respectively.
Various architectures exist to implement the controller functions, such as peak current mode, average current mode. However, the boost-buck converters with various architectures are difficult to realize seamless switching between boost and buck, even four switching tubes are switched in one period, and dynamic loss of the switches is more.
It can be seen that there are a number of problems with the prior art.
Disclosure of Invention
Therefore, in order to solve the above problems in the prior art, the present invention provides a buck-boost controller based on a current mode.
The invention solves the problems through the following technical means:
a buck-boost controller based on current mode, comprising: a controller, a voltage feedback loop and a current sampling circuit;
the controller outputs DRV1 signals, DRV2 signals, DRV3 signals and DRV4 signals, the voltage feedback loop comprises a first switching tube, a second switching tube, a third switching tube and a fourth switching tube, the drain electrode of the first switching tube is connected with VIN input signals, the grid electrode of the first switching tube is connected with the DRV1 signals of the controller, and the source electrode of the first switching tube is connected with the drain electrode of the second switching tube; the drain electrode of the third switching tube is connected with a VOUT output signal, the gate electrode of the third switching tube is connected with a DRV3 signal of the controller, and the source electrode of the third switching tube is connected with the drain electrode of the fourth switching tube; the source electrode of the second switch tube and the source electrode of the fourth switch tube are connected with a current sampling resistor, and the grid electrode of the second switch tube is connected with a DRV2 signal of the controller; the grid electrode of the fourth switching tube is connected with a DRV4 signal of the controller; the drain electrode of the third switching tube is connected in series with a first resistor and a second resistor in parallel and is connected to an output voltage feedback signal VFB, and the voltage feedback signal VFB is output to the controller;
an induction coil is connected between the source of the first switching tube and the source of the third switching tube in series, the source of the first switching tube and the drain of the second switching tube are connected with one end of the induction coil, and the source of the third switching tube and the drain of the fourth switching tube are connected with the other end of the induction coil;
an input capacitor is connected in parallel between the VIN input signal and the drain electrode of the first switch tube, and the other end of the input capacitor is grounded; an output capacitor is connected in parallel between the VOUT output signal and the drain of the third switch tube, and the other end of the output capacitor is grounded.
Further, the controller includes:
EA operational amplifier circuit, is used for outputting PWMBCK signal and PWMBST signal;
a BUCK BUCK logic circuit for outputting a DRV1 signal and a DRV2 signal;
a BOOST logic circuit for outputting a DRV3 signal and a DRV4 signal;
and the STATE STATE detection circuit is used for outputting the BOOSTM signal.
Furthermore, the BUCK BUCK logic circuit, the BOOST BOOST logic circuit and the STATE STATE detection circuit are all connected with a clock CLK signal.
Further, the BUCK logic circuit includes: the first and gate, the second and gate, the first or gate, the second or gate, the third or gate, the first RS trigger, the second RS trigger, the first driver and the second driver;
the PWMBCK signal and the BOOSTMB voltage reduction state signal are jointly accessed into a first AND gate, the PWMBCK signal and the BOOSTMB voltage reduction state signal are accessed into a first OR gate together with a rising edge signal of the BOOSTM voltage increase state signal, and the output of the first OR gate is accessed into the S end of a first RS trigger; the clock CLK signal and the BOOSTMB voltage reduction state signal are accessed into a second AND gate, and are accessed into the R end of the first RS trigger after being output; the Q output end of the first RS trigger and the BOOSTM boosting state signal synchronous with the result clock pass through a second OR gate and then are connected with a first driver to output a DRV1 signal, and a DRV1 signal is connected with the grid electrode of the first switching tube; the DRV1 signal is processed by a falling edge and then is connected with the S end of the second RS trigger; after the DRV1 signal is processed by a rising edge and the BUCKZCD signal passes through a third OR gate, the output of the third OR gate is connected with the R end of a second RS trigger, the output end Q of the second RS trigger is connected with a second driver, the second driver outputs a DRV2 signal, and the DRV2 signal is connected with the grid electrode of a second switch tube Q2.
Further, the BOOST logic circuit includes: the first and second and third and fourth and fifth or gates, a first RS trigger, a first driver and a first driver;
the clock CLK signal and the BOOSTM signal are accessed to the S end of the third RS trigger after passing through the third AND gate, and the PWMBST signal and the BOOSTM signal are accessed to the R end of the third RS trigger after passing through the fourth AND gate; the Q output end of the third RS trigger is connected with a fourth driver, the fourth driver outputs a DRV4 signal, and a DRV4 signal is connected with the grid electrode of a fourth switching tube Q4; the Q non-output end of the third trigger is connected to the S end of a fourth RS trigger through rising edge detection, a DRV4 signal and a BOOSTZCD signal are input to the R end of the fourth RS trigger after passing through a fourth OR gate, the Q output end of the fourth RS trigger and a BOOSTMB signal which is subjected to clock synchronization are output to a third driver after passing through a fifth OR gate, the third driver outputs a DRV3 signal, and the DRV3 signal is connected with the grid electrode of a third switching tube Q3.
Further, the STATE detection circuit includes: the system comprises a MIN-OFF timer, a MIN-ON timer, a first D trigger, a second D trigger, a fifth RS trigger, a fifth AND gate and a sixth AND gate;
a clock CLK signal is sent to a clock end of a first D trigger through an MIN-OFF timer, a DRV2 signal is sent to a data end of the first D trigger after being negated, and an output end of the first D trigger and a BOOSTMB voltage reduction state signal are sent to an S end of a fifth RS trigger after passing through a fifth AND gate; the clock CLK signal is sent to the clock end of the second D trigger through an MIN-ON timer, the DRV4 signal is sent to the data end of the second D trigger after being negated, the output end of the second D trigger and the BOOSTM voltage boosting state signal are sent to the R end of the fifth RS trigger through the sixth AND gate, the Q output of the fifth RS trigger is the BOOSTM voltage boosting state signal, and the Q negated is the BOOSTMB voltage reducing state signal.
Compared with the traditional buck-boost controller, the invention realizes the reduction of dynamic loss, and can adjust the time of MIN-ON and MIN-OFF aiming at different working frequencies, thereby realizing the smooth and seamless switching from boost to buck-boost to boost modes.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a buck-boost controller based on a current mode according to the present invention.
Fig. 2 is a structural block diagram of a controller in a buck-boost controller based on a current mode according to the present invention.
Fig. 3 is a schematic waveform diagram of a buck-boost controller operating in a buck mode based on a current mode according to the present invention.
Fig. 4 is a schematic waveform diagram of a boost-buck controller operating in a boost mode based on a current mode according to the present invention.
Fig. 5 is a schematic waveform diagram of a buck-boost controller based on a current mode according to the present invention when the buck-boost controller operates in a buck-boost critical state.
Fig. 6 is a schematic waveform diagram of a buck-boost controller based on a current mode when the buck-boost controller works in a buck-boost critical state.
Reference numerals
1-a first switch tube; 2-a second switch tube; 3-a third switching tube;
4-a fourth switching tube; 5-a first resistance; 6-a second resistance;
7-current sampling resistance.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It should be noted that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and all other embodiments obtained by those skilled in the art without any inventive work are within the scope of the present invention.
Examples
Referring to fig. 1, fig. 1 shows a buck-boost converter composed of a controller, a voltage feedback circuit and a current sampling circuit, the buck-boost converter mainly includes two parts, namely a core controller and a voltage current feedback loop cooperating with the core controller, the controller outputs a DRV1 signal, a DRV2 signal, a DRV3 signal and a DRV4 signal, the voltage feedback loop includes a first switch tube 1, a second switch tube 2, a third switch tube 3 and a fourth switch tube 4, a drain of the first switch tube 1 is connected to a VIN input signal, a gate of the first switch tube 1 is connected to a DRV1 signal of the controller, and a source of the first switch tube 1 is connected to a drain of the second switch tube 2; the drain of the third switching tube 3 is connected with a VOUT output signal, the gate of the third switching tube 3 is connected with a DRV3 signal of the controller, and the source of the third switching tube 3 is connected with the drain of the fourth switching tube 4; the source electrode of the second switch tube 2 and the source electrode of the fourth switch tube 4 are connected with a current sampling resistor 7, and the grid electrode of the second switch tube 2 is connected with a DRV2 signal of the controller; the grid of the fourth switch tube 4 is connected with a DRV4 signal of the controller; the drain of the third switching tube 3 is connected in series with the first resistor 5 and the second resistor 6 in parallel to output a voltage feedback signal VFB, and the voltage feedback signal VFB is output to the controller.
An induction coil is connected in series between the source of the first switch tube 1 and the source of the third switch tube 3, the source of the first switch tube 1 and the drain of the second switch tube 2 are connected with one end of the induction coil, and the source of the third switch tube 3 and the drain of the fourth switch tube 4 are connected with the other end of the induction coil.
An input capacitor is connected in parallel between the VIN input signal and the drain of the first switch tube 1, and the other end of the input capacitor is grounded; an output capacitor is connected between the output signal VOUT and the drain of the third switching tube 3 in parallel, and the other end of the output capacitor is grounded.
Preferably, the controller includes: EA operational amplifier circuit, is used for outputting PWMBCK signal and PWMBST signal; a BUCK BUCK LOGIC circuit (BUCK LOGIC) for outputting a DRV1 signal and a DRV2 signal; a BOOST logic circuit for outputting a DRV3 signal and a DRV4 signal; and the STATE STATE detection circuit is used for outputting BOOSTM signals (including BOOSTM boost STATE signals and BOOSTMB buck STATE signals).
Referring to fig. 2, fig. 2 shows a schematic structural diagram of a core controller circuit, the core controller circuit includes an EA operational amplifier circuit, EA outputs are connected with a compensation circuit, and then connected with input terminals of a BUCK comparator and a BOOST comparator respectively, current samples are respectively sent to the BUCK comparator and the BOOST comparator, the BUCK comparator outputs a PWMBCK signal, the BOOST comparator outputs a PWMBST signal, the PWMBCK signal is sent to a BUCK LOGIC circuit, and the PWMBST signal is sent to the BOOST LOGIC circuit.
The BUCK BUCK logic circuit includes: the BUCK BUCK logic circuit is also connected with a fixed clock CLK signal, a BOOSTMB BUCK state signal and a BOOSTM boost state signal, the PWMBCK signal and the BOOSTMB BUCK state signal are connected into the first AND gate together, and are connected into the first OR gate together with a rising edge signal of the BOOSTM boost state signal, and the output of the first OR gate is connected into the S end of the first RS trigger; the clock CLK signal and the BOOSTMB voltage reduction state signal are accessed into a second AND gate, and are accessed into the R end of the first RS trigger after being output; the Q output end of the first RS trigger and the BOOSTM boosting state signal synchronous with the result clock pass through a second OR gate and then are connected with a first driver to output a DRV1 signal, and the DRV1 signal is connected with the grid electrode of the first switch tube 1; the DRV1 signal is processed by a falling edge and then is connected with the S end of the second RS trigger; after the DRV1 signal is processed by the rising edge and the BUCKZCD signal passes through the third OR gate, the output end of the DRV1 signal is connected with the R end of the second RS trigger, the output end Q of the second RS trigger is connected with the second driver, the second driver outputs a DRV2 signal, and the DRV2 signal is connected with the grid electrode of the second switch tube 2.
Fig. 3 shows an operation waveform diagram of the BUCK LOGIC control circuit, when the controller operates in the BUCK mode, the boost signal is high, the rising edge of the clock CLK signal triggers the first RS flip-flop first, the output of the flip-flop is low, the DRV1 signal goes low, the first switch transistor 1 is turned off, after the DRV1 signal goes low, the falling edge triggers the second RS flip-flop, the output is high, the DRV2 signal goes high, the gate of the second switch transistor 2 goes high, the second switch transistor 2 is turned on, when the boost signal is high, the DRV3 signal is constantly high, the third switch transistor 3 is always turned on, the DRV4 signal is constantly low, and the fourth switch transistor 4 is always turned off.
The above conditions are continued until the BUCK comparator PWMBCK signal is output to be high, the first RS flip-flop is set, the output is high, the DRV1 signal is high, the first switch tube 1 is opened, the DRV1 rising edge is triggered, the DRV is input into the second RS flip-flop, the output of the second RS flip-flop is low, the DRV2 signal is low, the second switch tube 2 is closed, the next CLK rising edge is reached, and one period is ended.
The BOOST logic circuit comprises: the first and second and third and fourth and fifth or gates, a first RS trigger, a first driver and a first driver; the BOOST BOOST logic circuit is connected with a PWMBST, a BOOSTM BOOST state signal, a BOOSTMB buck state signal and a clock CLK signal, the clock CLK signal and the BOOSTM signal are connected to the S end of the third RS trigger after passing through a third AND gate, and the PWMBST signal and the BOOSTM signal are connected to the R end of the third RS trigger after passing through a fourth AND gate; the Q output end of the third RS trigger is connected with a fourth driver, the fourth driver outputs a DRV4 signal, and a DRV4 signal is connected with the grid electrode of the fourth switching tube 4; the Q non-output end of the third trigger is connected to the S end of a fourth RS trigger through rising edge detection, a DRV4 signal and a BOOSTZCD signal are input to the R end of the fourth RS trigger after passing through a fourth OR gate, the Q output end of the fourth RS trigger and a BOOSTMB signal which is subjected to clock synchronization are output to a third driver after passing through a fifth OR gate, the third driver outputs a DRV3 signal, and the DRV3 signal is connected with the grid electrode of a third switching tube 3.
FIG. 4 shows a waveform diagram of the operation of the BOOST LOGIC control circuit, when the controller operates in the BOOST BOOST mode, the BOOSTM signal is high, first, the rising edge of CLK triggers the third RS flip-flop, the output of the flip-flop is high, the DRV4 signal is high, and the fourth switch tube 4 is turned on; the DRV4 signal is high, after the rising edge triggers, the fourth RS flip-flop is triggered, the output of the fourth RS flip-flop is low, the DRV3 signal goes low, the third switch tube 3 is closed, when the boost tm is in a high state, the DRV1 signal is constantly high, the first switch tube 1 is always open, the DRV2 signal is constantly low, and the second switch tube 2 is always closed.
The above condition is continued until the PWMBST signal turns over to trigger the end R of the third RS flip-flop, the output of the third RS flip-flop is low, the DRV4 signal goes low, the fourth switch tube 4 is closed, meanwhile, the output of the non-end Q of the third RS flip-flop goes high, after the rising edge is triggered, the fourth RS flip-flop is triggered, the output of the flip-flop is high, the DRV3 signal goes high, the third switch tube 3 is opened, and the operation is continued until the next CLK clock arrives, and one cycle is ended.
The above core controller further comprises an STATE DETETCT status detection circuit, and the STATE status detection circuit includes: the system comprises a MIN-OFF timer, a MIN-ON timer, a first D trigger, a second D trigger, a fifth RS trigger, a fifth AND gate and a sixth AND gate; the input signals are a clock CLK signal, a DRV2 signal and a DRV4 signal; a clock CLK signal is sent to a clock end of a first D trigger through an MIN-OFF timer, a DRV2 signal is sent to a data end of the first D trigger after being negated, and an output end of the first D trigger and a BOOSTMB voltage reduction state signal are sent to an S end of a fifth RS trigger after passing through a fifth AND gate; the clock CLK signal is sent to the clock end of the second D trigger through an MIN-ON timer, the DRV4 signal is sent to the data end of the second D trigger after being negated, the output end of the second D trigger and the BOOSTM voltage boosting state signal are sent to the R end of the fifth RS trigger through the sixth AND gate, the Q output of the fifth RS trigger is the BOOSTM voltage boosting state signal, and the Q negated is the BOOSTMB voltage reducing state signal.
FIG. 5 shows a waveform diagram of VIN input voltage greater than or equal to VOUT output voltage, the system enters a buck-boost critical state, assuming that the first period is a buck mode, since VIN and VOUT voltages are relatively close at this time, PWMBCK is turned over for less than MIN-OFF set time, the state determination circuit will trigger the boost mode, after clock synchronization, the next clock cycle will enter the boost mode, after entering the boost mode, PWMBST is turned over for less than MIN-ON time, the state determination circuit will trigger the buck mode, after clock synchronization, the next clock cycle will enter the buck mode, and a large period is ended.
When the VOUT output voltage slowly approaches to VIN input voltage again, the boost state inserted in the large period is larger than 1, along with the increase of the VOUT approaching to VIN degree, the clock number of the large period is changed into 2, 3, 4 and the like until the system completely enters the boost mode after being separated from the buck-boost mode, the input and output voltage state is more smooth compared with the traditional voltage detection mode, and the system is approximately seamlessly switched from buck to buck-boost.
FIG. 6 shows a waveform diagram of the VIN input voltage being less than or equal to the VOUT output voltage, the system enters the buck-boost critical state, assuming that the first period is the boost mode, since VOUT and VIN are relatively close at this time, PWMBST is less than MIN-ON set time when turning over, the state judgment circuit will trigger the buck mode, after clock synchronization, the next CLK clock period will enter the buck mode, after entering the buck mode, PWMBCK turning time is less than MIN-OFF set time, the state judgment circuit will trigger the boost mode, after clock synchronization, the next clock period will enter the boost mode, a large period is over, only one pair of switching tubes will be switched in each CLK clock period, and dynamic loss of one pair of switching tubes is saved compared with the conventional buck-boost controller.
When the VIN voltage slowly approaches the VOUT voltage, the number of the inserted BOOSTMB states in the large period is larger than 1, along with the increase of the VIN approaching the VOUT degree, the number of the clocks in the large period is changed into 2, 3, 4 and the like until the system is separated from the voltage increasing and decreasing mode to enter the voltage decreasing mode, the change is smoother than the traditional voltage detection mode, and the system is approximately seamlessly switched from the voltage increasing mode to the voltage increasing-decreasing mode.
Compared with the traditional buck-boost controller, the invention realizes the reduction of dynamic loss, and can adjust the time of MIN-ON and MIN-OFF aiming at different working frequencies, thereby realizing the smooth and seamless switching from boost to buck-boost to boost modes.
Reference throughout this specification to "one embodiment," "another embodiment," "an embodiment," "a preferred embodiment," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment described generally in this application. The appearances of the same phrase in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments. Although the invention has been described herein with reference to a number of illustrative examples thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope and spirit of the principles of this disclosure. More specifically, other uses will be apparent to those skilled in the art in view of variations and modifications in the subject matter incorporating the components and/or arrangement of the arrangement within the scope of the disclosure, drawings and claims hereof.
Claims (6)
1. A buck-boost controller based on current mode, comprising: a controller, a voltage feedback loop and a current sampling circuit;
the controller outputs DRV1 signals, DRV2 signals, DRV3 signals and DRV4 signals, the voltage feedback loop comprises a first switching tube, a second switching tube, a third switching tube and a fourth switching tube, the drain electrode of the first switching tube is connected with VIN input signals, the grid electrode of the first switching tube is connected with the DRV1 signals of the controller, and the source electrode of the first switching tube is connected with the drain electrode of the second switching tube; the drain electrode of the third switching tube is connected with a VOUT output signal, the gate electrode of the third switching tube is connected with a DRV3 signal of the controller, and the source electrode of the third switching tube is connected with the drain electrode of the fourth switching tube; the source electrode of the second switch tube and the source electrode of the fourth switch tube are connected with a current sampling resistor, and the grid electrode of the second switch tube is connected with a DRV2 signal of the controller; the grid electrode of the fourth switching tube is connected with a DRV4 signal of the controller; the drain electrode of the third switching tube is connected in series with a first resistor and a second resistor in parallel and is connected to an output voltage feedback signal VFB, and the voltage feedback signal VFB is output to the controller;
an induction coil is connected between the source of the first switching tube and the source of the third switching tube in series, the source of the first switching tube and the drain of the second switching tube are connected with one end of the induction coil, and the source of the third switching tube and the drain of the fourth switching tube are connected with the other end of the induction coil;
an input capacitor is connected in parallel between the VIN input signal and the drain electrode of the first switch tube, and the other end of the input capacitor is grounded; an output capacitor is connected in parallel between the VOUT output signal and the drain of the third switch tube, and the other end of the output capacitor is grounded.
2. The current mode based buck-boost controller of claim 1, wherein the controller comprises:
EA operational amplifier circuit, is used for outputting PWMBCK signal and PWMBST signal;
a BUCK BUCK logic circuit for outputting a DRV1 signal and a DRV2 signal;
a BOOST logic circuit for outputting a DRV3 signal and a DRV4 signal;
and the STATE STATE detection circuit is used for outputting the BOOSTM signal.
3. The current mode based BUCK-BOOST controller of claim 2, wherein said BUCK logic, BOOST logic and STATE status detection circuit are all clocked by the CLK signal.
4. The current mode based BUCK-boost controller of claim 3, wherein said BUCK BUCK logic circuit comprises: the first and gate, the second and gate, the first or gate, the second or gate, the third or gate, the first RS trigger, the second RS trigger, the first driver and the second driver;
the PWMBCK signal and the BOOSTMB voltage reduction state signal are jointly accessed into a first AND gate, the PWMBCK signal and the BOOSTMB voltage reduction state signal are accessed into a first OR gate together with a rising edge signal of the BOOSTM voltage increase state signal, and the output of the first OR gate is accessed into the S end of a first RS trigger; the clock CLK signal and the BOOSTMB voltage reduction state signal are accessed into a second AND gate, and are accessed into the R end of the first RS trigger after being output; the Q output end of the first RS trigger and the BOOSTM boosting state signal synchronous with the result clock pass through a second OR gate and then are connected with a first driver to output a DRV1 signal, and a DRV1 signal is connected with the grid electrode of the first switching tube; the DRV1 signal is processed by a falling edge and then is connected with the S end of the second RS trigger; after the DRV1 signal is processed by a rising edge and the BUCKZCD signal passes through a third OR gate, the output of the third OR gate is connected with the R end of a second RS trigger, the output end Q of the second RS trigger is connected with a second driver, the second driver outputs a DRV2 signal, and the DRV2 signal is connected with the grid electrode of a second switch tube Q2.
5. The current mode based buck-BOOST controller of claim 3, wherein said BOOST logic circuit comprises: the first and second and third and fourth and fifth or gates, a first RS trigger, a first driver and a first driver;
the clock CLK signal and the BOOSTM signal are accessed to the S end of the third RS trigger after passing through the third AND gate, and the PWMBST signal and the BOOSTM signal are accessed to the R end of the third RS trigger after passing through the fourth AND gate; the Q output end of the third RS trigger is connected with a fourth driver, the fourth driver outputs a DRV4 signal, and a DRV4 signal is connected with the grid electrode of a fourth switching tube Q4; the Q non-output end of the third trigger is connected to the S end of a fourth RS trigger through rising edge detection, a DRV4 signal and a BOOSTZCD signal are input to the R end of the fourth RS trigger after passing through a fourth OR gate, the Q output end of the fourth RS trigger and a BOOSTMB signal which is subjected to clock synchronization are output to a third driver after passing through a fifth OR gate, the third driver outputs a DRV3 signal, and the DRV3 signal is connected with the grid electrode of a third switching tube Q3.
6. The current-mode based buck-boost controller of claim 3, wherein the STATE detection circuit comprises: the system comprises a MIN-OFF timer, a MIN-ON timer, a first D trigger, a second D trigger, a fifth RS trigger, a fifth AND gate and a sixth AND gate;
a clock CLK signal is sent to a clock end of a first D trigger through an MIN-OFF timer, a DRV2 signal is sent to a data end of the first D trigger after being negated, and an output end of the first D trigger and a BOOSTMB voltage reduction state signal are sent to an S end of a fifth RS trigger after passing through a fifth AND gate; the clock CLK signal is sent to the clock end of the second D trigger through an MIN-ON timer, the DRV4 signal is sent to the data end of the second D trigger after being negated, the output end of the second D trigger and the BOOSTM voltage boosting state signal are sent to the R end of the fifth RS trigger through the sixth AND gate, the Q output of the fifth RS trigger is the BOOSTM voltage boosting state signal, and the Q negated is the BOOSTMB voltage reducing state signal.
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