CN112071357B - SRAM memory charge-discharge effect test system and method based on FPGA - Google Patents
SRAM memory charge-discharge effect test system and method based on FPGA Download PDFInfo
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Abstract
The invention provides a system and a method for testing charge-discharge effect of an SRAM (static random Access memory) based on an FPGA (field programmable Gate array), comprising the following steps of: a test unit; the test unit includes: the device comprises a PC (personal computer), an upper computer, a lower computer, a charge-discharge effect simulation source and an electromagnetic shielding unit; the electromagnetic shielding unit includes: metal plates, faraday cages; the PC is connected with the upper computer through a serial port; the upper computer is connected with the lower computer through a shielding wire; the lower computer is arranged in a simulation source environment; the PC, the upper computer and the power supply system are arranged in the electromagnetic shielding unit. The invention provides a method for testing the charge and discharge effects of the SRAM for the first time, and the faults of the SRAM caused by the charge and discharge effects can be tested by using the method.
Description
Technical Field
The invention relates to the technical field of memory charging and discharging, in particular to a system and a method for testing charging and discharging effects of an SRAM (static random access memory) based on an FPGA (field programmable gate array).
Background
The SRAM device refers to a Static Random-Access Memory (SRAM), and the structure is characterized in that data stored inside can be maintained as long as power is maintained, and the stored data disappears when power is lost. The SRAM memory has been widely used in satellite electronic systems, such as memories of satellite computers and payload systems, because of its advantages of fast read/write, large storage capacity, low power consumption, etc. However, the surface charge and discharge of a spacecraft and the deep charge and discharge of a medium caused by space radiation can cause the restarting, latching, overturning and other faults of the satellite-borne SRAM, and the ground simulation test verification of the charge and discharge effect of the SRAM becomes very important along with the gradual improvement of the requirements on the long service life and high reliability of the satellite.
The existing SRAM memory space radiation effect test methods only aim at the single event effect and cannot evaluate faults induced by charge and discharge effects.
Patent document CN108133731A discloses an atmospheric neutron-induced SRAM device failure rate detection method and system, which performs atmospheric neutron single event effect detection on an SRAM array to obtain measurement data of the atmospheric neutron single event effect detection of the SRAM array; acquiring the total capacity of the SRAM array; and acquiring the failure rate of the SRAM device according to the measurement data and the total capacity of the SRAM array. The patent leaves room for improvement in both structure and performance.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a system and a method for testing the charge-discharge effect of an SRAM (static random access memory) based on an FPGA (field programmable gate array).
The SRAM memory charging and discharging effect test system based on the FPGA provided by the invention comprises: a test unit; the test unit includes: the device comprises a PC (personal computer), an upper computer, a lower computer, a charge-discharge effect simulation source and an electromagnetic shielding unit; the electromagnetic shielding unit includes: metal plates, faraday cages; the device is used for testing the charging and discharging effect of the chip, the lower computer, the upper computer, the PC and the testing equipment are isolated, when the analog source generates a discharging pulse at one end of the lower computer, the reflection is realized through the metal plate, and the interference of the discharging pulse on the upper computer, the PC and the testing equipment is relieved; the PC is connected with the upper computer through a serial port; the upper computer is connected with the lower computer through a shielding wire; the lower computer is placed in a simulation source environment; the PC, the upper computer and the power supply system are arranged in the electromagnetic shielding unit.
Preferably, the PC includes: PC hardware devices and control software; the host computer includes: FPGA control chip (Xilinx corporation chip). The PC is connected with an upper computer containing an FPGA control chip through a serial port and is used for sending a control instruction to the upper computer, controlling the upper computer, receiving data from the upper computer, realizing functions of data analysis and the like;
preferably, the host computer further includes: the device comprises a power supply part, an OSC module, an RS422 interface, a lower computer communication interface part, a Flash chip and a JTAG interface. The Flash chip is used for storing an FPGA configuration file of the upper computer; the JTAG interface is used for testing and directly configuring an upper computer FPGA.
Preferably, the lower computer comprises: an SRAM circuit board to be tested; the SRAM circuit board to be tested comprises: SRAM chip, power supply part and IO mouth to be measured.
Preferably, the charge-discharge effect simulation source includes: an electrostatic discharge generator, an electron gun, and a radioactive source. And selecting a proper simulation source according to experimental needs.
Preferably, the test unit further comprises: a power supply unit; and the power supply unit is connected with the PC, the upper computer and the lower computer. The power supply unit provides constant power supplies for the PC, the upper computer and the lower computer, and has a large current limiting protection function;
according to the SRAM memory charging and discharging effect test method based on the FPGA, the SRAM memory charging and discharging effect test system based on the FPGA is adopted, and the SRAM memory charging and discharging effect test method based on the FPGA comprises the following steps:
step S1: building a test unit before an irradiation test according to the control information built by the test unit; step S2: powering on the test unit according to the power-on control information of the test unit; step S3: configuring an FPGA control chip of an upper computer; step S4: transmitting a write command, a write address and data (such as 55H) to be written into an SRAM memory to an upper computer FPGA control chip through a communication interface by adopting a PC; the written data in the step S4 should be different from the level of the default pin of the SRAM chip as much as possible; step S5: after receiving the write command, the write address and the data to be written into the SRAM in the step S4, the FPGA control chip of the upper computer decodes and executes a write time sequence, and transmits the data to the SRAM device to be tested; step S6: the SRAM device to be tested receives the test data output in the step S5; step S7: the PC is adopted to transmit the reading instruction and the reading address to an upper computer FPGA control chip through a communication interface; step S8: the FPGA control chip of the upper computer receives the read instruction and the read address in the step S7, decodes and executes a read time sequence, reads the data of the SRAM device to be tested, and transmits the data to the PC in real time to acquire first return result information; step S9: judging whether the first return result information is the same as the first written data information or not; if yes, obtaining the information that the SRAM successfully writes data; if not, obtaining SRAM write data failure information, checking each component of the PC, the upper computer and the lower computer, and executing step S2; the PC receives the result returned in the step S8, compares the result with the written data, if the result is the same as the written data, the SRAM written data is successful, and the next step can be carried out; if the difference indicates that the SRAM fails to write data, checking each part of the PC, the upper computer and the lower computer and executing the step S2.
Preferably, the method further comprises the following steps:
step S10: starting a charge-discharge effect simulation source for irradiation; when the charge-discharge effect simulation source is an electrostatic discharge generator, the discharge voltage of the electrostatic discharge generator is adjusted, the gun head can be used for discharging a coupling metal plate to generate electromagnetic pulses which are coupled to the SRAM device to be tested through radiation conduction, and the gun head can also be used for directly injecting, discharging and coupling pins of the SRAM device to be tested into the device; in step S10, parameters such as discharge voltage and discharge frequency should be counted by using peripheral test equipment;
when the charge-discharge effect simulation source is an electron gun or a radioactive source, a dielectric material for the satellite is selected as an irradiated object, and discharge pulse radiation is generated through electron irradiation or injected into an SRAM device;
step S11: the PC is adopted to transmit the reading instruction and the reading address to an upper computer FPGA control chip through a communication interface;
step S12: receiving the reading instruction and the reading address in the step S11 by using an FPGA control chip of the upper computer, decoding, executing a reading time sequence, reading data of the SRAM device to be tested, transmitting the data to the PC in real time, and acquiring second returned result information;
step S13: recording the number of stored data overturns caused by charging and discharging according to the second returned result information;
judging whether the second returned result information is consistent with the second written data; in particular, whether the data received by the PC machine is consistent with the written data is judged,
if not, acquiring data overturning information and recording the number of overturning data.
Acquiring whether data is in a turning state or not;
step S14: according to the information of whether the data is in the overturn state result, if the data in the SRAM memory is not overturned, repeating the step S10 to the step S13;
repeating the steps S4 to S13 according to the data demand information in the SRAM memory;
step S15: stopping testing when the discharge times or the data turnover number in the SRAM reaches a set value;
when the PC and the upper computer cannot perform reading and writing operations, namely the PC and the upper computer are considered to be interrupted due to the influence of the charging and discharging effects, at the moment, the phenomenon data is recorded, the unit power supply is disconnected, the power supply is powered on again, the step S2 is executed, and the restarting detection process is started;
when the operation of resetting the data of the SRAM device to be tested is needed, the PC transmits a write instruction, a write address and the data which needs to be rewritten into the SRAM memory to be tested to an upper computer FPGA control chip through a communication interface;
and after receiving the write command, the write address and the data to be written into the SRAM memory, the FPGA control chip of the upper computer decodes and executes a write time sequence, transmits the data to the SRAM device to be tested, and receives and stores the test data by the SRAM device to be tested.
Preferably, the step S3 includes: step S3.1: configuring an upper computer FPGA control chip by adopting any one or more methods; -configured with a JTAG interface via a PC; and the FLASH chip is configured in an SPI form through the upper computer.
Preferably, the step S14 includes: step S14.1: if the data is stored to be changed from '1' to '0' or changed from '0' to '1', the data is turned over, and data turning judgment result information is obtained.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention provides a method for testing the charge and discharge effects of the SRAM for the first time, and the faults of the SRAM caused by the charge and discharge effects can be tested by using the testing method;
2. the invention can realize the test of different discharge sources by utilizing different charge-discharge simulation sources, and is suitable for the test under the atmospheric pressure environment and the vacuum environment;
3. the invention is provided with the mode of PC machine + upper computer + lower computer for testing, electromagnetic shielding is carried out on the PC machine and the upper computer, and the influence of a charge-discharge effect simulation source on a testing end is reduced;
4. the invention is suitable for various SRAM devices and can overcome the defects of the prior art.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
fig. 1 is a schematic diagram of a working flow of a method for comprehensively testing charge and discharge effects of an SRAM memory based on an FPGA according to the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
As shown in fig. 1, the SRAM memory charge/discharge effect test system based on FPGA according to the present invention includes: a test unit; the test unit includes: the device comprises a PC (personal computer), an upper computer, a lower computer, a charge-discharge effect simulation source and an electromagnetic shielding unit; the electromagnetic shielding unit includes: metal plates, faraday cages; the device is used for testing the charging and discharging effect of a chip, the lower computer, the upper computer, the PC and the testing equipment are isolated, and when a simulation source generates a discharging pulse at one end of the lower computer, the reflection is realized through a metal plate, so that the interference of the discharging pulse on the upper computer, the PC and the testing equipment is relieved; the PC is connected with the upper computer through a serial port; the upper computer is connected with the lower computer through a shielding wire; the lower computer is arranged in a simulation source environment; the PC, the upper computer and the power supply system are arranged in the electromagnetic shielding unit.
Preferably, the PC includes: PC hardware devices and control software; the host computer includes: FPGA control chip (Xilinx corporation chip). The PC is connected with an upper computer containing an FPGA control chip through a serial port and is used for sending a control instruction to the upper computer, controlling the upper computer, receiving data from the upper computer, realizing functions of data analysis and the like;
preferably, the host computer further includes: the device comprises a power supply part, an OSC module, an RS422 interface, a lower computer communication interface part, a Flash chip and a JTAG interface. The Flash chip is used for storing an FPGA configuration file of the upper computer; the JTAG interface is used for testing and directly configuring an upper computer FPGA.
Preferably, the lower computer comprises: an SRAM circuit board to be tested; the SRAM circuit board to be tested comprises: SRAM chip, power supply unit and IO mouth await measuring.
Preferably, the charge-discharge effect simulation source includes: an electrostatic discharge generator, an electron gun, and a radioactive source. And selecting a proper simulation source according to experimental needs.
Preferably, the test unit further comprises: a power supply unit; and the power supply unit is connected with the PC, the upper computer and the lower computer. The power supply unit provides constant power supplies for the PC, the upper computer and the lower computer, and has a large current limiting protection function;
according to the SRAM memory charging and discharging effect test method based on the FPGA, the SRAM memory charging and discharging effect test system based on the FPGA is adopted, and the SRAM memory charging and discharging effect test method based on the FPGA comprises the following steps:
step S1: building a test unit before an irradiation test according to the control information built by the test unit; step S2: powering on the test unit according to the power-on control information of the test unit; step S3: configuring an FPGA control chip of an upper computer; step S4: transmitting a write command, a write address and data (such as 55H) to be written into an SRAM memory to an upper computer FPGA control chip through a communication interface by adopting a PC; the written data in the step S4 should be different from the level of the default pin of the SRAM chip as much as possible; step S5: after receiving the write command, the write address and the data to be written into the SRAM in the step S4, the FPGA control chip of the upper computer decodes and executes a write time sequence, and transmits the data to the SRAM device to be tested; step S6: the SRAM device to be tested receives the test data output in the step S5; step S7: the PC is adopted to transmit the reading instruction and the reading address to an upper computer FPGA control chip through a communication interface; step S8: the FPGA control chip of the upper computer receives the read instruction and the read address in the step S7, decodes and executes a read time sequence, reads the data of the SRAM device to be tested, and transmits the data to the PC in real time to acquire first return result information; step S9: judging whether the first return result information is the same as the first written data information or not; if yes, obtaining the information that the SRAM successfully writes data; if not, obtaining SRAM write data failure information, checking each component of the PC, the upper computer and the lower computer, and executing step S2; the PC receives the result returned in the step S8, compares the result with the written data, if the result is the same as the written data, the SRAM written data is successful, and the next step can be carried out; if the difference indicates that the SRAM fails to write data, checking each part of the PC, the upper computer and the lower computer and executing the step S2.
Preferably, the method further comprises the following steps:
step S10: starting a charge-discharge effect simulation source for irradiation; when the charge-discharge effect simulation source is an electrostatic discharge generator, the discharge voltage of the electrostatic discharge generator is adjusted, the gun head can be used for discharging a coupling metal plate to generate electromagnetic pulses which are coupled to the SRAM device to be tested through radiation conduction, and the gun head can also be used for directly injecting, discharging and coupling pins of the SRAM device to be tested into the device; in step S10, parameters such as discharge voltage and discharge frequency should be counted by using peripheral test equipment;
when the charge-discharge effect simulation source is an electron gun or a radioactive source, a dielectric material for the satellite is selected as an irradiated object, and discharge pulse radiation is generated through electron irradiation or injected into an SRAM device;
step S11: the PC is adopted to transmit the reading instruction and the reading address to an upper computer FPGA control chip through a communication interface;
step S12: receiving the reading instruction and the reading address in the step S11 by using an FPGA control chip of the upper computer, decoding, executing a reading time sequence, reading data of the SRAM device to be tested, transmitting the data to the PC in real time, and acquiring second returned result information;
step S13: recording the number of stored data overturns caused by charging and discharging according to the second returned result information;
judging whether the second returned result information is consistent with the second written data; in particular, whether the data received by the PC machine is consistent with the written data is judged,
if not, acquiring data overturning information and recording the number of overturning data.
Acquiring whether data is in a turning state or not;
step S14: according to the information of whether the data is in the overturn state result, if the data in the SRAM memory is not overturned, repeating the step S10 to the step S13;
repeating the steps S4 to S13 according to the data demand information in the SRAM memory;
step S15: stopping testing when the discharge times or the data turnover number in the SRAM reaches a set value;
when the PC and the upper computer cannot perform reading and writing operations, namely the PC and the upper computer are considered to be interrupted due to the influence of the charging and discharging effects, at the moment, the phenomenon data is recorded, the unit power supply is disconnected, the power supply is powered on again, the step S2 is executed, and the restarting detection process is started;
when the operation of resetting the data of the SRAM device to be tested is needed, the PC transmits a write instruction, a write address and the data which needs to be rewritten into the SRAM memory to be tested to an upper computer FPGA control chip through a communication interface;
and after receiving the write command, the write address and the data to be written into the SRAM memory, the FPGA control chip of the upper computer decodes and executes a write time sequence, transmits the data to the SRAM device to be tested, and receives and stores the test data by the SRAM device to be tested.
Preferably, the step S3 includes: step S3.1: configuring an upper computer FPGA control chip by adopting any one or more methods; -configured with a JTAG interface via a PC; and the FLASH chip is configured in an SPI form through the upper computer.
Preferably, the step S14 includes: step S14.1: if the data is stored to be changed from '1' to '0' or changed from '0' to '1', the data is turned over, and data turning judgment result information is obtained.
The invention provides a method for testing the charge and discharge effects of the SRAM for the first time, and the faults of the SRAM caused by the charge and discharge effects can be tested by using the testing method; the invention can realize the test of different discharge sources by utilizing different charge-discharge simulation sources, and is suitable for the test under the atmospheric pressure environment and the vacuum environment; the invention is provided with the mode of PC machine + upper computer + lower computer for testing, electromagnetic shielding is carried out on the PC machine and the upper computer, and the influence of a charge-discharge effect simulation source on a testing end is reduced; the invention is suitable for various SRAM devices and can overcome the defects of the prior art.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (3)
1. A SRAM memory charge-discharge effect test method based on FPGA is characterized in that an SRAM memory charge-discharge effect test system based on FPGA is adopted,
the test system comprises:
a test unit;
the test unit includes: the device comprises a PC (personal computer), an upper computer, a lower computer, a charge-discharge effect simulation source and an electromagnetic shielding unit;
the electromagnetic shielding unit includes: metal plates, faraday cages;
the PC is connected with the upper computer through a serial port;
the upper computer is connected with the lower computer through a shielding wire;
the lower computer is arranged in a simulation source environment;
the PC, the upper computer and the power supply system are arranged in the electromagnetic shielding unit;
the PC machine includes: PC hardware devices and control software;
the host computer includes: an FPGA control chip;
the host computer still includes: the device comprises a power supply part, an OSC module, an RS422 interface, a lower computer communication interface part, a Flash chip and a JTAG interface;
the lower computer comprises: an SRAM circuit board to be tested;
the SRAM circuit board to be tested comprises: the SRAM chip to be tested, the power supply part and the IO port;
the charge-discharge effect simulation source comprises any one of the following:
-an electrostatic discharge generator;
-an electron gun;
-a radioactive source;
the test unit further includes: a power supply unit;
and the power supply unit is connected with the PC, the upper computer and the lower computer.
The test method comprises the following steps:
step S1: building a test unit before an irradiation test according to the control information built by the test unit;
step S2: powering on the test unit according to the power-on control information of the test unit;
step S3: configuring an FPGA control chip of an upper computer;
step S4: transmitting the write command, the write address and data to be written into the SRAM memory to an upper computer FPGA control chip through a communication interface by adopting a PC;
step S5: after receiving the write command, the write address and the data to be written into the SRAM in the step S4, the FPGA control chip of the upper computer decodes and executes a write time sequence, and transmits the data to the SRAM device to be tested;
step S6: the SRAM device to be tested receives the test data output in the step S5;
step S7: the PC is adopted to transmit the reading instruction and the reading address to an upper computer FPGA control chip through a communication interface;
step S8: the FPGA control chip of the upper computer receives the read instruction and the read address in the step S7, decodes and executes a read time sequence, reads the data of the SRAM device to be tested, and transmits the data to the PC in real time to acquire first return result information;
step S9: judging whether the first return result information is the same as the first written data information or not;
if yes, obtaining the information that the SRAM successfully writes data;
if not, obtaining SRAM write data failure information, checking the PC, the upper computer and the lower computer and executing the step S2;
further comprising:
step S10: starting a charge-discharge effect simulation source for irradiation; when the analog source of the charge-discharge effect is an electrostatic discharge generator, the discharge voltage of the electrostatic discharge generator is adjusted; the gun head can be used for discharging the coupling metal plate to generate electromagnetic pulses which are coupled to the SRAM device to be tested through radiation conduction, or the gun head can be used for directly injecting, discharging and coupling pins of the SRAM device to be tested into the device;
when the charge-discharge effect simulation source is an electron gun or a radioactive source, selecting a medium material for the satellite as an irradiated object, and generating discharge pulse radiation through electron irradiation or injecting the discharge pulse radiation into an SRAM device; when the analog source is adopted, the discharge voltage threshold can be changed by adjusting the parameters of the dielectric material;
step S11: the PC is adopted to transmit the reading instruction and the reading address to an upper computer FPGA control chip through a communication interface;
step S12: receiving the reading instruction and the reading address in the step S11 by using an FPGA control chip of the upper computer, decoding, executing a reading time sequence, reading data of the SRAM device to be tested, transmitting the data to the PC in real time, and acquiring second returned result information;
step S13: recording the number of stored data overturns caused by charging and discharging according to the second returned result information;
judging whether the second returned result information is consistent with the second written data;
if not, acquiring data overturning information and recording the number of overturning data;
acquiring whether data is in a turning state or not;
step S14: according to the information of whether the data is in the overturn state result, if the data in the SRAM memory is not overturned, repeating the step S10 to the step S13;
repeating the steps S4 to S13 according to the data demand information in the SRAM memory;
step S15: stopping testing when the discharge times or the data turnover number in the SRAM reaches a set value;
when the PC and the upper computer cannot perform reading and writing operations, namely the PC and the upper computer are considered to be interrupted due to the influence of the charging and discharging effects, at the moment, the phenomenon data is recorded, the unit power supply is disconnected, the power supply is powered on again, the step S2 is executed, and the restarting detection process is started;
when the operation of resetting the data of the SRAM device to be tested is needed, the PC transmits a write instruction, a write address and the data which needs to be rewritten into the SRAM memory to be tested to an upper computer FPGA control chip through a communication interface;
and after receiving the write command, the write address and the data to be written into the SRAM memory, the FPGA control chip of the upper computer decodes and executes a write time sequence, transmits the data to the SRAM device to be tested, and receives and stores the test data by the SRAM device to be tested.
2. The method for testing charge and discharge effects of the SRAM memory based on the FPGA of claim 1, wherein the step S3 comprises:
step S3.1: configuring an upper computer FPGA control chip by adopting any one or more methods;
-configured with a JTAG interface via a PC;
and the FLASH chip is configured in an SPI form through the upper computer.
3. The method for testing charge and discharge effects of the SRAM memory based on the FPGA of claim 1, wherein the step S14 comprises:
step S14.1: and if the data is stored to be changed from 1 to 0 or changed from 0 to 1, acquiring data turnover judgment result information.
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| CN102332310A (en) * | 2011-10-18 | 2012-01-25 | 中国航天科技集团公司第五研究院第五一〇研究所 | FPGA (Field Programmable Gate Array)-based single event effect test system for NAND FLASH device |
| CN105448350A (en) * | 2014-08-29 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | SRAM test key, and test apparatus and SRAM test method thereof |
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