CN112053968B - Method and device for reducing high-temperature off-state leakage of semiconductor device - Google Patents

Method and device for reducing high-temperature off-state leakage of semiconductor device Download PDF

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CN112053968B
CN112053968B CN202010876479.0A CN202010876479A CN112053968B CN 112053968 B CN112053968 B CN 112053968B CN 202010876479 A CN202010876479 A CN 202010876479A CN 112053968 B CN112053968 B CN 112053968B
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高林春
曾传滨
李晓静
闫薇薇
倪涛
李多力
卜建辉
张颢译
王可
刘海南
罗家俊
韩郑生
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Abstract

The invention provides a method and a device for reducing high-temperature off-state leakage of a semiconductor device, wherein the method comprises the following steps: aiming at a target device, acquiring a first temperature transfer characteristic curve of the target device at normal temperature and a second temperature transfer characteristic curve of the target device at a target temperature; acquiring a first gate voltage corresponding to a sub-threshold leakage cut-off current of a target device, a first threshold voltage and a second gate voltage corresponding to the sub-threshold leakage cut-off current; determining a target threshold voltage of a target device at a target temperature; adjusting the trap ion implantation concentration of the target device based on the target threshold voltage; thus, the target threshold voltage can be reached only by implanting ions based on the adjusted ion implantation concentration; on a temperature transfer characteristic curve, the cut-off point of the sub-threshold leakage cut-off current is ensured to be at the position of zero grid voltage, so that the off-state leakage of the device at high temperature can be ensured to be the lowest without greatly changing the structure and the process flow of the device, and the cost is ensured.

Description

Method and device for reducing high-temperature off-state leakage of semiconductor device
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a method and a device for reducing high-temperature off-state electric leakage of a semiconductor device.
Background
Silicon-based CMOS technology is currently the dominant technology for high temperature integrated circuit design. However, as the threshold voltage, channel length, and gate oxide thickness decrease, high leakage current is becoming a major factor affecting high temperature CMOS circuits, resulting in increased static power consumption of high temperature integrated circuits.
The main features of MOS devices under high temperature conditions are an increase in leakage current and a shift in threshold voltage. Although static power consumption of high temperature integrated circuits can now be reduced by reducing the leakage of PN junctions within the devices and improving isolation between devices; however, as process dimensions shrink to deep submicron and even nanometer dimensions, sub-threshold leakage of low voltage MOS devices can render the devices unusable in extremely high temperature environments.
The common method for reducing junction leakage in the prior art is to reduce the area of an internal device or a PN junction between devices, but the method needs to make great changes to the structure and the process flow of the device, and the process flow is complex and expensive.
Disclosure of Invention
Aiming at the problems in the prior art, the embodiment of the invention provides a method and a device for reducing high-temperature off-state leakage of a semiconductor device, which are used for solving the technical problems that the process flow is complex and the cost is high because the structure and the process flow of the device need to be greatly changed when the high-temperature off-state leakage of the device is reduced in the prior art.
The invention provides a method for reducing high-temperature off-state leakage of a semiconductor device, which comprises the following steps:
aiming at a target device, acquiring a first temperature transfer characteristic curve of the target device at normal temperature and a second temperature transfer characteristic curve of the target device at a target temperature;
acquiring a first gate voltage and a first threshold voltage corresponding to the sub-threshold leakage off-current of the target device based on the first temperature transfer characteristic curve; acquiring a second gate voltage corresponding to the sub-threshold leakage off-current of the target device based on the second temperature transfer characteristic curve;
determining a target threshold voltage of the target device at the target temperature from the first gate voltage, the first threshold voltage and the second gate voltage;
adjusting a trap ion implantation concentration of the target device based on the target threshold voltage.
Optionally, the obtaining a first gate voltage corresponding to a sub-threshold leakage off-current of the target device based on the first temperature transfer characteristic curve includes:
determining a first boundary point of a junction leakage area and a sub-threshold leakage area in the first temperature transfer characteristic curve, wherein the ordinate of the first boundary point corresponds to the sub-threshold leakage cutoff current;
acquiring a voltage corresponding to the abscissa of the first junction point; and the voltage corresponding to the abscissa of the first intersection point is the first gate voltage.
Optionally, the obtaining a second gate voltage corresponding to the sub-threshold leakage off-current of the target device based on the second temperature transfer characteristic curve includes:
determining a second junction point of the junction leakage area and the sub-threshold leakage area in the second temperature transfer characteristic curve, wherein the ordinate of the second junction point corresponds to the sub-threshold leakage cutoff current;
acquiring voltage corresponding to the abscissa of the second junction point; and the voltage corresponding to the abscissa of the second intersection point is the second gate voltage.
Optionally, the determining a target threshold voltage of the target device at the target temperature according to the first gate voltage, the first threshold voltage and the second gate voltage includes:
obtaining a difference voltage between the first gate voltage and the second gate voltage;
determining the sum of the difference voltage and the first threshold voltage, wherein the sum of the difference voltage and the first threshold voltage is the target threshold voltage.
Optionally, the adjusting the trap ion implantation concentration of the target device based on the target threshold voltage includes:
acquiring a corresponding relation table of threshold voltage and trap ion implantation concentration;
searching the corresponding relation table for the ion implantation concentration of the target trap corresponding to the target threshold voltage;
and adjusting the trap ion implantation concentration of the target device based on the searched target trap ion implantation concentration.
The invention provides a device for reducing high-temperature off-state electric leakage of a semiconductor device, which comprises:
the device comprises an acquisition unit, a comparison unit and a control unit, wherein the acquisition unit is used for acquiring a first temperature transfer characteristic curve of a target device at normal temperature and a second temperature transfer characteristic curve of the target device at a target temperature aiming at the target device; acquiring a first gate voltage and a first threshold voltage corresponding to the sub-threshold leakage off-current of the target device based on the first temperature transfer characteristic curve; acquiring a second gate voltage corresponding to the sub-threshold leakage cutoff current of the target device based on the second temperature transfer characteristic curve;
a determining unit, configured to determine a target threshold voltage of the target device at the target temperature according to the first gate voltage, the first threshold voltage and the second gate voltage;
and the adjusting unit is used for adjusting the trap ion implantation concentration of the target device based on the target threshold voltage.
Optionally, the obtaining unit is specifically configured to:
determining a first boundary point of a junction leakage area and a sub-threshold leakage area in the first temperature transfer characteristic curve, wherein the ordinate of the first boundary point corresponds to the sub-threshold leakage cutoff current;
acquiring a voltage corresponding to the abscissa of the first junction point; and the voltage corresponding to the abscissa of the first intersection point is the first gate voltage.
Optionally, the obtaining unit is specifically configured to:
determining a second junction point of the junction leakage area and the sub-threshold leakage area in the second temperature transfer characteristic curve, wherein the ordinate of the second junction point corresponds to the sub-threshold leakage cutoff current;
acquiring voltage corresponding to the abscissa of the second junction point; and the voltage corresponding to the abscissa of the second intersection point is the second gate voltage.
Optionally, the determining unit is specifically configured to:
acquiring a difference voltage between the first gate voltage and the second gate voltage;
determining the sum of the difference voltage and the first threshold voltage, wherein the sum of the difference voltage and the first threshold voltage is the target threshold voltage.
Optionally, the adjusting unit is specifically configured to:
acquiring a corresponding relation table of threshold voltage and trap ion implantation concentration;
searching the corresponding relation table for the target trap ion implantation concentration corresponding to the target threshold voltage;
and adjusting the trap ion implantation concentration of the target device based on the searched target trap ion implantation concentration.
The invention provides a method and a device for reducing high-temperature off-state leakage of a semiconductor device, wherein the method comprises the following steps: aiming at a target device, acquiring a first temperature transfer characteristic curve of the target device at normal temperature and a second temperature transfer characteristic curve of the target device at a target temperature; acquiring a first gate voltage and a first threshold voltage corresponding to the sub-threshold leakage off-current of the target device based on the first temperature transfer characteristic curve; acquiring a second gate voltage corresponding to the sub-threshold leakage cutoff current of the target device based on the second temperature transfer characteristic curve; determining a target threshold voltage of the target device at the target temperature from the first gate voltage, the first threshold voltage and the second gate voltage; adjusting a trap ion implantation concentration of the target device based on the target threshold voltage; thus, when ions are implanted into the trap of the target device, the target threshold voltage can be reached only by implanting the ions based on the adjusted ion implantation concentration; therefore, on the temperature transfer characteristic curve, the cut-off point of the sub-threshold leakage cut-off current can fall at the position of zero grid voltage, and the minimum off-state leakage of the device at high temperature is ensured.
Drawings
FIG. 1 is a schematic flow chart of a method for reducing high-temperature off-state leakage of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of temperature transfer characteristics of devices at different temperatures according to an embodiment of the present invention;
fig. 3 is a first temperature transfer characteristic curve corresponding to a target device at a standard temperature and a second temperature transfer characteristic curve corresponding to the target device at a target temperature according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the mechanism of the leakage current of the MOSFET according to the embodiment of the present invention;
fig. 5 is a schematic structural diagram of an apparatus for reducing high-temperature off-state leakage of a semiconductor device according to an embodiment of the present invention.
Detailed Description
The method aims to solve the technical problems that in the prior art, when the high-temperature off-state leakage of a device is reduced, the structure and the process flow of the device need to be greatly changed, so that the process flow is complex and the cost is high. The invention provides a method and a device for reducing high-temperature off-state electric leakage of a semiconductor device.
The technical solution of the present invention is further described in detail by the accompanying drawings and the specific embodiments.
Example one
The embodiment provides a method for reducing high-temperature off-state leakage of a semiconductor device, which is called high temperature when the temperature is higher than 125 ℃, as shown in fig. 1, the method comprises the following steps:
s110, aiming at a target device, acquiring a first temperature transfer characteristic curve of the target device at normal temperature and a second temperature transfer characteristic curve of the target device at a target temperature;
for any device, referring to fig. 2, the temperature transfer characteristic curves of the device at different temperatures (25 ℃, 100 ℃, 200 ℃ and 300 ℃ respectively) can be tested, and the electrical parameters of the target device, such as the threshold voltage (Vth), off-state leakage, driving current, and sub-threshold leakage off-current Idb, can be determined from the temperature transfer characteristic curves. Here, fig. 2 is a temperature transition characteristic curve of the NMOS device at different temperatures when Vds is 0.05V.
Therefore, for the target device, a first temperature transfer characteristic curve of the target device at normal temperature and a second temperature transfer characteristic curve of the target device at the target temperature can be obtained. Referring to fig. 3, fig. 3 is a temperature transfer characteristic curve corresponding to the NMOS device when Vds is 0.05V. When the standard temperature is 25 degrees, the corresponding first temperature transfer characteristic curve is as the line in fig. 3
Figure BDA0002652697100000051
Shown; when the high temperature is 300 ℃, the corresponding second temperature transfer characteristic curve is as the line in fig. 3
Figure BDA0002652697100000052
As shown. Wherein the target device may include: a semiconductor device of an SOI substrate or a semiconductor device of a silicon substrate; the target device may be an NMOS device or a PMOS device.
The off-state leakage influences the static power consumption in the circuit and is an electrical parameter which is mainly concerned by the high-temperature circuit; the driving current represents the driving capability of the circuit, and the driving current varies with the variation of the threshold voltage.
Here, the device leakage scheme includes many, referring to FIG. 4, I1Is reverse biased pn junction leakage; i is2Is a sub-threshold leak; I.C. A3Is the oxide tunneling current; i is4Is the gate current due to hot carrier injection; i is5Gate-induced drain leakage current (GIDL); i is6Is the channel punch-through current. Wherein, the current I2，I5And I6Is leakage in the off state, and1and I3Are all in on and IOFFAnd occurs in a state. I is4Can occur in the off state, but more commonly occurs in the transistor bias state during the transition.
The sub-threshold leakage refers to that when the gate voltage is smaller than the threshold voltage, the device is not in a complete cut-off state, but a tiny current flows, and the magnitude of the current and the gate voltage are in an exponential relationship. For a short channel device, when the Drain voltage increases, the sub-threshold leakage of the device increases sharply due to the effect of the Barrier Lowering effect (DIBL) introduced by the Drain terminal, and a very large leakage current exists even under the off-state condition.
Then the sub-threshold leakage cutoff current is the current corresponding to the intersection of the sub-threshold leakage and the junction leakage point. Referring to fig. 2, the region with a relatively flat temperature transfer characteristic curve (left region) is the junction leakage, the region with a suddenly increased slope (right region) is the sub-threshold leakage region, and the ordinate of the boundary between the two regions is the sub-threshold leakage cutoff current.
S111, acquiring a first gate voltage and a first threshold voltage corresponding to the sub-threshold leakage off-current of the target device based on the first temperature transfer characteristic curve; acquiring a second gate voltage corresponding to the sub-threshold leakage cutoff current of the target device based on the second temperature transfer characteristic curve;
after the first temperature transfer characteristic curve and the second temperature transfer characteristic curve are obtained, a first gate voltage and a first threshold voltage corresponding to the sub-threshold leakage cut-off current of the target device are obtained based on the first temperature transfer characteristic curve; and acquiring a second gate voltage corresponding to the sub-threshold leakage off-current of the target device based on the second temperature transfer characteristic curve.
As an alternative embodiment, obtaining a first gate voltage corresponding to a sub-threshold leakage off-current of a target device based on a first temperature transfer characteristic curve includes:
determining a first junction point of the junction leakage area and the sub-threshold leakage area in the first temperature transfer characteristic curve, wherein the ordinate of the first junction point corresponds to the sub-threshold leakage cut-off current;
acquiring voltage corresponding to the abscissa of the first junction point; and the voltage corresponding to the abscissa of the first intersection point is a first gate voltage.
With continued reference to fig. 3, the first boundary point may be indicated by a mark a. And the threshold voltage is the voltage corresponding to ordinate 1.0E-07.
As an alternative embodiment, obtaining the second gate voltage corresponding to the sub-threshold leakage off-current of the target device based on the second temperature transfer characteristic curve includes:
determining a second junction point of the junction leakage area and the sub-threshold leakage area in a second temperature transfer characteristic curve, wherein the ordinate of the second junction point corresponds to the sub-threshold leakage cut-off current;
acquiring voltage corresponding to the abscissa of the second junction point; the voltage corresponding to the abscissa of the second intersection point is the second gate voltage. With continued reference to fig. 3, the second boundary point can be identified as mark B.
S112, determining a target threshold voltage of the target device at the target temperature according to the first gate voltage, the first threshold voltage and the second gate voltage;
and after the first gate voltage, the first threshold voltage and the second gate voltage are determined, determining a target threshold voltage of the target device at a target temperature according to the first gate voltage, the first threshold voltage and the second gate voltage.
As an alternative embodiment, determining the target threshold voltage of the target device at the target temperature according to the first gate voltage, the first threshold voltage and the second gate voltage includes:
acquiring a difference voltage between the first gate voltage and the second gate voltage;
and determining the sum of the difference voltage and the first threshold voltage, wherein the sum of the difference voltage and the first threshold voltage is the target threshold voltage.
And S113, adjusting the trap ion implantation concentration of the target device based on the target threshold voltage.
After the target threshold voltage is determined, the trap ion implantation concentration of the target device is adjusted based on the target threshold voltage.
Here, for a gate dielectric layer with a fixed thickness, the threshold voltage has a certain corresponding relationship with the ion implantation concentration in the trap, so that when the ion implantation concentration of the trap is adjusted, the threshold voltage can be adjusted.
As an alternative embodiment, adjusting the trap ion implantation concentration of the target device based on the target threshold voltage includes:
acquiring a corresponding relation table of threshold voltage and trap ion implantation concentration;
searching the corresponding relation table for the ion implantation concentration of the target trap corresponding to the target threshold voltage;
and adjusting the trap ion implantation concentration of the target device based on the searched target trap ion implantation concentration.
In this embodiment, the dose of the implanted ions on the surface of the channel of the target device is 1014cm-2The particle implantation concentration is 1018cm-3The target threshold voltage is about 0.6-0.7V.
Thus, the target threshold voltage is adjusted by adjusting the ion implantation concentration in the trap, and when the target threshold voltage is increased, the corresponding temperature transfer characteristic curve is shifted to the right along the X axis; thus, when Vg is 0, the target device is not in the sub-on state, and the leakage mainly includes junction leakage, and at this time, sub-threshold leakage is not caused. And the junction leakage is far smaller than the sub-threshold leakage, so the off-state leakage of the device can be reduced, and the high-temperature power consumption of the device is further reduced.
Based on the same inventive concept, the invention also provides a device for reducing the high-temperature off-state leakage of the semiconductor device, which is described in the second embodiment.
Example two
The present embodiment provides an apparatus for reducing high-temperature off-state leakage of a semiconductor device, as shown in fig. 5, the apparatus includes: an acquisition unit 51, a determination unit 52, and an adjustment unit 53; wherein the content of the first and second substances,
an obtaining unit 51, configured to obtain, for a target device, a first temperature transfer characteristic curve of the target device at normal temperature and a second temperature transfer characteristic curve of the target device at a target temperature; acquiring a first gate voltage and a first threshold voltage corresponding to the sub-threshold leakage off-current of the target device based on the first temperature transfer characteristic curve; acquiring a second gate voltage corresponding to the sub-threshold leakage off-current of the target device based on the second temperature transfer characteristic curve;
a determining unit 52, configured to determine a target threshold voltage of the target device at the target temperature according to the first gate voltage, the first threshold voltage and the second gate voltage;
and an adjusting unit 53, configured to adjust the trap ion implantation concentration of the target device based on the target threshold voltage.
For any device, referring to fig. 2, the temperature transfer characteristic curves of the device at different temperatures (25 ℃, 100 ℃, 200 ℃ and 300 ℃ respectively) can be tested, and the electrical parameters of the target device, such as the threshold voltage (Vth), off-state leakage, driving current, and sub-threshold leakage off-current Idb, can be determined from the temperature transfer characteristic curves. Here, fig. 2 is a temperature transition characteristic curve of the NMOS device at different temperatures when Vds is 0.05V.
Therefore, for the target device, a first temperature transfer characteristic curve of the target device at normal temperature and a second temperature transfer characteristic curve of the target device at the target temperature can be obtained. Referring to fig. 3, fig. 3 is a temperature transfer characteristic curve corresponding to the NMOS device when Vds is 0.05V. When the standard temperature is 25 degrees, the corresponding first temperature transfer characteristic curve is as the line in FIG. 3 "
Figure BDA0002652697100000091
Shown; when the high temperature is 300 ℃, the corresponding second temperature transfer characteristic curve is as the line in fig. 3
Figure BDA0002652697100000092
As shown. It is composed ofThe target device may include: a semiconductor device of an SOI substrate or a semiconductor device of a silicon substrate; the target device may be an NMOS device or a PMOS device.
The off-state leakage influences the static power consumption in the circuit and is an electrical parameter which is mainly concerned by the high-temperature circuit; the driving current represents the driving capability of the circuit, and the driving current varies with the variation of the threshold voltage.
Here, the device leakage scheme includes many, referring to FIG. 4, I1Is reverse biased pn junction leakage; I.C. A2Is a sub-threshold leak; i is3Is the oxide tunneling current; I.C. A4Is the gate current due to hot carrier injection; i is5Gate-induced drain leakage current (GIDL); i is6Is the channel punch-through current. Wherein, the current I2，I5And I6Is leakage in the off state, and1and I3Are all in on and IOFFAnd occurs in a state. I is4Can occur in the off state, but more commonly occurs in the transistor bias state during the transition.
The sub-threshold leakage is that when the gate voltage is less than the threshold voltage, the device is not in a complete cut-off state, but a small current flows, and the magnitude of the current is in an exponential relation with the gate voltage. For a short channel device, when the Drain voltage increases, the sub-threshold leakage of the device increases sharply due to the effect of the Barrier Lowering effect (DIBL) introduced by the Drain terminal, and a very large leakage current exists even under the off-state condition.
The sub-threshold leakage cutoff current is the current corresponding to the intersection of the sub-threshold leakage and the junction leakage point. Referring to fig. 2, a region with a relatively flat temperature transfer characteristic curve (left-side region) is junction leakage, a region with a suddenly increased slope (right-side region) is a sub-threshold leakage region, and a vertical coordinate of a junction between the two regions is a sub-threshold leakage cutoff current.
After the first temperature transfer characteristic curve and the second temperature transfer characteristic curve are acquired, the acquiring unit 51 acquires a first gate voltage and a first threshold voltage corresponding to the sub-threshold leakage off-current of the target device based on the first temperature transfer characteristic curve; and acquiring a second gate voltage corresponding to the sub-threshold leakage off-current of the target device based on the second temperature transfer characteristic curve.
As an alternative embodiment, the obtaining unit 51 obtains the first gate voltage corresponding to the sub-threshold leakage off-current of the target device based on the first temperature transfer characteristic curve, and includes:
determining a first junction point of the junction leakage area and the sub-threshold leakage area in the first temperature transfer characteristic curve, wherein the ordinate of the first junction point corresponds to the sub-threshold leakage cut-off current;
acquiring voltage corresponding to the abscissa of the first junction point; and the voltage corresponding to the abscissa of the first intersection point is a first gate voltage.
With continued reference to fig. 3, the first boundary point may be indicated by a mark a. And the threshold voltage is the voltage corresponding to ordinate 1.0E-07.
As an alternative embodiment, the obtaining unit 51 obtains the second gate voltage corresponding to the sub-threshold leakage off-current of the target device based on the second temperature transfer characteristic curve, and includes:
determining a second junction point of the junction leakage area and the sub-threshold leakage area in a second temperature transfer characteristic curve, wherein the ordinate of the second junction point corresponds to the sub-threshold leakage cut-off current;
acquiring voltage corresponding to the abscissa of the second junction point; the voltage corresponding to the abscissa of the second intersection point is the second gate voltage. With continued reference to fig. 3, the second boundary point may be indicated by the mark B.
After the first gate voltage, the first threshold voltage and the second gate voltage are determined, the determining unit 52 determines a target threshold voltage of the target device at a target temperature according to the first gate voltage, the first threshold voltage and the second gate voltage.
As an alternative embodiment, the determining unit 52 determines the target threshold voltage of the target device at the target temperature according to the first gate voltage, the first threshold voltage and the second gate voltage, and includes:
acquiring a difference voltage between the first gate voltage and the second gate voltage;
and determining the sum of the difference voltage and the first threshold voltage, wherein the sum of the difference voltage and the first threshold voltage is the target threshold voltage.
After the target threshold voltage is determined, the trap ion implantation concentration of the target device is adjusted based on the target threshold voltage.
Here, for a gate dielectric layer with a fixed thickness, the threshold voltage has a certain corresponding relationship with the ion implantation concentration in the trap, so that when the ion implantation concentration of the trap is adjusted, the threshold voltage can be adjusted.
As an alternative embodiment, the adjusting unit 53 adjusts the trap ion implantation concentration of the target device based on the target threshold voltage, and includes:
acquiring a corresponding relation table of threshold voltage and trap ion implantation concentration;
searching the corresponding relation table for the ion implantation concentration of the target trap corresponding to the target threshold voltage;
and adjusting the trap ion implantation concentration of the target device based on the searched target trap ion implantation concentration.
In this embodiment, the dose of the implanted ions on the surface of the channel of the target device is 1014cm-2The particle implantation concentration is 1018cm-3The target threshold voltage is about 0.6-0.7V.
Thus, the target threshold voltage is adjusted by adjusting the ion implantation concentration in the trap, and when the target threshold voltage is increased, the corresponding temperature transfer characteristic curve is shifted to the right along the X axis; thus, when Vg is 0, the target device is not in the sub-on state, and the leakage mainly includes junction leakage, and at this time, sub-threshold leakage is not caused. And the junction leakage is far smaller than the sub-threshold leakage, so that the off-state leakage of the device can be reduced, and the high-temperature power consumption of the device is further reduced.
The method and the device for reducing the high-temperature off-state leakage of the semiconductor device provided by the embodiment of the invention have the following beneficial effects that:
the invention provides a method and a device for reducing high-temperature off-state leakage of a semiconductor device, wherein the method comprises the following steps: aiming at a target device, acquiring a first temperature transfer characteristic curve of the target device at normal temperature and a second temperature transfer characteristic curve of the target device at a target temperature; acquiring a first gate voltage and a first threshold voltage corresponding to the sub-threshold leakage cutoff current of the target device based on the first temperature transfer characteristic curve; acquiring a second gate voltage corresponding to the sub-threshold leakage cutoff current of the target device based on the second temperature transfer characteristic curve; determining a target threshold voltage of the target device at the target temperature according to the first gate voltage, the first threshold voltage and the second gate voltage; adjusting a trap ion implantation concentration of the target device based on the target threshold voltage; thus, when ions are implanted into the trap of the target device, the target threshold voltage can be reached only by implanting the ions based on the adjusted ion implantation concentration; therefore, on the temperature transfer characteristic curve, the cut-off point of the sub-threshold leakage cut-off current can fall at the position of zero grid voltage, and the minimum off-state leakage of the device at high temperature is ensured.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.

Claims (8)

1. A method for reducing high temperature off-state leakage in a semiconductor device, the method comprising:
aiming at a target device, acquiring a first temperature transfer characteristic curve of the target device at normal temperature and a second temperature transfer characteristic curve of the target device at a target temperature;
acquiring a first gate voltage and a first threshold voltage corresponding to the sub-threshold leakage off-current of the target device based on the first temperature transfer characteristic curve; acquiring a second gate voltage corresponding to the sub-threshold leakage off-current of the target device based on the second temperature transfer characteristic curve;
determining a target threshold voltage of the target device at the target temperature according to the first gate voltage, the first threshold voltage and the second gate voltage;
adjusting a trap ion implantation concentration of the target device based on the target threshold voltage; wherein the content of the first and second substances,
the determining a target threshold voltage of the target device at the target temperature from the first gate voltage, the first threshold voltage, and the second gate voltage includes:
obtaining a difference voltage between the first gate voltage and the second gate voltage;
determining the sum of the difference voltage and the first threshold voltage, wherein the sum of the difference voltage and the first threshold voltage is the target threshold voltage.
2. The method of claim 1, wherein the obtaining a first gate voltage corresponding to a sub-threshold leakage off-current of the target device based on the first temperature transfer characteristic curve comprises:
determining a first boundary point of a junction leakage area and a sub-threshold leakage area in the first temperature transfer characteristic curve, wherein the ordinate of the first boundary point corresponds to the sub-threshold leakage cutoff current in the first temperature transfer characteristic curve;
acquiring a voltage corresponding to the abscissa of the first junction point; and the voltage corresponding to the abscissa of the first intersection point is the first gate voltage.
3. The method of claim 1, wherein the obtaining a second gate voltage corresponding to a sub-threshold leakage off-current of the target device based on the second temperature transfer characteristic curve comprises:
determining a second boundary point of the junction leakage area and the sub-threshold leakage area in the second temperature transfer characteristic curve, wherein the ordinate of the second boundary point corresponds to the sub-threshold leakage cutoff current in the second temperature transfer characteristic curve;
acquiring voltage corresponding to the abscissa of the second junction point; and the voltage corresponding to the abscissa of the second intersection point is the second gate voltage.
4. The method of claim 1, wherein the adjusting the trap ion implantation concentration of the target device based on the target threshold voltage comprises:
acquiring a corresponding relation table of threshold voltage and trap ion implantation concentration;
searching the corresponding relation table for the target trap ion implantation concentration corresponding to the target threshold voltage;
and adjusting the trap ion implantation concentration of the target device based on the searched target trap ion implantation concentration.
5. An apparatus for reducing high temperature off-state leakage in a semiconductor device, the apparatus comprising:
the device comprises an acquisition unit, a comparison unit and a control unit, wherein the acquisition unit is used for acquiring a first temperature transfer characteristic curve of a target device at normal temperature and a second temperature transfer characteristic curve of the target device at a target temperature aiming at the target device; acquiring a first gate voltage and a first threshold voltage corresponding to the sub-threshold leakage off-current of the target device based on the first temperature transfer characteristic curve; acquiring a second gate voltage corresponding to the sub-threshold leakage off-current of the target device based on the second temperature transfer characteristic curve;
a determining unit, configured to determine a target threshold voltage of the target device at the target temperature according to the first gate voltage, the first threshold voltage and the second gate voltage;
an adjusting unit for adjusting the trap ion implantation concentration of the target device based on the target threshold voltage; wherein the content of the first and second substances,
the determining unit is specifically configured to:
obtaining a difference voltage between the first gate voltage and the second gate voltage;
determining the sum of the difference voltage and the first threshold voltage, wherein the sum of the difference voltage and the first threshold voltage is the target threshold voltage.
6. The apparatus of claim 5, wherein the obtaining unit is specifically configured to:
determining a first boundary point of a junction leakage area and a sub-threshold leakage area in the first temperature transfer characteristic curve, wherein the ordinate of the first boundary point corresponds to the sub-threshold leakage cutoff current in the first temperature transfer characteristic curve;
acquiring voltage corresponding to the abscissa of the first intersection point; and the voltage corresponding to the abscissa of the first intersection point is the first gate voltage.
7. The apparatus of claim 5, wherein the obtaining unit is specifically configured to:
determining a second boundary point of the junction leakage area and the sub-threshold leakage area in the second temperature transfer characteristic curve, wherein the ordinate of the second boundary point corresponds to the sub-threshold leakage cutoff current in the second temperature transfer characteristic curve;
acquiring voltage corresponding to the abscissa of the second junction point; and the voltage corresponding to the abscissa of the second intersection point is the second gate voltage.
8. The apparatus of claim 5, wherein the adjustment unit is specifically configured to:
acquiring a corresponding relation table of threshold voltage and trap ion implantation concentration;
searching the corresponding relation table for the ion implantation concentration of the target trap corresponding to the target threshold voltage;
and adjusting the trap ion implantation concentration of the target device based on the searched target trap ion implantation concentration.
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