CN112039805B

CN112039805B - Low-delay jitter high-speed signal switching system

Info

Publication number: CN112039805B
Application number: CN202010880369.1A
Authority: CN
Inventors: 张吉林; 杨聃; 陈开国; 王敏; 叶云涛; 陈世朴
Original assignee: Ksw Technologies Co ltd
Current assignee: Ksw Technologies Co ltd
Priority date: 2020-08-27
Filing date: 2020-08-27
Publication date: 2021-09-03
Anticipated expiration: 2040-08-27
Also published as: CN112039805A

Abstract

The invention discloses a low-delay jitter high-speed signal exchange system which comprises RapidIO, gigabit Ethernet, RS485, GPIO, radio frequency connection and the like, reserves abundant interfaces and supports higher backboard bandwidth. The inter-board exchange provides 8 pairs of transceivers, the line speed can reach 6.25Gbps, and the theoretical highest data exchange capacity of 50Gbps can be provided between any boards. The system architecture adopts a switching structure to replace a main control structure such as PXI-e, CPCIe and the like, so that the overall performance of the system is not limited by a main control board any more, and the overall performance of the system is improved. Meanwhile, under a switching structure, any board card can send data at any time without bus arbitration, thereby reducing the uncertainty time delay increased by bus request and bus arbitration process, and being particularly suitable for the requirements of high-speed and real-time signal transmission.

Description

Low-delay jitter high-speed signal switching system

Technical Field

The invention belongs to the technical field of communication, and particularly relates to a low-delay jitter high-speed signal switching system.

Background

The backplane is a physical channel between the input and output. The traditional back board adopts a structure of a shared back board, a master-slave exchange mode is used, and all the carrier boards are controlled through a master control board. The backplane bandwidth marks the total data exchange capacity of the switch, and is also called as Gbps, and the backplane bandwidth of a general switch varies from several Gbps to hundreds of Gbps. The higher the backplane bandwidth, the more capable of processing data, but at the same time the higher the design cost.

With the increasing communication frequency, the increasing number of ports of the communication equipment and the increasing bandwidth of the communication system bus, when the communication equipment is tested, the corresponding testing technical requirements have the requirements of high bandwidth, rapid data exchange and the like, and the communication testing equipment has the characteristics of more channels, excellent synchronization characteristics and the like.

At present, communication test equipment developed based on bus technologies such as PXI and PCIe is implemented by using a main control board loading board, and all the carriers need to exchange data through the main control board, that is, the above-mentioned type of bus equipment uses the main control board as a core exchange unit, and has the disadvantages that the bus rate is limited by the main control board, the delay is large, and the jitter is large.

Therefore, a low delay jitter high speed handshake system is needed to solve the above problems.

Disclosure of Invention

The present invention is directed to a low delay jitter high speed signal switching system, which is used to solve the technical problems in the prior art.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a low delay jitter high speed signal switching system comprising:

the RAPIDIO switching module is used for carrying out RAPIDIO X8 high-speed data switching among all the board cards;

the Ethernet exchange module is used for carrying out gigabit Ethernet data exchange among the board cards, the front panel and the rear panel;

the 24-path GPIO signal exchange module is used for transmitting 24-path GPIO signals;

the reference signal providing module is used for providing 100MHz reference signals for each board card;

the trigger signal providing module is used for providing trigger signals for the board cards;

the power supply module converts an alternating current power supply into a low-ripple power supply through the AC-DC conversion module and provides a direct current power supply for each board card;

each board card is provided with two radio frequency connectors;

each board card carries out internal low-speed data exchange through an RS485 bus;

the acquisition module is used for completing signal acquisition of the system;

the storage module is used for directly storing the signals acquired by the acquisition module after high-speed exchange;

the playback module is used for directly playing back the signals acquired by the acquisition module after high-speed exchange;

and the structure fixing module is used for fixing the structures of all the modules of the whole system.

Further, the reference signal providing module provides 100MHz reference signals for each carrier, and outputs 100MHz reference signals to the outside at the same time, where the reference signals are from:

the crystal is derived from a system backboard 100MHz crystal, and the frequency of an output signal can be adjusted through a numerical control potentiometer;

the signal is derived from a 10MHz signal provided by a GPS/Beidou receiver; through a frequency divider/frequency multiplier, a phase discriminator and a phase-locked loop, a 100MHz crystal phase of a system backboard is locked in a 10MHz signal provided by a GPS/Beidou receiver;

derived from an externally provided reference signal; through a frequency divider/frequency multiplier, a phase discriminator and a phase-locked loop, the HBI backboard 100MHz crystal phase-locked is in reference signal provided by the outside.

Furthermore, the 24 paths of GPIO signal exchange modules provide a function of switching network of TTL signals among the boards, the board of each slot is provided with 24 paths of TTL signals to be connected to the GPIO signal exchange modules, and the TTL signal exchange control among the boards can be realized through an HBI backboard control tool provided along with the development platform;

the mutual communication of TTL signals between boards can be quickly realized by configuring a source slot position and a source port and a target slot position and a target port of the TTL signals through software; and automatically storing the configuration result of the system backboard control tool into the system, and loading the GPIO configuration table for the last time by default when the system is restarted each time after the configuration is finished.

Further, the trigger signal providing module provides an external trigger signal to a synchronous trigger network among all board cards in the system; the trigger signal network uses a special path in the system, ensures the synchronism of the trigger signal reaching each board card, provides powerful support for the system needing synchronous processing, and simultaneously each board card in the system can also output the synchronous trigger signal to the outside to meet the synchronous trigger requirement among devices; the system back plate control tool provided with the development platform can conveniently realize the routing control of the trigger signal;

the configuration of the trigger signal internet can be quickly realized by configuring the trigger node, the output enable, the output signal type and the trigger signal source through software; and automatically storing the configuration result of the system backboard control tool into the system, and loading the configuration table of the trigger node for the last time by default when the system is restarted each time after the configuration is finished.

Furthermore, the RAPIDIO switching module realizes high-speed data switching of 14 slots through three SRIO switching chips, each slot in the system comprises two SRIO interfaces which are configured to be in an X4 mode by default, and the line rate of the backplane switching chip and the SRIO interface of each slot can be configured to be 2.5Gbps, 3.125Gbps, 5Gbps and 6.25 Gbps; the address ID of the SRIO port of each slot position is a fixed value, and the configuration of the SRIO port speed mode of each slot position and the routing table configuration of HBI can be realized through a back plate control tool provided with the system;

the rate mode of each port of each slot position can be configured independently, and the SRIO rate modes between two intercommunicated board cards need to be configured to be consistent;

selecting the path type as unidirectional connection or bidirectional connection, and connecting at the slot SRIO port needing high-speed data interaction;

the port rate mode configuration and the port routing configuration issue the configuration table to the back panel through an RS485 bus, and after the back panel driver receives the configuration table, the back panel driver writes the configuration table into an EPROM and configures the parameters of the configuration table to an SRIO switching chip;

every time power is on, the back board driver firstly checks whether an SRIO port mode configuration table and a port routing table exist in the EPROM, if user configuration exists, the configuration table is read, the parameters of the configuration table are configured to the SRIO switching chip, and if the user configuration does not exist, default configuration is loaded.

Furthermore, the Ethernet exchange module can exchange 10M/100M/1000M Ethernet data between any carrier boards with 14 slots, and simultaneously provides 1 external 10M/100M/1000M Ethernet interface.

Further, the bus exchange module is: an RS485 bus shared by the back plate EP3C120 and the 14 slot positions, and RS232 and RS485 serial data interfaces, wherein the first slot position is independently connected with the back plate EP3C120 chip.

Furthermore, each time the EPROM is powered on, whether an SRIO port mode configuration table and a port routing table exist or not is checked; the method comprises the following specific steps:

if the port mode configuration table and the port routing table are checked at the same time; the system directly executes the read port mode configuration table;

if only checking the port mode configuration table, not checking the port routing table; the system temporarily stores the port mode configuration table, performs secondary check on the port routing table, if the port routing table is checked during the secondary check, the system reads the port mode configuration table, and if the port routing table is not checked yet during the secondary check, the system suspends operation and sends out a port routing table check exception prompt;

if only the port routing table is checked, the port mode configuration table is not checked; the system temporarily stores the port routing table, performs secondary check on the port mode configuration table, if the port mode configuration table is checked during the secondary check, the system reads the port mode configuration table, and if the port mode configuration table is not checked yet during the secondary check, the system suspends operation and sends out a port mode configuration table check exception prompt;

if the port mode configuration table and the port routing table are not checked; the system directly suspends the operation and sends out a port mode configuration table and a port routing table check exception prompt.

Compared with the prior art, the invention has the beneficial effects that:

one innovation point of the scheme is that the data exchange channel of the system comprises: RapidIO, gigabit Ethernet, RS485, GPIO, radio frequency connection and the like, reserve rich interfaces and simultaneously support higher backplane bandwidth. The inter-board exchange provides 8 pairs of transceivers, the line speed can reach 6.25Gbps, and the theoretical highest data exchange capacity of 50Gbps can be provided between any boards. The system architecture adopts a switching structure to replace a main control structure such as PXI-e, CPCIe and the like, so that the overall performance of the system is not limited by a main control board any more, and the overall performance of the system is improved. Meanwhile, under a switching structure, any board card can send data at any time without bus arbitration, thereby reducing the uncertainty time delay increased by bus request and bus arbitration process, and being particularly suitable for the requirements of high-speed and real-time signal transmission.

Drawings

Fig. 1 is a schematic diagram of an HBI clock interconnect network in accordance with an embodiment of the present invention.

Fig. 2 is a schematic diagram of an HBI low-speed IO interconnect network according to an embodiment of the present invention.

Fig. 3 is a functional diagram illustrating a configuration function of a GPIO routing table of an HBI backplane control tool according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of an HBI trigger signal interconnect network according to an embodiment of the present invention.

Fig. 5 is a functional diagram of setting a trigger node parameter by the HBI backplane control tool according to the embodiment of the present invention.

Fig. 6 is a schematic diagram of an HBI high-speed data switching network according to an embodiment of the present invention.

Fig. 7 is a functional diagram of a RAPIDIO port rate mode configuration according to an embodiment of the present invention.

Fig. 8 is a functional diagram of a RAPIDIO port routing configuration according to an embodiment of the present invention.

Fig. 9 is a RAPIDIO port routing representation of an embodiment of the present invention.

Fig. 10 is a schematic diagram of an HBI low speed data switching network in accordance with an embodiment of the present invention.

Fig. 11 is a schematic view of a Z7100 carrier according to an embodiment of the present invention.

Fig. 12 is a schematic view of a Z7035 carrier according to an embodiment of the present invention.

Fig. 13 is a schematic view of a Z7020 carrier according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to fig. 1 to 13 of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example (b):

At present, communication test equipment developed based on bus technologies such as PXI and PCIe is implemented by using a main control board loading board, and all the carriers need to exchange data through the main control board, that is, the above-mentioned type of bus equipment uses the main control board as a core exchange unit, and has the disadvantages that the bus rate is limited by the main control board, the delay is large, and the jitter is large. Therefore, a low-delay-jitter high-speed signal switching system, also called an HBI hardware development platform, is developed.

First, summarize HBI hardware development platform:

the HBI hardware development platform introduces the latest high-speed serial transmission technology at present and is widely applied to 4U standard rack structure equipment.

The data exchange channel comprises: RapidIO, gigabit Ethernet, RS485, GPIO, radio frequency connection and the like, reserve rich interfaces and simultaneously support higher backplane bandwidth. The inter-board exchange provides 8 pairs of transceivers, the line speed can reach 6.25Gbps, and the theoretical highest data exchange capacity of 50Gbps can be provided between any boards.

The HBI framework adopts a switching structure to replace a main control structure such as PXI-e, CPCIe and the like, so that the overall performance of the system is not limited by a main control board any more, and the overall performance of the system is improved. Meanwhile, under a switching structure, any board card can send data at any time without bus arbitration, thereby reducing the uncertainty time delay increased by bus request and bus arbitration process, and being particularly suitable for the requirements of high-speed and real-time signal transmission.

Introduction of HBI basic framework:

the HBI core data exchange system has the following functions:

RAPIDIO exchange function: each board card has a RAPIDIO X8 high-speed data exchange function.

Ethernet switching function: the function of gigabit Ethernet data exchange is provided between each board card and the front and the rear panels.

24-way GPIO signal exchange function: has 24-path GPIO signal transmission function.

Providing a reference signal: a 100MHz reference signal is provided for each board.

Providing a trigger signal: and providing trigger signals for each board card.

Power supply: and an AC-DC conversion module converts an AC power supply into a power supply with low ripple waves to provide a DC power supply for each board card.

Providing structural fixation.

Each card provides 2 rf connectors.

Internal bus: and each board card performs internal low-speed data exchange through an RS485 bus.

Third, HBI clock interconnection network introduction:

as shown in fig. 1, the HBI clock interconnect network provides 100MHz reference signals for each carrier, and outputs 100MHz reference signals to the outside at the same time, where the reference signals are from:

the frequency of an output signal of the crystal is adjusted by a numerical control potentiometer from an HBI backboard 100MHz crystal.

Derived from the 10MHz signal provided by the GPS/beidou receiver. Through a frequency divider/frequency multiplier, a phase discriminator and a phase-locked loop, the HBI backboard 100MHz crystal phase-locked is in a 10MHz signal provided by a GPS/Beidou receiver.

Derived from an externally supplied reference signal. Through a frequency divider/frequency multiplier, a phase discriminator and a phase-locked loop, the HBI backboard 100MHz crystal phase-locked is in reference signal provided by the outside.

Fourthly, HBI low-speed IO interconnection network:

as shown in fig. 2, the HBI low-speed IO internet provides a switching network function of TTL signals between boards, each board in each slot has 24 TTL signals connected to a GPIO switching module (backplane EP3C120), and TTL signal switching control between boards can be conveniently implemented by an HBI backplane control tool provided along with the development platform.

As shown in fig. 3, the source slot, the source port, the destination slot, and the destination port of the TTL signal are configured by software, so that the TTL signals between boards can be interconnected and intercommunicated quickly. The configuration result of the HBI backboard control tool is automatically stored in the HBI hardware development platform, and the last GPIO configuration table is loaded by default when the hardware platform is restarted each time after the configuration is completed.

Fifth, HBI trigger signal interconnection network:

as shown in fig. 4, the HBI trigger interconnect network provides an external trigger signal to the synchronous trigger network between the boards in the HBI hardware platform. The trigger signal network uses a special path in the HBI platform, so that the synchronism of the trigger signals reaching each board card is ensured, a powerful support is provided for a system needing synchronous processing, and meanwhile, each board card in the HBI hardware platform can also output synchronous trigger signals to the outside to meet the synchronous trigger requirement among equipment. The trigger signal routing control can be conveniently realized through an HBI back panel control tool provided with the development platform.

As shown in fig. 5, the configuration of the trigger signal interconnection network can be quickly realized by configuring the trigger node, the output enable, the output signal type, and the trigger signal source through software. The configuration result of the HBI back panel control tool is automatically stored in the HBI hardware development platform, and the last trigger node configuration table is loaded by default when the hardware platform is restarted each time after the configuration is completed.

Sixthly, the HBI high-speed data switching network:

as shown in fig. 6, the HBI high-speed data switching network implements high-speed data switching of 14 slots by three SRIO switching chips, and the topology structure of the switching network is shown in detail in the HBI high-speed data switching network. Each slot in the HBI comprises two SRIO interfaces which are configured to be in an X4 mode by default, and the line rate of the SRIO interfaces of the backplane switching chip and each slot can be configured to be 2.5Gbps, 3.125Gbps, 5Gbps and 6.25 Gbps. The address ID of the SRIO port of each slot is a fixed value, for example, the address ID of SRIO [3:0] of slot 1 is 1, and the address ID of SRIO [7:4] is 2; the SRIO [3:0] address ID for slot 14 is 27 and the SRIO [7:4] address ID is 28. The configuration of the SRIO port rate mode of each slot and the routing table configuration of the HBI can be conveniently realized through an HBI backboard control tool provided with a development platform.

As shown in fig. 7, the rate mode of each port of each slot may be configured separately, and it should be noted that SRIO rate modes between two intercommunicated boards need to be configured to be consistent.

As shown in fig. 8, the selection path type is "unidirectional connection" or "bidirectional connection", and the connection may be performed at the slot SRIO port that needs to perform high-speed data interaction, for example, the SRIO [3:0] and SRIO [3:0], SRIO [3:0] and SRIO [7: and 4, bidirectional connection is respectively carried out, after the ports needing high-speed data interaction are connected, the 'generating routing table' is clicked to generate routing configuration, and then the 'setting' is clicked to complete the routing configuration of the high-speed interaction ports.

As shown in fig. 9, the port rate mode configuration and the port routing configuration issue the configuration table to the backplane through the RS485 bus, and after receiving the configuration table, the backplane driver writes the configuration table into the EPROM, and configures the configuration table parameters to the SRIO switch chip.

Because the system may encounter program bugs when checking data, that is, accidental errors are generated, when checking the port mode configuration table and the port routing table, if only one condition is checked, the probability of the accidental errors is high, so that secondary checking is needed to overcome the defects; if the secondary check is not checked, the abnormity caused by accidental errors can be basically determined; this situation only prompts the operator for the relevant debugging.

When the EPROM is powered on every time, whether an SRIO port mode configuration table and a port routing table exist or not is checked; the method comprises the following specific steps:

Seventhly, HBI intermediate speed data exchange network:

10M/100M/1000M Ethernet data exchange between any carrier boards with 14 slots, and 1 external 10M/100M/1000M Ethernet interface is provided.

Ethernet UDP instruction sending format

Ethernet receiving UDP instruction format

Eight, HBI low speed data switching network:

as shown in fig. 10, the HBI low-speed data switching network is mainly embodied as an RS485 bus shared by the backplane EP3C120 and the 14 slots, an RS232 and RS485 serial data interface in which the slot 1 is independently connected to the backplane EP3C120 chip (generally, the slot 1 is a main control board, and the main control board implements configuration of a backplane clock interconnection network, a low-speed IO interconnection network, a trigger signal interconnection network, and a high-speed data switching network through the RS485 interface independent from the slot 1), and an RS232 interface of the backplane EP3C120 and the power board.

HBI board RS485 bus Master sending instruction format

HBI board RS485 bus Slave sending instruction format

Nine, an example of an HBI application development environment:

embedded development environment

Xilinx series chips: SDK

Altera series chip: NIOS

The upper computer development environment: VS2010 and above (c # language development)

Ten, example of HBI platform application development:

the application development of the HBI platform is mainly based on various existing carrier boards and functional daughter cards meeting the HBI interface specification and matched driving programs to accelerate the development of the application.

(1) HBI carrier plate description:

as shown in fig. 11, Z7100 carrier plate;

main resources of the FPGA:

LC：444K

LUTs：277,400

Block RAM：26.5Mb

DSP Slices：2,020

Processor Core：Dual-core ARM Cortex-A9。

as shown in fig. 12, a Z7035 carrier;

main resources of the FPGA:

LC：275K

LUTs：173900

Block RAM：17.6Mb

DSP Slices：900

Processor Core：Dual-core ARM Cortex-A9。

as shown in fig. 13, a Z7020 carrier plate;

main resources of the FPGA:

LC：85K

LUTs：53200

Block RAM：4.9Mb

DSP Slices：220

Processor Core：Dual-core ARM Cortex-A9。

(2) description of HBI function board:

(3) and (3) acquisition board card application development:

the acquisition board card of the high-end FPGA + C5 series carrier board uses C5 to run an embedded operating system to manage system application, and the high-end FPGA is mounted on the embedded operating system in a bus peripheral mode. And receiving and preprocessing high-speed ADC data are completed in a high-end FPGA, and the data are sent to a special signal processing module or a storage board card by an application with high real-time requirement and high data bandwidth through an HBI high-speed data switching network. The application with low real-time requirement and low data bandwidth is processed by the C5 embedded operating system and the processing result is reported by the Ethernet interface.

The acquisition board card of the middle-end FPGA + Z7020 series carrier board adopts a similar mode, the Z7020 runs an embedded operating system, and the middle-end FPGA is mounted on the embedded operating system in a bus peripheral mode. And receiving and preprocessing high-speed ADC data in the middle-end FPGA, and transmitting the data through an HBI high-speed switching network or an Ethernet.

The Z7100 series carrier plate is suitable for development of medium-low speed or software radio related acquisition applications, an ARM part of the Z7100 runs an embedded operating system, and a PL part completes receiving and preprocessing of ADC data.

In application development, related driving codes such as ADC chip control and data interface, clock chip, inter-chip bus interface, SRIO high-speed data interface, Ethernet and the like are provided along with the board card, normal transmission of data flow and control flow is guaranteed, and a user only needs to concentrate on data processing and related application program development.

(4) And (3) launching board card application development:

the transmitting board card of the high-end FPGA + C5 series carrier board uses C5 to run an embedded operating system to manage system application, and the high-end FPGA is mounted on the embedded operating system in a bus peripheral mode. The preprocessing and the sending of high-speed DAC data are completed in a high-end FPGA, and the application with high real-time requirement and high data bandwidth is directly sent down to a preset waveform file of a main control board or a high-speed storage board through an HBI high-speed data switching network. The application with low real-time requirement and low data bandwidth issues waveforms to the high-end FPGA signal processing module through the Ethernet interface of the C5 embedded operating system.

A similar mode is adopted for the transmitting board card of the middle-end FPGA + Z7020 series carrier board, the Z7020 runs an embedded operating system, and the middle-end FPGA is mounted on the embedded operating system in a bus peripheral mode. And preprocessing and sending high-speed DAC data in the middle-end FPGA, wherein the data are transmitted through an HBI high-speed switching network or an Ethernet.

The Z7100 series carrier board is suitable for development of medium-low speed or software radio related transmitting application, an ARM part of the Z7100 runs an embedded operating system, and a PL part completes preprocessing and sending of DAC data.

In application development, a DAC chip control and data interface, a clock chip, an inter-chip bus interface, an SRIO high-speed data interface, an Ethernet and other related driving codes are provided along with a board card, normal transmission of data flow and control flow is guaranteed, and a user only needs to concentrate on data processing and related application program development.

(5) And (3) storage board application development:

the storage board card adopts a middle-end FPGA + Z7020 series carrier board, the Z7020 runs an embedded operating system to manage and transfer the storage files at a low speed, and the Z7020 external interface is an Ethernet. And the middle-end FPGA receives the high-speed data stream through the HBI high-speed switching network and stores the high-speed data stream or sends storage file information to nodes in the high-speed switching network.

And providing a control protocol of a storage type board card and an SRIO high-speed interface protocol in application development.

(6) And (3) application development of radio frequency channels and local oscillator sources:

the RF channel and local oscillator are applied to develop an open control protocol, and a general control interface is an Ethernet interface or an RS485 interface. And when the application is developed, a user selects the radio frequency channel type board card or the local oscillator type board card with matched performance according to the requirement, and the upper-layer application development is carried out through the provided control protocol.

(7) Bus board card application development:

the bus board card application development flexibility is strong, the standard bus protocol provides an application layer driving program, and the bus protocol with customization requirements can open all driving part programs so as to be convenient for transplantation and secondary development.

(8) And (3) development of extension application:

the development of new HBI function daughter cards, HBI carrier boards and other types of HBI function board cards can be carried out according to specific applications without meeting the application development requirements in the existing framework.

The above are preferred embodiments of the present invention, and all changes made according to the technical scheme of the present invention that produce functional effects do not exceed the scope of the technical scheme of the present invention belong to the protection scope of the present invention.

Claims

1. A low delay jitter high speed signal switching system, comprising:

each board card is provided with two radio frequency connectors;

the acquisition module is used for completing signal acquisition of the system;

the structure fixing module is used for fixing the structure of each module of the whole system;

the RAPIDIO switching module realizes high-speed data switching of 14 slots through three SRIO switching chips, each slot in the system comprises two SRIO interfaces which are configured into an X4 mode by default, and the line rate of the backplane switching chip and the SRIO interfaces of each slot can be configured into 2.5Gbps, 3.125Gbps, 5Gbps and 6.25 Gbps; the address ID of the SRIO port of each slot position is a fixed value, and the configuration of the SRIO port speed mode of each slot position and the routing table configuration of HBI can be realized through a back plate control tool provided with the system;

every time power is on, the back board driver firstly checks whether an SRIO port mode configuration table and a port routing table exist in the EPROM, if so, the configuration table is read, and the parameters of the configuration table are configured to the SRIO switching chip;

2. The system according to claim 1, wherein the reference signal providing module provides 100MHz reference signals for each carrier, and outputs 100MHz reference signals to the outside, and the reference signal sources are:

3. The low-delay-jitter high-speed signal switching system according to claim 1, wherein the 24 GPIO signal switching modules provide a switching network function for TTL signals between boards, each slot board has 24 TTL signals connected to the GPIO signal switching modules, and TTL signal switching control between boards can be achieved through an HBI backplane control tool provided along with the development platform;

4. The low-delay-jitter high-speed signal switching system according to claim 1, wherein the trigger signal providing module provides an external trigger signal to a synchronous trigger network among boards in the system; the trigger signal network uses a special path in the system, ensures the synchronism of the trigger signal reaching each board card, provides powerful support for the system needing synchronous processing, and simultaneously each board card in the system can also output the synchronous trigger signal to the outside to meet the synchronous trigger requirement among devices; the trigger signal routing control can be realized through a system backboard control tool provided with the development platform;

5. The system according to claim 1, wherein the ethernet switch module is capable of performing 10M/100M/1000M ethernet data exchange between any 14-slot boards, and providing 1 external 10M/100M/1000M ethernet interface.

6. The low-delay-jitter high-speed signal switching system according to claim 1, wherein said bus switching module is: an RS485 bus shared by the back plate EP3C120 and the 14 slot positions, and RS232 and RS485 serial data interfaces, wherein the first slot position is independently connected with the back plate EP3C120 chip.