CN112015346B - Storage controller, data storage method and device thereof and storage medium - Google Patents
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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Abstract
The invention discloses a data storage method and a data storage device of a storage controller, the storage controller and a computer readable storage medium, wherein the method comprises the following steps: the storage controller acquires a storage event; if the storage event is a fast event, processing the storage event by using a fast path, and storing the data to be stored in the storage event into a corresponding hard disk; the fast path is a path for processing a fast event by a plurality of CPU cores in the storage controller together; if the storage event is a slow event, processing the storage event by using a slow path, and storing the data to be stored in the storage event into a corresponding hard disk; according to the invention, through the arrangement of the fast path and the slow path, the originally disordered storage event is divided into two events, namely the fast event and the slow event which are independent from each other, so that each event can be stably operated and processed according to the respective processing speed, the data storage performance of the storage controller is improved, and the data storage delay of the storage controller is reduced.
Description
Technical Field
The present invention relates to the field of data storage technologies, and in particular, to a data storage method and apparatus for a storage controller, and a computer-readable storage medium.
Background
With the development of modern society science and technology, the application of server is more and more extensive. The function of the storage controller is to receive data from the server and then store the data on a hard disk connected to the storage controller. For an SAN (Storage Area Network) Network, as shown in fig. 1, a Storage controller may be connected to a server through a fiber port (i.e., an FC port) of an FC (fiber Channel) fiber card, and receive and send data of the server; and after receiving the data, the storage controller performs corresponding processing on the data, and finally drops the data onto a hard disk connected with the storage controller.
In the above-described process of data storage, there are great demands on the performance of the storage controller. The performance of the memory controller is largely due to the CPU (central processing unit) usage of the memory controller, and most of the memory controllers are multi-core systems currently, for example, the number of CPU cores of the CPU 2630E5V4 of intel (intel corporation) is 10.
In the prior art, a memory controller usually uses each CPU core to respectively store data (e.g., IO blocks) required to be stored in a corresponding memory event (e.g., IO event) to ensure a stored IPOS (i.e., the number of IO per second); as server performance has increased, client storage requirements have shifted from initial pursuit of maximum IOPS to IOPS and latency and are heavy. Therefore, how to reduce the latency of the storage controller to the data storage, so that the storage controller can meet the increasing capability of the server with faster latency, is a problem that needs to be solved nowadays.
Disclosure of Invention
The invention aims to provide a data storage method and device of a storage controller, the storage controller and a computer readable storage medium, so as to reduce the time delay of the storage controller for data storage, thereby meeting the increasing capability of a server by utilizing faster time delay.
In order to solve the above technical problem, the present invention provides a data storage method of a storage controller, including:
the storage controller acquires a storage event; the storage event is a fast event or a slow event, and the fast event comprises an IO event;
if the storage event is the fast event, processing the storage event by using a fast path, and storing the data to be stored in the storage event into a corresponding hard disk; the fast path is a path for a plurality of CPU cores in the storage controller to jointly process the fast event;
if the storage event is the slow event, processing the storage event by using a slow path, and storing the data to be stored in the storage event into a corresponding hard disk; wherein the slow path is a path for a single CPU core in the memory controller to process the slow event.
Optionally, the method further includes: setting the fast path; the fast path setting process comprises the following steps:
slicing and dividing the processing path of the rapid event to obtain a preset number of uncoupled subpaths; wherein the preset number is greater than or equal to 2;
binding the preset number of the sub-paths to the preset number of CPU cores by utilizing a CPU affinity binding technology; and each sub-path corresponds to one CPU core.
Optionally, the single CPU core corresponding to the slow path is specifically a fixed CPU core in the memory controller.
Optionally, the single CPU core corresponding to the slow path is specifically a target CPU core in the storage controller; wherein the target CPU core is any one of the CPU cores in the storage controller that is not handling the fast event.
Optionally, after the storage controller obtains the storage event, the method further includes:
the storage controller judges whether the storage event is the fast event or not;
if so, executing the step of processing the storage event by using the fast path and storing the data to be stored in the storage event into a corresponding hard disk;
if not, executing the step of processing the storage event by using the slow path and storing the data to be stored in the storage event into a corresponding hard disk.
The present invention also provides a data storage device of a storage controller, comprising:
the acquisition module is used for acquiring the storage event; the storage event is a fast event or a slow event, and the fast event comprises an IO event;
the first storage module is used for processing the storage event by using a fast path and storing data to be stored in the storage event into a corresponding hard disk if the storage event is the fast event; the fast path is a path for a plurality of CPU cores in the storage controller to jointly process the fast event;
the second storage module is used for processing the storage event by using a slow path and storing data to be stored in the storage event into a corresponding hard disk if the storage event is the slow event; wherein the slow path is a path for a single CPU core in the memory controller to process the slow event.
Optionally, the apparatus further comprises: the quick path setting module is used for setting the quick path;
the fast path setting module includes:
the slicing submodule is used for slicing and dividing the processing path of the rapid event to obtain a preset number of uncoupled subpaths; wherein the preset number is greater than or equal to 2;
a binding submodule, configured to bind the preset number of sub paths to the preset number of CPU cores by using a CPU affinity binding technique; and each sub-path corresponds to one CPU core.
Optionally, the apparatus further comprises:
the judging module is used for judging whether the storage event is the quick event or not; if yes, sending a first starting signal to the first storage module; and if not, sending a second starting signal to the second storage module.
The present invention also provides a memory controller comprising:
a memory for storing a computer program;
a processor for implementing the steps of the data storage method of the storage controller as described above when executing the computer program.
Furthermore, the present invention also provides a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the data storage method of the storage controller described above.
The invention provides a data storage method of a storage controller, which comprises the following steps: the storage controller acquires a storage event; the storage event is a fast event or a slow event, and the fast event comprises an IO event; if the storage event is a fast event, processing the storage event by using a fast path, and storing the data to be stored in the storage event into a corresponding hard disk; the fast path is a path for processing a fast event by a plurality of CPU cores in the storage controller together; if the storage event is a slow event, processing the storage event by using a slow path, and storing the data to be stored in the storage event into a corresponding hard disk; the slow path is a path for processing a slow event by a single CPU core in the memory controller;
therefore, through the arrangement of the fast path and the slow path, as the highway is divided into the motorway and the non-motorway, the originally disordered storage events are divided into two events, namely the fast event and the slow event which are independent from each other, so that each event can be stably operated and processed according to the respective processing speed, and the transport capacity of the highway is improved, thereby improving the data storage performance of the storage controller, reducing the data storage delay of the storage controller, and enabling the storage controller to meet the increasingly improved capacity of the server by utilizing faster delay. In addition, the invention also provides a data storage device of the storage controller, the storage controller and a computer readable storage medium, which also have the beneficial effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a data storage system according to the prior art;
FIG. 2 is a flowchart illustrating a data storage method of a storage controller according to an embodiment of the present invention;
fig. 3 is a schematic diagram of IO event processing of a fast path according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating slow event processing of a slow path according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a data storage device of a storage controller according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, fig. 2 is a flowchart illustrating a data storage method of a memory controller according to an embodiment of the present invention. The method can comprise the following steps:
step 101: the storage controller acquires a storage event; the storage event is a fast event or a slow event, and the fast event comprises an IO event.
It should be noted that the storage event obtained by the storage controller in this step may be an event (or referred to as a task or a transaction) that needs to store corresponding data (i.e., data to be stored in the storage event) to the connected hard disk, such as an IO event, a logging event, a command line processing event, an inter-process communication event, and the like. The embodiment is exemplified by storing the acquired data of one storage event by the storage controller, and the storing of the acquired data of a plurality of storage events by the storage controller may be implemented in a manner the same as or similar to the method provided in the embodiment, which is not limited in any way by the embodiment.
Specifically, the specific manner in which the processor (e.g., CPU) of the storage controller acquires the storage event in this step may be set by the designer according to the practical scenario and the user requirement, for example, the storage controller may be implemented in the same or similar manner as the storage event acquisition method in the prior art, for example, the storage controller may receive an IO event (i.e., a storage event) sent by the server through the FC port. The embodiment is not limited as long as the processor of the storage controller can obtain the storage event containing the data to be stored.
It can be understood that the Fast event in this step may be a storage event that needs to be processed by using a Fast Path (Fast Path), that is, an event that needs to be processed quickly and/or with high frequency, such as an IO event corresponding to an IO block that is transmitted by the server to the storage controller through the FC port; the Slow event in this step may be a storage event that needs to be processed by using a Slow Path (Slow Path), that is, an event that can be processed slowly and/or with low frequency, such as a log event, a command line processing event, an inter-process communication event, and the like.
Specifically, in this embodiment, the originally disordered storage event is divided into two events, namely a fast event and a slow event, which are independent from each other, and each event can be processed by using a respective corresponding processing path (i.e., the fast event or the slow path), so that the data storage performance of the storage controller is improved, and the delay of the storage controller for data storage is reduced.
Correspondingly, for the specific manner of distinguishing the fast event and the slow event by the storage controller in this embodiment, the specific manner may be set by a designer according to a practical scenario and a user requirement, for example, the storage controller may directly distinguish the fast event corresponding to the fast path and the slow event corresponding to the slow path through the setting of the hardware circuit structure, for example, the storage controller may directly transmit the storage event (e.g., IO event) received by the FC port to the plurality of CPU cores corresponding to the corresponding fast paths, so as to store the data to be stored in the storage event through step 102. The storage controller can also distinguish a fast event from a slow event by detecting the acquired storage event; after the processor such as the storage controller acquires the storage event, whether the storage event is a fast event can be detected and judged; if yes, go to step 102; if not, go to step 103.
Step 102: if the storage event is a fast event, processing the storage event by using a fast path, and storing the data to be stored in the storage event into a corresponding hard disk; the fast path is a path for processing a fast event by a plurality of CPU cores in the memory controller together.
It can be understood that the fast path in this step may be a processing path in which multiple (i.e., greater than or equal to 2) CPU cores process a storage event (i.e., a fast event) together, that is, multiple CPU cores corresponding to the fast path may process a part of a processing procedure of the fast event corresponding to each fast path, respectively, so as to implement pipeline processing of the fast event concurrency, as shown in fig. 3, when an IO event (I/O # 1 and I/O #2) is processed by using the fast paths corresponding to 4 CPU cores (CPU # 0 to CPU #3), after the fast path starts processing the I/O # 1, the I/O # 2 may start processing only by waiting for 10us on a Time axis (Time flush), instead of waiting for 50us for processing the slow path shown in fig. 4, so as to reduce the delay. That is, in the fast path, the task granularity is smaller, the resource allocation is more, the corresponding processing is more timely, and the method is suitable for processing most of events (such as IO events) on the IO path.
Specifically, the embodiment may further include a setting process of the fast path corresponding to the acquired storage event (i.e., the fast event) in this step, for example, the processor may perform slice segmentation on the processing path of the fast event to acquire a preset number of uncoupled sub-paths; binding a preset number of sub paths to a preset number of CPU cores by utilizing a CPU affinity binding technology; wherein each sub-path corresponds to a CPU core. That is to say, in this embodiment, slice segmentation may be performed on the processing path of the fast event, the processing path is decomposed into a preset number of processing processes (i.e., sub-paths) without coupling, and then the processing processes corresponding to the preset number of CPU cores are processed by combining the CPU affinity binding technology, so as to implement pipeline processing of true concurrence of the fast event, thereby ensuring that the consumption of IO average delay is reduced, the overall concurrence of software is further improved, and finally the overall performance of the system is improved.
Step 103: if the storage event is a slow event, processing the storage event by using a slow path, and storing the data to be stored in the storage event into a corresponding hard disk; the slow path is a path for processing a slow event by a single CPU core in the memory controller.
It can be understood that the slow path in this step may be a processing path where a single CPU core processes a storage event (i.e., a slow event), that is, a single CPU core corresponding to the slow path may process all processing processes of the slow event, as shown in fig. 4, when two slow events are processed by using the slow path corresponding to one CPU core (CPU # n), after the slow path starts processing a first slow event, a second slow event on a Time axis (Time flush) needs to wait for 50us to start processing. That is, in the slow path, the resource allocation is low, the task granularity is larger, the scheduling period is longer, and the method is suitable for processing slow or low-frequency events (i.e. slow events), such as logging events, command line processing events, and inter-process communication events.
Correspondingly, the purpose of this step may be to separately process the slow event in the storage event by using the slow path corresponding to the single CPU core, so as to distinguish the slow event from the fast event, and avoid the influence of the processing of the slow event on the processing of the fast event.
Specifically, the specific selection of the single CPU core corresponding to the slow path in this step may be set by a designer or a user according to a practical scenario and a user requirement, for example, the single CPU core corresponding to the slow path may be a fixed CPU core in the CPU, that is, the CPU core corresponding to the slow path may specifically be a fixed CPU core in the memory controller, and for example, the CPU core may only process a slow event but may not process a fast event. The single CPU core corresponding to the slow path may also be a CPU core that does not process a fast event in the CPU (i.e., a target CPU core); that is to say, the CPU core corresponding to the slow path may specifically be a target CPU core in the storage controller, where the target CPU core is any CPU core in the storage controller that has not processed the fast event; for example, when a fast event is not processed by one of the plurality of CPU cores corresponding to the fast path, the CPU core may be used as a target CPU core to process a slow event. This embodiment does not set any limit to this.
In the embodiment, through the arrangement of the fast path and the slow path, as if the road is divided into a motorway and a non-motorway, originally disordered storage events are divided into two events, namely the fast event and the slow event which are independent from each other, so that each event can be stably operated and processed according to the respective processing speed, and the transport capacity of the road is improved, thereby improving the data storage performance of the storage controller, reducing the data storage delay of the storage controller, and enabling the storage controller to meet the increasingly improved capacity of the server by utilizing faster delay.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a data storage device of a storage controller according to an embodiment of the present invention. The device can be applied to a storage controller and comprises:
an obtaining module 10, configured to obtain a storage event; the storage event is a fast event or a slow event, and the fast event comprises an IO event;
the first storage module 20 is configured to, if the storage event is a fast event, process the storage event by using a fast path, and store data to be stored in the storage event in a corresponding hard disk; the fast path is a path for processing a fast event by a plurality of CPU cores in the storage controller together;
the second storage module 30 is configured to, if the storage event is a slow event, process the storage event by using a slow path, and store data to be stored in the storage event in a corresponding hard disk; the slow path is a path for processing a slow event by a single CPU core in the memory controller.
Optionally, the single CPU core corresponding to the slow path may be specifically a fixed CPU core in the memory controller.
Optionally, the single CPU core corresponding to the slow path may specifically be a target CPU core in the memory controller; the target CPU core is any CPU core which does not process the quick event in the storage controller.
Optionally, the apparatus may further include: the fast path setting module is used for setting a fast path;
the fast path setting module may include:
the slicing submodule is used for slicing and dividing the processing path of the rapid event to obtain a preset number of uncoupled subpaths; wherein the preset number is greater than or equal to 2;
the binding submodule is used for binding the sub paths with the preset number to the CPU cores with the preset number by utilizing the CPU affinity binding technology; wherein each sub-path corresponds to a CPU core.
Optionally, the apparatus further comprises:
the judging module is used for storing whether the event is a quick event or not; if yes, sending a first starting signal to the first storage module; and if not, sending a second starting signal to the second storage module.
In the embodiment, through the arrangement of the fast path and the slow path, as if the road is divided into a motorway and a non-motorway, originally disordered storage events are divided into two events, namely the fast event and the slow event which are independent from each other, so that each event can be stably operated and processed according to the respective processing speed, and the transport capacity of the road is improved, thereby improving the data storage performance of the storage controller, reducing the data storage delay of the storage controller, and enabling the storage controller to meet the increasingly improved capacity of the server by utilizing faster delay.
An embodiment of the present invention further provides a storage controller, including: a memory for storing a computer program; and a processor, configured to implement the steps of the data storage method of the storage controller provided in the foregoing embodiments when executing the computer program. Of course, the storage controller may also include various network interfaces (e.g., FC ports), power supplies, and the like.
In addition, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed, the computer program may implement the steps of the data storage method of the storage controller provided in the foregoing embodiment. The storage medium may include: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device, the storage controller and the computer-readable storage medium disclosed by the embodiments correspond to the method disclosed by the embodiments, so that the description is simple, and the relevant points can be referred to the description of the method part.
The data storage method and device of the storage controller, the storage controller and the computer readable storage medium provided by the invention are described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (7)
1. A data storage method of a storage controller, comprising:
the storage controller acquires a storage event; the storage event is a fast event or a slow event, the fast event comprises an IO event, and the slow event comprises a log recording event, a command line processing event and an inter-process communication event;
if the storage event is the fast event, processing the storage event by using a fast path, and storing the data to be stored in the storage event into a corresponding hard disk; the fast path is a path for a plurality of CPU cores in the storage controller to jointly process the fast event;
if the storage event is the slow event, processing the storage event by using a slow path, and storing the data to be stored in the storage event into a corresponding hard disk; wherein the slow path is a path for a single CPU core in the memory controller to process the slow event;
the single CPU core corresponding to the slow path is specifically a target CPU core in the storage controller; wherein the target CPU core is any one of the CPU cores in the storage controller which does not process the fast event;
after the storage controller acquires the storage event, the method further comprises the following steps:
the storage controller judges whether the storage event is the fast event or not;
if so, executing the step of processing the storage event by using the fast path and storing the data to be stored in the storage event into a corresponding hard disk;
if not, executing the step of processing the storage event by using the slow path and storing the data to be stored in the storage event into a corresponding hard disk.
2. The data storage method of the storage controller according to claim 1, further comprising: setting the fast path; the fast path setting process comprises the following steps:
slicing and dividing the processing path of the rapid event to obtain a preset number of uncoupled subpaths; wherein the preset number is greater than or equal to 2;
binding the preset number of the sub-paths to the preset number of CPU cores by utilizing a CPU affinity binding technology; and each sub-path corresponds to one CPU core.
3. The data storage method of claim 1, wherein the single CPU core corresponding to the slow path is specifically a fixed CPU core in the storage controller.
4. A data storage device of a storage controller, comprising:
the acquisition module is used for acquiring the storage event; the storage event is a fast event or a slow event, the fast event comprises an IO event, and the slow event comprises a log recording event, a command line processing event and an inter-process communication event;
the first storage module is used for processing the storage event by using a fast path and storing data to be stored in the storage event into a corresponding hard disk if the storage event is the fast event; wherein the fast path is a path for a plurality of CPU cores in the storage controller to jointly process the fast event;
the second storage module is used for processing the storage event by using a slow path and storing data to be stored in the storage event into a corresponding hard disk if the storage event is the slow event; wherein the slow path is a path for a single CPU core in the memory controller to process the slow event;
the single CPU core corresponding to the slow path is specifically a target CPU core in the storage controller; wherein the target CPU core is any one of the CPU cores in the storage controller which does not process the fast event;
the judging module is used for judging whether the storage event is the quick event or not; if yes, sending a first starting signal to the first storage module; and if not, sending a second starting signal to the second storage module.
5. The data storage device of the storage controller of claim 4, further comprising: the quick path setting module is used for setting the quick path;
the fast path setting module includes:
the slicing submodule is used for slicing and dividing the processing path of the rapid event to obtain a preset number of uncoupled subpaths; wherein the preset number is greater than or equal to 2;
a binding submodule, configured to bind the preset number of sub paths to the preset number of CPU cores by using a CPU affinity binding technique; and each sub-path corresponds to one CPU core.
6. A storage controller, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the data storage method of the storage controller of any of claims 1 to 3 when executing said computer program.
7. A computer-readable storage medium, characterized in that a computer program is stored thereon, which computer program, when being executed by a processor, carries out the steps of the data storage method of a storage controller according to any one of claims 1 to 3.
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