CN111988229B

CN111988229B - Compression storage and quick searching system and method for IP and MAC address mapping table

Info

Publication number: CN111988229B
Application number: CN202010835229.2A
Authority: CN
Inventors: 邓政; 郑容�; 刘望; 陈伯芳; 詹万鹏; 危必波; 张小波; 王永业; 陈默; 王越
Original assignee: WUHAN ZHONGYUAN HUADIAN SOFTWARE CO Ltd
Current assignee: WUHAN ZHONGYUAN HUADIAN SOFTWARE CO Ltd
Priority date: 2020-08-19
Filing date: 2020-08-19
Publication date: 2022-06-24
Anticipated expiration: 2040-08-19
Also published as: CN111988229A

Abstract

The invention discloses a compression storage and quick searching system and method for IP and MAC address mapping table, in the system: the register group is used for storing the IP field of the amplification probability and the corresponding life cycle countdown timer; setting a plurality of register groups, numbering the register groups in sequence, and expressing the corresponding approximate IP fields by the corresponding numbers of the register groups; the storage unit array is used for storing an array formed by data blocks, the row number of the array is the power of addressing bit width of 2, and the addressing bit width is the bit width of an addressing field; the column number is the number of allowed conflict points, and the allowed conflict points are IP addresses with the same addressing field but different IP fields or other fields with high probability; the data structure of the data block is: other fields, MAC address, number corresponding to register group, and life cycle countdown timer corresponding to the data block. The invention is realized based on hardware, reduces the load of a CPU, improves the efficiency of storage and search, can reduce the size of a storage unit and realizes quick query.

Description

Compression storage and quick searching system and method for IP and MAC address mapping table

Technical Field

The invention relates to the technical field of network communication, in particular to a system and a method for compressed storage and quick search of an IP and MAC address mapping table.

Background

The IP address can be planned to be used in the network, when a host wants to join the network, a certain IP address is allocated to the host for use, when the host leaves the network, the IP address previously allocated to the host can be reused by another new host, therefore, the user needs to know which IP address is used by which device in real time in network communication, and the unique ID of the mark device is the MAC address of the mark device. It is therefore necessary to store the latest mapping of IP addresses to MAC addresses within the network.

In conventional devices this part of the work is done by the CPU. The work mode of the CPU is serial, namely, when executing a certain task, the CPU can not execute other tasks, only one task can be done at a time, and if the efficiency of the CPU for processing other tasks is improved, partial work of the CPU needs to be released. The FPGA has the obvious advantages that due to the parallel work and the programmable property of the FPGA and certain storage units (no external DDR is needed, and the cost is saved), the FPGA is selected to replace the CPU to process the part of work.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide a system and method for compressed storage and fast lookup of IP and MAC address mapping tables, aiming at the defects in the prior art.

The technical scheme adopted by the invention for solving the technical problems is as follows:

the invention provides a compression storage and quick searching system for IP and MAC address mapping table, comprising:

an IP address splitting unit, configured to divide an IP address into: a high probability IP field, an addressing field, other fields; the division rule is as follows: the IP address is expressed by binary number, and is divided by 8 bit as unit, the IP address of 32 bit is divided into 4 fields, and the fields are converted into decimal, namely, a dot decimal description method is adopted, and a rough probability threshold value is preset; which field has the least decimal number, and is divided into addressing fields; the fields which are the same are divided into the large probability fields when the times of the fields exceed the large probability threshold; the non-selected field is the other field;

the register group is used for storing the IP field of the amplification probability and the corresponding life cycle countdown timer; setting a plurality of register groups, numbering the register groups in sequence, and expressing the corresponding approximate IP fields by the corresponding numbers of the register groups;

the storage unit array is used for storing an array formed by data blocks, the row number of the array is the power of addressing bit width of 2, and the addressing bit width is the binary bit width of an addressing field; the column number is the number of allowed conflict points, and the allowed conflict points are IP addresses with the same addressing field but different IP fields or other fields with high probability; the data structure of the data block is: other fields, MAC addresses, numbers corresponding to the register groups and a life cycle countdown timer corresponding to the data block;

the address writing unit is used for acquiring an IP address to be written and a corresponding MAC address, and writing the IP address and the MAC address into the address writing unit according to the data structures of the register group and the storage unit array;

and the address reading unit is used for acquiring the IP address to be read, reading the storage unit array according to the addressing field, further reading the register group according to the read number, and returning the MAC address stored in the data block after the reading is successful.

Further, the data structure in the register set of the present invention is specifically:

high probability IP field: the number is marked as IP [ m: n ], and the IP address interval is represented by an upper limit marker n and a lower limit marker m of a dynamically specified large probability field;

life cycle countdown of register set: it is recorded as reg _ alive _ s _ time, and a timer with 16 bit width is adopted to satisfy the requirement of TCP _ IP protocol.

Further, the number of register sets of the present invention is:

the number of the register group is marked as reg _ id, if the bit width of the number reg _ id is k, the number reg _ id describes the register group of the k power of 2 at most, and in order to save resources, the minimum integer value meeting the condition is selected as the number of the register groups.

Further, the data structure in the data block of the memory cell array of the present invention is specifically:

other fields: the length is marked as others _ IP, namely the value of the IP address except the high-probability IP field and the addressing field is N bytes;

MAC address: the length is recorded as mac _ addr and is 6 bytes;

the number corresponding to the register group is recorded as reg _ id;

the lifecycle countdown timer corresponding to the data block is recorded as block _ alive _ s _ time, and the length of reg _ id and block _ alive _ s _ time is 2 bytes.

Furthermore, the system of the invention is also provided with a global zero clearing function, and when zero clearing is needed, each unit of the CPU control system returns to the original state again.

The invention provides a compression storage and quick searching method for an IP and MAC address mapping table, which comprises the following steps:

writing process of the address mapping table: acquiring an IP address to be written and a corresponding MAC address, and writing the IP address and the MAC address into a register group and a storage unit array according to the data structure of the register group and the storage unit array;

reading process of the address mapping table: and acquiring the IP address to be read, reading the storage unit array according to the addressing field, reading the register group according to the read number, and returning the MAC address stored in the data block after the reading is successful.

Further, the specific steps of the write flow of the address mapping table of the present invention are:

w1: generating an IP address wr _ req _ IP to be written and a corresponding MAC address wr _ req _ MAC;

w2: accessing a plurality of data blocks in the same row in the memory cell array according to the addressing bit in the wr _ req _ ip;

w3: inquiring a corresponding register group according to the number reg _ id in each data block in the step W2 to recover the original IP address;

w4: comparing wr _ req _ IP with the IPs recovered in the step W3, wherein if matching indicates that the IP is recorded; the step W5 is entered after recording, and the steps W6 and W7 are entered in order if no recording is entered;

w5: writing the wr _ req _ mac into a mac _ addr unit, and resetting block _ alive _ s _ time in the corresponding data block to the maximum life time; meanwhile, the reg _ alive _ s _ time in the register corresponding to the number reg _ id is reset to the maximum life time; the write operation is completed;

w6: the content in the register group is viewed, and the content is divided into three conditions:

a: when the matching register value exists, the reg _ alive _ s _ time is reset to the maximum life time, and the step W7 is carried out;

b: if no matching value exists but a free register exists, writing the high-probability IP field into the free register, resetting reg _ alive _ s _ time to the maximum life time, and entering step W7;

c: when no matching register exists and no idle register exists, the whole register group and the storage unit array are reset, the condition belongs to abnormal regression, and abnormal emptying is reported to the CPU; at this point, the operation is completed abnormally;

w7: looking up the addressed data blocks in the storage unit array, finding out the data block with the minimum block _ alive _ s _ time, writing wr _ req _ mac into a mac _ addr unit, writing other fields in wr _ req _ ip into an others _ ip unit, and resetting the block _ alive _ s _ time to the maximum life time; this time the write operation is complete.

Further, the specific steps of the reading process of the address mapping table of the present invention are:

r1: generating an IP address rd _ req _ IP to be read;

r2: accessing a plurality of data blocks in the same row in the memory cell array according to the addressing field of the IP address rd _ req _ IP in the step R1;

r3: inquiring a corresponding register group according to reg _ id in each data block in the step R2 to recover an original IP value;

r4: comparing rd _ req _ IP with the respective IP recovered in step R3, a match indicating that it has been recorded; the recorded entry step R5, and the unrecorded entry step R6;

r5: after the reply operation is completed, reading successfully, and returning the mac _ addr in the data block;

r6: the reply operation is complete and the read fails.

The invention has the following beneficial effects: the invention provides a hardware-implemented and dynamic IP and MAC address mapping table storage scheme, which compresses and stores a source IP and a source MAC address carried in an input ARP message according to the requirement of a TCP _ IP protocol, records an address mapping table of a current active device in the system and responds to the address access operation of an upstream module. The dynamic updating scheme is provided, any address conversion in a network is recorded in real time, the whole recording and inquiring process is automatically completed by the FPGA, the participation of a CPU is not needed, a DDR is not required to be hung externally, the cost is saved, the recording and inquiring efficiency is improved, the CPU overhead is reduced, and the storage and searching efficiency is improved; aiming at the mapping characteristics of the IP and the MAC address, the size of a storage unit is reduced, and quick query is realized; the invention dynamically appoints the large probability field according to the characteristics of the IP set in the application system, thereby realizing dynamic storage.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

FIG. 1 is a flow chart of the writing of an address mapping table according to an embodiment of the present invention;

fig. 2 is a read flow of the address mapping table according to the embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The compression storage and quick searching system for the IP and MAC address mapping table of the embodiment of the invention comprises:

an IP address splitting unit, configured to divide an IP address into: a high probability IP field, an addressing field, other fields; the IP address in communication is binary number, and is usually divided in 8-bit units, for example, the IP address of 32 bits is divided into 4 bytes, and converted into decimal, that is, a common dot decimal description method: and a, b, c, d (wherein a, b, c and d are decimal numbers between 0 and 255), the address division is based on the number statistics of each decimal digit of the IP in the system, in addition, a rough rate threshold (judgment basis of rough rate field) needs to be preset according to experience and storage capacity, and when the statistics is finished, the decimal number of which field is the same is the least, the decimal number is divided into addressing fields. And if the number of times of the fields which are the same exceeds the maximum probability threshold value, dividing the fields into the maximum probability fields, and if the fields which are not selected are other fields. The register group is used for storing the IP field of the amplification probability and the corresponding life cycle countdown timer; setting a plurality of register groups, numbering the register groups in sequence, and expressing the corresponding approximate IP fields by the corresponding numbers of the register groups;

the storage unit array is used for storing an array formed by data blocks, the row number of the array is the power of addressing bit width of 2, and the addressing bit width is the binary bit width of an addressing field; the column number is the number of allowed conflict points, and the allowed conflict points are IP addresses with the same addressing field but different IP fields or other fields with high probability; the data structure of the data block is: other fields, MAC addresses, numbers corresponding to the register group and a life cycle countdown timer corresponding to the data block;

The data structure in the register group is specifically as follows:

high probability IP field: marking as IP [ m: n ], representing the upper limit marker n and the lower limit marker m of the dynamically specified large probability field in the IP address interval;

The set number of the register groups is as follows:

The data structure in the data block of the memory cell array is specifically as follows:

other fields: note as others _ IP, i.e. the value of the IP address except the high-probability IP field and the addressing field, the length is N bytes;

MAC address: denoted mac _ addr, length 6 bytes;

the number corresponding to the register group is recorded as reg _ id;

The system is also provided with a global zero clearing function, and when zero clearing is needed, each unit of the CPU control system returns to the original state again.

In another embodiment of the present invention, a configurable, compressed storage and dynamically recorded IP and MAC address mapping table based on FPGA is described, which provides a pure logic implementation method for address mapping storage, query and aging control without external DDR.

The embodiment of the invention provides a storage structure model aiming at the characteristics of IP addresses, which can realize lossless compression storage and quick matching search.

The same probability of the 'network numbers' in the IP address is generally larger, and the change rate is extremely low, so that the original content is not required to be stored in a mapping table, a few registers are used for storing, then a register group is coded, the codes are used for replacing original data, a CPU (central processing unit) can dynamically specify a large probability field according to the actual networking condition, and the design is more flexible.

The same probability of the 'equipment numbers' in the IP address is generally smaller, and the change rate is extremely high, so that a plurality of bits with the highest change rate can be selected as the index of the storage space, and the content can be quickly searched without storing.

If a plurality of IP index bits are the same and other IP index bits are different, the IP index bits are regarded as conflict nodes, a plurality of conflict nodes can be designed according to the board card capacity, and in order to solve the problem that the address condition of each device cannot be completely recorded, the following solution is designed: each storage node starts a life cycle countdown from the writing, the countdown is returned to 0, the content of the node is automatically cleared, and when a plurality of conflict nodes with the same index are all used, a new writing operation value is stored into the node with the minimum life cycle count (countdown). Therefore, the current active address can be recorded, and the inactive address can be dynamically cleared, so that the dynamic and sustainable operation of the whole system is ensured. In the system:

the storage interval is divided into two parts: register groups and memory cell arrays.

The register set is used to store the IP field with amplification probability, and its structure is shown in table 1, where reg _ alive _ s _ time is a life cycle countdown timer (in implementation, a 16-bit wide timer is designed enough to meet the TCP _ IP protocol requirement), and m and n of the IP interval are: the dynamically-assigned upper and lower limiting marks of the large probability field can observe the IP address used at ordinary times, most fields have smaller change with the IP address in the network, but different networks have possibly smaller change fields which are not the same, so that the interval of the field with small change can be found according to the characteristics of the field IP, namely the upper and lower limiting marks of the large probability field are mentioned here, and the partial contents are stored in the register in the table 1, and each large probability field with different contents corresponds to one register group.

Table 1: register set structure

Thirdly, because the table 1 stores fields with small changes, the number of register groups is not large, the registers can be numbered, the original long content is replaced by a small number of numbers, the numbers are expressed by reg _ id, the bit width of the reg _ id is determined according to the number of the register groups in the table 1, if the bit width is k, the reg _ id describes at most 2 register groups raised to the power of k, and the minimum integer value meeting the condition is selected for saving resources.

The structure of the memory cell array is shown in table 2, where the number of rows is the power of "addressing bit width" of 2, for example, the addressing bit width is 8 bits, the number of rows is 256, and the number of columns is the number of allowed collision points, and the IP with the same addressing value but different contents is stored. Addressing address we generally choose a field that changes faster, generally use the lowest byte as the addressing address, such as 192.168.2.56, 192.168.3.56, and if we use the lowest byte as the addressing address (its addressing bit width is 8), the address behavior 56 needs to use two data blocks in the same row to store separately because the next lowest byte of two IPs is different.

Each element of the array is called a data block, the structure of the data block is shown in table 3, block _ alive _ s _ time in the structure of the data block is a life cycle countdown timer, reg _ id is a corresponding register code, mac _ addr is a mac address, and the first N bytes store values except a large byte and an addressing byte in the IP. Since it was mentioned that the most probable bytes are stored in table 1, the addressing address is used as the row number, and no extra storage is needed, so that only the remaining IP fields in table 2 that are not categorized need to be stored, and the contents will be filled into others _ IP.

Table 2: memory array structure

Table 3: data block patterning

Fifthly, writing in the address mapping table: (assume: the addressing bit is the lower 8 bits of IP, 256 x 16 memory cell arrays, 16 register sets)

W1: the ARP resolution module (also implemented by FPGA, but not within the scope of the description herein) generates the IP address (wr _ req _ IP) that needs to be written, the corresponding MAC address (wr _ req _ MAC).

W2: from the lower 8 bits of the IP in step W1, the 16 data blocks of the same row in table 2 are accessed. Table 2 is written with all zeros at power-on initialization, which ensures that each node is invalid before invalid writing, and is valid only after data is written in the valid period of the data, and the valid flag indicates that block _ alive _ s _ time corresponding to the node is greater than 0, and is equal to 0, which indicates that the node has failed. Certainly, in the running process, a function of global zero clearing of the CPU is designed, and the CPU is ensured to return all the nodes to the original state again when needed.

W3: and (5) according to the reg _ id table lookup 1 register group in each data block in the step W2, recovering the original IP address.

W4: comparing wr _ req _ IP with the recovered IPs in step 3, a match indicates that it has been recorded. The process proceeds to step W5 after recording, and proceeds to steps W6 and W7 after no recording.

W5: and writing the wr _ req _ mac into a mac _ addr unit, and resetting the block _ alive _ s _ time in the data block of the recording unit to the maximum life time. And meanwhile, resetting reg _ alive _ s _ time in a reg _ id corresponding register to the maximum life time. This operation is completed. The others _ IP portion in table 2 is not updated since this step is entered if the IP value has already been recorded.

W6: looking at the contents of the registers in Table 1, there are three cases:

A. when the matching register value exists, the reg _ alive _ s _ time is reset to the maximum life time, and the step W7 is carried out;

B. if there is no match value but there is a free register, the large probability field may be written into the free register, reg _ alive _ s _ time is reset to the maximum lifetime, and step W7 is entered.

C. And when no matching register exists and no idle register exists, resetting the whole register and the storage array, wherein the condition belongs to abnormal regression and needs to report abnormal emptying to the CPU. At which point the operation is completed abnormally.

W7: looking at the addressed 16 nodes in the storage array, finding out the data block with the minimum block _ alive _ s _ time, writing wr _ req _ mac into a mac _ addr unit, writing other values except a large probability field stored in a register in a table 1 and a small probability field serving as an addressing address in wr _ req _ ip into an others _ ip unit, and resetting the block _ alive _ s _ time to the maximum life time. The reply operation is complete.

Sixthly, reading process of address mapping table

R1: the upstream module generates the IP address (rd _ req _ IP) that needs to be read.

R2: from the lower 8 bits of the IP in step R1, the 16 data blocks in the same row in table 2 are accessed.

R3: and (4) according to the reg _ id table lookup 1 register group in each data block in the step R2, recovering the original IP value.

R4: comparing rd _ req _ IP with the recovered IPs in step R3, a match indicates that it has been recorded. The record proceeds to step R5, and the record does not proceed to step R6.

R5: the reply operation is complete, the read is successful, and the mac _ addr in the data block is returned.

R6: the reply operation is complete and the read fails.

It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.

Claims

1. A system for compressed storage and fast lookup of IP and MAC address mapping tables, the system comprising:

an IP address splitting unit, configured to divide an IP address into: a high probability IP field, an addressing field, other fields; the division rule is as follows: the IP address is represented by binary number, and is divided by 8 bits, the IP address of 32 bits is divided into 4 fields, and the fields are converted into decimal, namely, a dot decimal description method is adopted, and a large probability threshold value is preset; which field has the least decimal number, and is divided into addressing fields; the fields which are the same are divided into the large probability fields when the times of the fields exceed the large probability threshold; if not selected, the field is other field;

the storage unit array is used for storing an array formed by data blocks, the row number of the array is the power of addressing bit width of 2, the addressing bit width is the binary bit width of an addressing field, and an addressing address is used as the row number of the storage unit array; the column number is the number of allowed conflict points, and the allowed conflict points are IP addresses with the same addressing field but different IP fields or other fields with high probability; the data structure of the data block is: other fields, MAC addresses, numbers corresponding to the register group and a life cycle countdown timer corresponding to the data block;

2. The system as claimed in claim 1, wherein the data structure in the register set is specifically:

3. The system of claim 1, wherein the number of registers is:

4. The system according to claim 1, wherein the data structure in the data block of the memory cell array is specifically:

MAC address: denoted mac _ addr, length 6 bytes;

the number corresponding to the register group is recorded as reg _ id;

5. The system as claimed in claim 1, wherein the system further comprises a global zero clearing function, and each unit of the CPU control system returns to the original state again when the zero clearing is required.

6. A compressed storage and fast lookup method for IP and MAC address mapping table, which employs the compressed storage and fast lookup system for IP and MAC address mapping table of claim 1, comprising the following steps:

7. The method as claimed in claim 6, wherein the step of writing the address mapping table comprises:

w2: accessing a plurality of data blocks in the same row in the memory cell array according to the addressing bits in the wr _ req _ ip;

w4: comparing the wr _ req _ IP with the IPs recovered in the step W3, wherein if the matching indicates that the IP is recorded; the step W5 is entered after recording, and the steps W6 and W7 are entered in order if no recording is entered;

w6: the content in the register group is viewed, and the three conditions are divided into:

8. The method as claimed in claim 6, wherein the step of reading the address mapping table comprises:

r1: generating an IP address rd _ req _ IP to be read;

r4: comparing rd _ req _ IP with the respective IP recovered in step R3, a match indicating that it has been recorded;

record-passed step R5, record-not-passed step R6;

r5: after the reply operation is completed and the reading is successful, returning the mac _ addr in the data block;

r6: the reply operation is complete and the read fails.