CN111984477A - PCIe equipment signal parameter dynamic correction device and method - Google Patents
PCIe equipment signal parameter dynamic correction device and method Download PDFInfo
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The invention provides a PCIe equipment signal parameter dynamic correction device and a method, wherein the device comprises: an error rate configuration unit, configured to configure a TLP layer error retransmission rate; the test template unit is used for providing a plurality of test templates for selecting a required test sending sequence; the emphasis and pre-emphasis parameter adjusting unit is used for automatically and dynamically adjusting and correcting the eq/deq parameter under a standard mode specified by a PCIe protocol aiming at the output and the input of a PCIe link respectively; the loop test unit is used for marking a loop mark on the test sending sequence and then sending the test sending sequence; the data integrity checking unit is used for carrying out cyclic redundancy code checking and link cyclic redundancy code checking on the end-to-end of the PCIe link so as to judge whether the PCIe link signal is deteriorated; and the data comparison unit is used for comparing the test sending sequence sent by the PCIe interface with the received decoded data in the test mode. The invention is realized in the chip, can be tested by directly connecting the EP device of the opposite terminal, has low cost, is automatically carried out and has high efficiency.
Description
Technical Field
The invention relates to the technical field of chip production, in particular to a device and a method for dynamically correcting PCIe equipment signal parameters.
Background
PCIe (PCIe express) interface is a bus interface, and uses point-to-point serial connection, and compared to PCI and earlier shared parallel architectures of computer buses, each device has its own dedicated connection, and does not need to request bandwidth from the entire bus, and can increase the data transfer rate to a very high frequency, reaching a high bandwidth that PCI cannot provide, and thus becoming a mainstream bus interface in the industry at present.
In practical use, the existing host device and PCIe interface signals are not completely adapted, and therefore a signal compatibility test needs to be performed on the host device, and at present, a specific practice is to use a PCIe association test fixture to perform an internal loop bandwidth signal-to-noise test, that is, connect the PCIe association test fixture to a PCIe slot of the host device, use a signal generator to send a TX signal, and compare the TX signal with a returned signal to obtain a test result, where the test flow is only from the chip output end to the last slot for the version. However, the PCIe association test fixture is a large test device, which is expensive, and is only used by the manufacturer of the chip or host device, which is an unbearable cost for many users.
Even some host equipment manufacturers can directly use the signal data set by the chip manufacturers, and the chip manufacturers need to use an evaluation board (a PCB board provided with a chip and external equipment) for reference and tuning parameters of the evaluation board for clients after the chips are produced. Therefore, some manufacturers of host equipment may directly use the chip manufacturers to evaluate the tuning parameters of the board, which brings about a certain hidden danger for the following reasons:
(1) the external equipment has larger randomness, can only be compatible with most products, and cannot be completely compatible;
(2) after multi-stage bridging, impedance parameters change greatly, which greatly affects signals, causes the increase of retransmission rate and affects power consumption and performance;
(3) the signal parameters with better level adaptation can be degraded along with the change of the use environment.
Based on this, this case is under the condition that does not increase board level hardware and produces the line station, directly realizes a PCIe equipment parameter's dynamic correction device and method in the chip inside, need not to increase purchase costs such as PCIe association's test fixture, and no matter be the producer or the end user can carry out the test as required.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a device and a method for dynamically correcting PCIe equipment signal parameters, which are realized in a chip, and an EP (Internet protocol) device directly connected with an opposite end can be tested without increasing the purchase cost of test fixtures of a PCIe association and the like and increasing board-level hardware and production line stations.
In a first aspect, the present invention provides a PCIe device signal parameter dynamic correction apparatus, which is characterized in that: set up in the inside chip of PCIe device, and include:
an error rate configuration unit, configured to receive a configuration of a TLP layer error retransmission rate by a user, where the TLP layer error retransmission rate is recorded as an error rate;
the test template unit is used for providing a plurality of test templates for a user to select the required test template, and each test template stores a test sending sequence;
the emphasis and pre-emphasis parameter adjusting unit is used for automatically and dynamically adjusting and correcting the eq/deq parameter under a standard mode specified by a PCIe protocol aiming at the output and the input of a PCIe link respectively;
the loop test unit is used for marking a loop mark on the test sending sequence in a test state and then sending the test sending sequence;
the data integrity checking unit is used for checking the cyclic redundancy codes of the end-to-end of the PCIe link and the cyclic redundancy codes of the link, and judging that the PCIe link signal is deteriorated when the cyclic redundancy codes and the cyclic redundancy codes of the link are incomplete;
the error rate counting unit is used for counting the error rate under the condition that PCIe link signals are deteriorated, and when the error rate reaches the configuration value of the error rate configuration unit, the emphasis and pre-emphasis parameter adjustment unit is automatically triggered to enter a dynamic adjustment and correction function, and the loop test unit enters a test state;
and the data comparison unit is used for transferring the test sending sequence sent by the loop test unit to the opposite-end EP device in a test state, receiving decoded data returned by the opposite-end EP device, comparing the test sending sequence with the decoded data, and feeding a comparison result back to the emphasis and pre-emphasis parameter adjustment unit.
In a second aspect, the present invention provides a PCIe device signal parameter dynamic correction method, which is implemented inside a chip, and includes the following steps:
s1, accepting the configuration of the test mode by the user through the mode selection unit; receiving the configuration of a user on the TLP layer error retransmission rate through an error rate configuration unit, wherein the TLP layer error retransmission rate is recorded as an error rate; providing a plurality of test sending sequences for a user to select through a test template unit;
s2, after configuration is completed, enabling the PCIe link to be connected with an EP device at the opposite end for normal use, carrying out end-to-end cyclic redundancy code check and link cyclic redundancy code check through the data integrity check unit, starting the error rate statistical unit to carry out statistics on the error rate in unit time if the cyclic redundancy code check and the link cyclic redundancy code are incomplete, and automatically triggering the dynamic correction function of PCIe device signal parameters if the error rate reaches the configuration value of the error rate configuration unit;
s3, triggering the emphasis and pre-emphasis parameter adjustment unit to automatically and dynamically adjust eq/deq parameters, and then triggering the loop test unit to enable the opposite end EP device to enter a loop test mode;
s4, in a loop test mode, a test sending sequence is taken out from the test template selected by the user, sent out after a loop test unit marks a loop mark, sent out to the opposite end EP device through a PCIe interface by a data comparison unit, and then the data comparison unit receives the returned data decoded by the opposite end EP device;
s5, comparing the sent test sending sequence with the received decoded data by the data comparing unit to see whether the test sending sequence is consistent with the received decoded data, if so, indicating that the eq/deq parameter is a proper parameter, and ending the process; if not, the process returns to step S3.
One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages: the device and the method provided by the embodiment of the application are realized in a chip, and the EP device directly connected with the opposite end can be tested without increasing the purchase cost of testing clamps and the like of PCIe association and without increasing board level hardware and production line stations. And a plurality of configuration units are provided, for example, the configuration of the user on the test mode can be received through the mode selection unit, the configuration of the user on the error retransmission rate of the TLP layer can be received through the error rate configuration unit, a plurality of test sending sequences are provided for the user to select through the test template unit, and the configuration of the user on the test mode can be received through the mode selection unit, so that the test is more diversified, and the test result is more accurate and reasonable. And because an AER mechanism in a PCIe protocol can be adopted to count the error rate in real time, and the test is triggered through the error rate, the parameter correction can be carried out in the operation process of the external PCIe equipment, and the aim of dynamically adjusting the signal parameters is fulfilled.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
FIG. 1 is a schematic block diagram of the system of the present invention;
FIG. 2 is a schematic structural diagram of an apparatus according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method according to a second embodiment of the present invention.
Detailed Description
The embodiment of the application provides the device and the method for dynamically correcting the PCIe equipment signal parameters, which are realized in a chip, and the EP equipment directly connected with the opposite end can be tested without increasing the purchase cost of test fixtures and the like of a PCIe association and without increasing board-level hardware and production line stations.
The technical scheme in the embodiment of the application has the following general idea: the method is realized in the chip, the EP device directly connected with the opposite end can be tested, a plurality of configuration units are arranged, such as an error rate configuration unit, a test template unit and a mode selection unit, and under the configuration of a user, more diversified tests are provided. The eq/deq parameter can be automatically adjusted in a standard mode specified by the PCIe protocol by setting the emphasis and pre-emphasis parameter adjustment unit until the appropriate eq/deq parameter. The test is completely automatic, the purchase cost of a test fixture of a PCIe association and the like is not required to be increased, the board level hardware and the production line station are not required to be increased, and the test cost and the error rate are greatly reduced.
Before describing the specific embodiment, a system framework during testing according to the embodiment of the present application is described, and as shown in fig. 1, the system framework during testing is divided into a chip and two pairs of end EP devices:
the chip belongs to PCIe equipment, and the dynamic correction device and method for PCIe equipment signal parameters are realized inside the chip.
Example one
As shown in fig. 2, the present embodiment provides a dynamic PCIe device signal parameter calibration apparatus, which is disposed inside a chip of a PCIe device, and includes:
an error rate configuration unit, configured to receive a configuration of a TLP layer error retransmission rate by a user, where the TLP layer error retransmission rate is recorded as an error rate;
the test template unit is used for providing a plurality of test templates for a user to select the required test template, and each test template stores a test sending sequence;
the emphasis and pre-emphasis parameter adjusting unit is used for automatically and dynamically adjusting and correcting the eq/deq parameter under a standard mode specified by a PCIe protocol aiming at the output and the input of a PCIe link respectively; however, in practical applications, influences of various parameters of the PCIe device and the board level need to be considered, for example, unstable signal parameters of the PCIe device are considered, and data transmission failure is easily caused by signal errors, so that fine dynamic adjustment needs to be considered.
The loop test unit is used for testing the loop bandwidth of the PCIe link, and when the error rate statistic unit reaches a trigger condition, the dynamic correction function of the PCIe equipment signal parameter is automatically triggered, so that the loop test unit enters a test state and starts to test the loop bandwidth of the PCIe link;
the data integrity checking unit is used for performing cyclic redundancy code (end-to-end CRC) and link cyclic redundancy code (linkCRC) of the end-to-end of the PCIe link, and judging that the PCIe link signal is deteriorated when the cyclic redundancy code and the link cyclic redundancy code are incomplete; the cyclic redundancy check and the LINK cyclic redundancy check belong to check data of two layers of a standard PCIe LINK layer and a TLP layer, and in a PCIe communication packet, generally, the ECRC can better reflect a data state seen by an opposite-end TLP layer, and a CRC state of a LINK layer only provides a reference because data is not formally decoded yet.
The error rate counting unit is used for counting the error rate under the condition that PCIe link signals are deteriorated, and when the error rate reaches the configuration value of the error rate configuration unit, the emphasis and pre-emphasis parameter adjustment unit is automatically triggered to enter a dynamic adjustment and correction function, and the loop test unit enters a test state;
and the data comparison unit is used for transferring the test sending sequence sent by the loop test unit to the opposite-end EP device in a test state, receiving decoded data returned by the opposite-end EP device, comparing the test sending sequence with the decoded data, and feeding a comparison result back to the emphasis and pre-emphasis parameter adjustment unit.
When the weighting and pre-weighting parameter adjusting unit automatically adjusts the eq/deq parameter, the protocol recommendation value is continuously increased and decreased downwards and upwards until the upper and lower boundaries of the signal change are detected.
The error rate statistic unit is used for carrying out statistics on the error rate in unit time and comprises the following two modes:
firstly, if the opposite end EP device supports AER, the AER information of both sides is directly inquired for statistics; the error rate is counted by directly utilizing an AER mechanism in the PCIe protocol, and the dynamic correction of the PCIe device signal parameters can be easily realized.
Second, if the peer EP device does not support AER, it counts the number density of retransmission interrupts per unit time of the host interface. For example, one thousand retransmissions are implemented within one second per unit time, 1000 retransmission interruptions are generated, the bit density is marked to be 1, the bit error rate is set to be 0.5, that is, 500 retransmissions are generated within 1 second, and so on, and the PCIe device signal parameter dynamic correction can still be implemented.
As a preferred implementation manner of this embodiment, the apparatus further includes:
the mode selection unit is used for setting a test mode by a user, and the test mode comprises the following two aspects:
(1) whether the test is absolutely needed or not is judged, if the user configuration is yes, the step S2 is carried out, and if the user configuration is not, the process is ended;
(2) and testing whether subdivision into different lane granularities is needed, if the user configuration is yes, and the number of lanes is configured to be n, and circulating the steps S3 to the step 5 for each lane until n lanes are corrected.
The device of this example was tested according to the method of example two, and the specific steps are described in example two below.
In addition, it should be noted that: in a specific implementation, all units in the apparatus in this embodiment may be software modules, or may be hardware modules, or a part of the apparatus may be software modules (e.g., bit error rate configuration unit, test template unit, emphasis and pre-emphasis parameter adjustment unit, and data integrity check unit), and another part may be hardware modules (e.g., loop back test unit and data comparison unit), as long as the same functions are achieved.
Based on the same inventive concept, the application also provides a method corresponding to the device in the first embodiment, which is detailed in the second embodiment.
Example two
As shown in fig. 3, in this embodiment, a PCIe device signal parameter dynamic correction method is provided, which is implemented inside a chip, and includes the following steps:
s1, accepting the configuration of the test mode by the user through the mode selection unit; receiving the configuration of a user on the TLP layer error retransmission rate through an error rate configuration unit, wherein the TLP layer error retransmission rate is recorded as an error rate; providing a plurality of test sending sequences for a user to select through a test template unit;
s2, after configuration is completed, enabling the PCIe link to be connected with an EP device at the opposite end for normal use, carrying out end-to-end cyclic redundancy code check and link cyclic redundancy code check through the data integrity check unit, starting the error rate statistic unit to carry out statistics on the error rate in unit time if the cyclic redundancy code check and the link cyclic redundancy code are incomplete, and automatically triggering the dynamic correction function of PCIe device signal parameters if the error rate reaches the configuration value of the error rate configuration unit;
s3, triggering the emphasis and pre-emphasis parameter adjustment unit to automatically and dynamically adjust eq/deq parameters, and then triggering the loop test unit to enable the opposite end EP device to enter a loop test mode;
s4, in a loop test mode, a test sending sequence is taken out from the test template selected by the user, sent out after a loop test unit marks a loop mark, sent out to the opposite end EP device through a PCIe interface by a data comparison unit, and then the data comparison unit receives the returned data decoded by the opposite end EP device;
s5, comparing the sent test sending sequence with the received decoded data by the data comparing unit to see whether the test sending sequence is consistent with the received decoded data, if so, indicating that the eq/deq parameter is a proper parameter, and ending the process; if not, the process returns to step S3.
When the weighting and pre-weighting parameter adjusting unit automatically adjusts the eq/deq parameter, the protocol recommendation value is continuously increased and decreased downwards and upwards until the upper and lower boundaries of signal deterioration are detected.
The error rate statistic unit is used for carrying out statistics on the error rate in unit time and comprises the following two modes:
firstly, if the opposite end EP device supports AER, the AER information of both sides is directly inquired for statistics;
second, if the peer EP device does not support AER, the count is based on the retransmission interruption number density per unit time of the host interface.
As a preferred implementation manner of this embodiment, the apparatus further includes:
in step S1, the method further includes accepting, by a mode selection unit, a configuration of a test mode by a user, where the test mode includes the following two aspects:
(1) whether the test is absolutely needed or not is judged, if the user configuration is yes, the step S2 is carried out, and if the user configuration is not, the process is ended;
(2) and testing whether the lanes need to be subdivided into different lane granularities, if the user configuration is yes, and the number of the lanes is n, wherein n is larger than or equal to 2, the steps S3 and S5 are circulated for each lane until the n lanes are corrected.
Where n or more Lanes are corrected according to the same set of eq/deq parameters, or each Lane is corrected using a separate eq/deq parameter.
Since the method described in the second embodiment of the present invention is a method for performing a test by using the device in the first embodiment of the present invention, the device described in the first embodiment of the present invention and the method described in the second embodiment of the present invention are the same inventive concept, and those skilled in the art can understand the corresponding functions of the device and the method, and thus will not be described herein again.
The technical scheme provided in the embodiment of the application at least has the following technical effects or advantages: the device and the method provided by the embodiment of the application are realized in a chip, and the EP device directly connected with the opposite end can be tested without increasing the purchase cost of testing clamps and the like of PCIe association and without increasing board level hardware and production line stations. And a plurality of configuration units are provided, for example, the configuration of the user on the test mode can be received through the mode selection unit, the configuration of the user on the error retransmission rate of the TLP layer can be received through the error rate configuration unit, a plurality of test sending sequences are provided for the user to select through the test template unit, and the configuration of the user on the test mode can be received through the mode selection unit, so that the test is more diversified, and the test result is more accurate and reasonable. And because an AER mechanism in a PCIe protocol can be adopted to count the error rate in real time, and the test is triggered through the error rate, the signal parameters can be dynamically adjusted.
Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.
Claims (9)
1. A PCIe device signal parameter dynamic correction device is characterized in that: set up in the inside chip of PCIe device, and include:
an error rate configuration unit, configured to receive a configuration of a TLP layer error retransmission rate by a user, where the TLP layer error retransmission rate is recorded as an error rate;
the test template unit is used for providing a plurality of test templates for a user to select the required test template, and each test template stores a test sending sequence;
the emphasis and pre-emphasis parameter adjusting unit is used for automatically and dynamically adjusting and correcting the eq/deq parameter under a standard mode specified by a PCIe protocol aiming at the output and the input of a PCIe link respectively;
the loop test unit is used for marking a loop mark on the test sending sequence in a test state and then sending the test sending sequence;
the data integrity checking unit is used for checking the cyclic redundancy codes of the end-to-end of the PCIe link and the cyclic redundancy codes of the link, and judging that the PCIe link signal is deteriorated when the cyclic redundancy codes and the cyclic redundancy codes of the link are incomplete;
the error rate counting unit is used for counting the error rate under the condition that PCIe link signals are deteriorated, and when the error rate reaches the configuration value of the error rate configuration unit, the emphasis and pre-emphasis parameter adjustment unit is automatically triggered to enter a dynamic adjustment and correction function, and the loop test unit enters a test state;
and the data comparison unit is used for transferring the test sending sequence sent by the loop test unit to the opposite-end EP device in a test state, receiving decoded data returned by the opposite-end EP device, comparing the test sending sequence with the decoded data, and feeding a comparison result back to the emphasis and pre-emphasis parameter adjustment unit.
2. The PCIe device signal parameter dynamic correction apparatus of claim 1, wherein: and when the weighting and pre-weighting parameter adjusting unit automatically adjusts the eq/deq parameter, the protocol recommendation value is continuously increased and decreased downwards and upwards until the upper and lower boundaries of the signal change are detected.
3. The PCIe device signal parameter dynamic correction apparatus of claim 1, wherein: the error rate statistic unit is used for carrying out statistics on the error rate in unit time and comprises the following two modes:
firstly, if the opposite end EP device supports AER, the AER information of both sides is directly inquired for statistics;
second, if the peer EP device does not support AER, the count is based on the retransmission interruption number density per unit time of the host interface.
4. The apparatus of claim 3, wherein the PCIe device signal parameter dynamic correction apparatus comprises: further comprising:
the mode selection unit is used for setting a test mode by a user, and the test mode comprises the following two aspects:
(1) whether the testing is absolutely needed or not, if the user configuration is yes, allowing the loop testing unit to enter a testing state so as to dynamically correct PCIe equipment signal parameters, and if the user configuration is not yes, ending the process;
(2) and testing whether the lans need to be subdivided into different lane granularities, and if the user configuration is yes and the number of the lanes is configured to be n, respectively performing PCIe device signal parameter dynamic correction on each lane until n lanes are corrected.
5. A PCIe device signal parameter dynamic correction method is characterized in that: is realized inside a chip and comprises the following steps:
s1, accepting the configuration of the test mode by the user through the mode selection unit; receiving the configuration of a user on the TLP layer error retransmission rate through an error rate configuration unit, wherein the TLP layer error retransmission rate is recorded as an error rate; providing a plurality of test sending sequences for a user to select through a test template unit;
s2, after configuration is completed, enabling the PCIe link to be connected with an EP device at the opposite end for normal use, carrying out end-to-end cyclic redundancy code check and link cyclic redundancy code check through the data integrity check unit, starting the error rate statistic unit to carry out statistics on the error rate in unit time if the cyclic redundancy code check and the link cyclic redundancy code are incomplete, and automatically triggering the dynamic correction function of PCIe device signal parameters if the error rate reaches the configuration value of the error rate configuration unit;
s3, triggering the emphasis and pre-emphasis parameter adjustment unit to automatically and dynamically adjust eq/deq parameters, and then triggering the loop test unit to enable the opposite end EP device to enter a loop test mode;
s4, in a loop test mode, a test sending sequence is taken out from the test template selected by the user, sent out after a loop test unit marks a loop mark, sent out to the opposite end EP device through a PCIe interface by a data comparison unit, and then the data comparison unit receives the returned data decoded by the opposite end EP device;
s5, comparing the sent test sending sequence with the received decoded data by the data comparing unit to see whether the test sending sequence is consistent with the received decoded data, if so, indicating that the eq/deq parameter is a proper parameter, and ending the process; if not, the process returns to step S3.
6. The method of claim 5, wherein the dynamic correction of the signal parameters of the PCIe device comprises: and when the weighting and pre-weighting parameter adjusting unit automatically adjusts the eq/deq parameter, the protocol recommendation value is continuously increased and decreased downwards and upwards until the upper and lower boundaries of the signal change are detected.
7. The method of claim 5, wherein the dynamic correction of the signal parameters of the PCIe device comprises: the error rate statistic unit is used for carrying out statistics on the error rate in unit time and comprises the following two modes:
firstly, if the opposite end EP device supports AER, the AER information of both sides is directly inquired for statistics;
second, if the peer EP device does not support AER, the count is based on the retransmission interruption number density per unit time of the host interface.
8. The method of claim 5, wherein the dynamic correction of the signal parameters of the PCIe device comprises: in step S1, the method further includes accepting, by a mode selection unit, a configuration of a test mode by a user, where the test mode includes the following two aspects:
(1) whether the test is absolutely needed or not is judged, if the user configuration is yes, the step S2 is carried out, and if the user configuration is not, the process is ended;
(2) and testing whether the lanes need to be subdivided into different lane granularities, if the user configuration is yes, and the number of the lanes is n, wherein n is larger than or equal to 2, the steps S3 and S5 are circulated for each lane until the n lanes are corrected.
9. The method of claim 8, wherein the dynamic PCIe device signal parameter correction method comprises: n or more Lanes are corrected according to the same set of eq/deq parameters, or each Lane is corrected using a separate eq/deq parameter.
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| CN113176963A (en) * | 2021-04-29 | 2021-07-27 | 山东英信计算机技术有限公司 | PCIe fault self-repairing method, device, equipment and readable storage medium |
| CN114443537A (en) * | 2022-01-28 | 2022-05-06 | 浪潮(山东)计算机科技有限公司 | Method, device, equipment and medium for configuring parameters of PCIE signal sending terminal |
| CN117271201A (en) * | 2023-11-22 | 2023-12-22 | 北京紫光芯能科技有限公司 | Cyclic redundancy check device and cyclic redundancy check method |
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| CN117271201B (en) * | 2023-11-22 | 2024-03-19 | 北京紫光芯能科技有限公司 | Cyclic redundancy check device and cyclic redundancy check method |
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