CN111901257B

CN111901257B - Switch, message forwarding method and electronic equipment

Info

Publication number: CN111901257B
Application number: CN202010798409.8A
Authority: CN
Inventors: 苏勇; 万伟; 李斌; 袁伟
Original assignee: Zhongke Sugon Information Industry Chengdu Co ltd; Dawning Information Industry Beijing Co Ltd
Current assignee: Zhongke Shuguang information industry Chengdu Co., Ltd; Dawning Information Industry Beijing Co Ltd
Priority date: 2020-08-10
Filing date: 2020-08-10
Publication date: 2022-02-25
Anticipated expiration: 2040-08-10
Also published as: CN111901257A

Abstract

The application relates to a switch, a message forwarding method and electronic equipment, and belongs to the technical field of network communication. The switch includes: a first switch chip; the system comprises a fully-connected network topology comprising a plurality of second switching chips, wherein each second switching chip in the fully-connected network topology is connected with at least one first switching chip. In the embodiment of the application, on the basis of the fully-connected network topology, at least one first switching chip is further connected to each second switching chip in the fully-connected network topology to form a fully-connected network enhanced topology framework, the computing requirement of the computing-intensive application is guaranteed by the fully-connected network main body, the requirement on the I/O-intensive operation is met by the extended Plus framework, and the switch can be used for easily coping with a large amount of frequent I/O operations while the requirement on a large amount of computing by the high-performance application is guaranteed.

Description

Switch, message forwarding method and electronic equipment

Technical Field

The application belongs to the technical field of network communication, and particularly relates to a switch, a message forwarding method and electronic equipment.

Background

Typical high performance applications are dominated by computationally intensive applications such as ocean current simulation, scientific computing, and the like. The compute-intensive task is characterized in that a large amount of computation is required, a large amount of Central Processing Unit (CPU) resources are consumed, such as computing the circumference ratio, performing high-definition decoding on a video and the like, and the computing power of the CPU is relied on. However, with the rapid development of new technologies such as big data and artificial intelligence, a large number of io (input output) intensive applications, such as stock exchange, real-time airline reservations, search engines, online games, relational databases, World Wide Web (Web) applications, etc., have been increasingly demanded for high performance computing. The denser the transaction, the higher the demand for Input Output Per Second (IOPS), and such I/O-intensive applications are characterized by low CPU consumption and waiting for IO operations to complete most of the time (because the IO response speed is much lower than that of CPU and memory).

With the advent of the mobile internet, mobile terminals, and data sensors, data is rapidly increasing beyond imagination. For storage systems, there are a large number of I/O read and write operations, which do not have high requirements for data bandwidth, but handle a large amount of traffic, which presents a new challenge to the classical high performance interconnect network topology. At present, no equipment which gives consideration to calculation-intensive application and I/O-intensive application exists internationally or domestically, so that the requirement of high-performance application on a large amount of calculation is ensured, and a large amount of frequent I/O operation can be coped with at ease.

Disclosure of Invention

In view of this, an object of the present application is to provide a switch, a message forwarding method and an electronic device, so as to solve the problem that the existing computation-intensive application device cannot meet the requirement of a large number of frequent I/O operations.

The embodiment of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a switch, including: a first switch chip; the system comprises a fully-connected network topology comprising a plurality of second switching chips, wherein each second switching chip in the fully-connected network topology is connected with at least one first switching chip. In the embodiment of the application, on the basis of the fully-connected network topology, at least one first switching chip is further connected to each second switching chip in the fully-connected network topology to form a fully-connected network enhanced topology framework, the computing requirements of the compute-intensive applications are guaranteed by the fully-connected network main body, and the connected first switching chips meet the requirements of the I/O-intensive operations, so that the switch can be used for tolerably dealing with a large amount of frequent I/O operations while guaranteeing the requirements of the high-performance applications on a large amount of computations.

With reference to a possible implementation manner of the embodiment of the first aspect, each of the second switch chips has 2M ports, M ports of each of the second switch chips are used for connecting a computing node, and the remaining M ports of each of the second switch chips are used for connecting the first switch chip and the remaining second switch chips in the fully-connected network topology, where M is a positive integer. In the embodiment of the application, M ports of the second switch chip in the fully-connected network topology are used for connecting the computing nodes, and the remaining M ports are used for connecting the first switch chip and the remaining second switch chips in the fully-connected network topology, so that the balance between the computation-intensive application and the I/O-intensive application is realized.

With reference to a possible implementation manner of the embodiment of the first aspect, the switch further includes: a back plate; the plurality of page plates are arranged on the back plate, so that the connection among the page plates is realized through the back plate. In the embodiment of the application, the first exchange chip and the second exchange chip are arranged on the page plate and connected through the backboard to realize the connection among the multiple page plates, so that the wiring mode of each line is standardized, and the complexity of a connection line is simplified.

In a second aspect, an embodiment of the present application further provides a message forwarding method, which is applied to a target switch chip in a switch, where the switch includes: a first switch chip and a fully-connected network topology including a plurality of second switch chips, each second switch chip in the fully-connected network topology having at least one first switch chip connected thereto, the target switch chip being the first switch chip or the second switch chip, the method including: when a data message is received, acquiring a target logic identifier carried in the data message and acquiring the current code of the target logic identifier; acquiring a target code corresponding to the target logic identifier according to the corresponding relation between the preset logic identifier and the coding rule; and determining a forwarding port according to the target code and the current code, and forwarding the data message through the forwarding port. In the embodiment of the application, when the current target exchange chip receives a data message, the target logic identifier carried in the data message and the current code of the current target exchange chip are obtained, the target code corresponding to the target logic identifier is obtained according to the corresponding relation between the preset logic identifier and the coding rule, then the position relation of the destination in the topology can be quickly determined according to the target code and the current code, the forwarding port is further determined, the data message is forwarded through the forwarding port, and therefore the purpose of no deadlock of the route is achieved.

In combination with one possible implementation manner of the embodiment of the second aspect, the target code is (Xd, Yd, Pd, Nd), and the current code is (Xs, Ys, Ps, Ns), where Xd and Yd represent positions of the destination switch chip in the entire switch network topology, and Xs, Ys represent positions of the target switch chip in the entire switch network topology; pd represents a chip type of the destination switch chip, Ps represents a chip type of the target switch chip, Nd represents a port number of the destination switch chip, and Ns represents a port number of the target switch chip; determining a forwarding port according to the target code and the current code, including: determining whether Xd is equal to the Xs and Yd is equal to the Ys; when the Xd is equal to the Xs and the Yd is equal to the Ys, judging whether the Pd is equal to the Ps; and when the Pd is equal to the Ps, the port corresponding to the Nd is the forwarding port. In the embodiment of the application, during encoding, positions of the switching chips in the entire switch network topology, types of the switches, and port numbers are taken into consideration, so that subsequently, when a forwarding port is determined, the approximate position of a target can be determined by judging whether Xd is equal to Xs and whether Yd is equal to Ys, and if Xd is equal to Xs and Yd is equal to Ys, then further judging whether Pd is equal to Ps, so that the forwarding port corresponding to the target can be determined quickly.

With reference to a possible implementation manner of the embodiment of the second aspect, the fully-connected network topology includes 4 second switch chips, determines a forwarding port according to the target code and the current code, and further includes: and when the Xd is not equal to the Xs and the Yd is not equal to the Ys, the port where the XY diagonal dimension link is located is the forwarding port. In the embodiment of the present application, when the fully-connected network topology includes 4 second switching chips, when Xd is not equal to Xs and Yd is not equal to Ys, it may be quickly determined that the port where the XY diagonal dimension link is located is a forwarding port.

With reference to a possible implementation manner of the embodiment of the second aspect, the fully-connected network topology includes 4 second switch chips, determines a forwarding port according to the target code and the current code, and further includes: and when the Xd is equal to the Xs and the Yd is not equal to the Ys, the port where the Y-dimension link is located is the forwarding port. In the embodiment of the present application, when the fully-connected network topology includes 4 second switching chips, when Xd is equal to Xs and Yd is not equal to Ys, it may be quickly determined that the port where the Y-dimensional link is located is a forwarding port.

With reference to a possible implementation manner of the embodiment of the second aspect, the fully-connected network topology includes 4 second switch chips, determines a forwarding port according to the target code and the current code, and further includes: and when the Xd is not equal to the Xs and the Yd is equal to the Ys, the port where the X-dimension link is located is the forwarding port. In the embodiment of the present application, when the fully-connected network topology includes 4 second switching chips, when Xd is not equal to Xs and Yd is equal to Ys, it may be quickly determined that the port where the X-dimension link is located is a forwarding port.

With reference to a possible implementation manner of the embodiment of the second aspect, determining a forwarding port according to the target code and the current code further includes: and when the Pd is not equal to the Ps, a port where a P-dimension link is located is the forwarding port, wherein the P-dimension link represents a link for connecting the second switching chip and the first switching chip. In this embodiment of the application, if Xd is equal to Xs and Yd is equal to Ys, if Pd is not equal to Ps, it may be determined that a port where the P-dimensional link is located is a forwarding port.

In a third aspect, an embodiment of the present application further provides an electronic device, including: a memory and a processor, the processor coupled to the memory; the memory is used for storing programs; the processor is configured to invoke a program stored in the memory to perform the method according to the first aspect embodiment and/or any possible implementation manner of the first aspect embodiment.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The foregoing and other objects, features and advantages of the application will be apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intended to be to scale as practical, emphasis instead being placed upon illustrating the subject matter of the present application.

Fig. 1 shows a network topology diagram of a switch provided in an embodiment of the present application.

Fig. 2 shows a network topology diagram of another switch provided in an embodiment of the present application.

Fig. 3 shows a schematic diagram of a port connection relationship of a switch chip inside a switch according to an embodiment of the present application.

Fig. 4 shows a front panel port layout schematic of the switch shown in fig. 1.

Figure 5 shows a front panel port layout schematic of the switch shown in figure 2.

Fig. 6 shows a flowchart of a message forwarding method according to an embodiment of the present application.

Fig. 7 is a schematic diagram illustrating a principle of a message forwarding method according to an embodiment of the present application.

Fig. 8 shows a schematic structural diagram of a concurrent link provided in an embodiment of the present application.

Fig. 9 shows a schematic structural diagram of an electronic device provided in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely in the description herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Further, the term "and/or" in the present application is only one kind of association relationship describing the associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone.

In view of the fact that no device capable of simultaneously considering both calculation-intensive applications and I/O-intensive applications exists at present, the requirement of high-performance applications on a large number of calculations is guaranteed, and meanwhile a large number of frequent I/O operations can be coped with leisurely. Based on this, the embodiment of the present application provides a switch formed based on a switch chip, so that the switch can simultaneously consider compute intensive application and I/O intensive application, implement a super-fusion architecture, and can provide high-performance computing power and meet the requirements of intensive I/O operations. As shown in fig. 1 and fig. 2, the switch provided by the embodiment of the present application and configured based on the switch chip includes: the system comprises a first exchange chip and a fully-connected network (Full Mesh) topology comprising a plurality of second exchange chips, wherein at least one first exchange chip (Plus exchange chip) is connected to each second exchange chip (Full Mesh exchange chip) in the fully-connected network topology. On the basis of the Full-connection network topology, a Full-connection network enhancement type (Full Mesh Plus) topology framework is formed by further connecting a first exchange chip, a Full Mesh network main body ensures the calculation requirement of calculation intensive application, and the extended Plus framework meets the requirement of I/O intensive operation. The fully-connected network topology refers to that each second switching chip located in the network topology is connected with each of the other second switching chips, so as to form a fully-connected network topology. Fig. 1 shows a situation in which one first switch chip is connected to each second switch chip in the fully-connected network topology, and fig. 2 shows a situation in which three first switch chips are connected to each second switch chip in the fully-connected network topology.

In one embodiment, the fully-connected network topology includes 4 second switch chips, each second switch chip has 2M (M is a positive integer) ports, and the M ports of each second switch chip are used for connecting to a compute node to ensure the compute requirements of the compute-intensive application; and the remaining M ports of each second switching chip are used for being connected with the remaining 3 second switching chips and at least one first switching chip, and the requirement on I/O intensive operation is met by expanding the I/O ports. In the embodiment of the present application, in view of the local communication characteristics naturally associated with many high-performance applications of the two-dimensional Mesh topology, there are direct links in both X/Y dimensions, especially in the 2X2 Mesh, and a diagonal network diameter of 2 hops (one hop is used for transmitting data between two second switching chips for one time) is reachable (for ease of understanding, taking the fully-connected network topology in fig. 1 as an example, for the two-dimensional Mesh topology, since there is no direct link from SW0 to diagonal SW2, the network diameter from SW0 to diagonal SW2 is 2 hops (the path may be SW0 to SW1 and then from SW1 to SW2, or may also be SW0 to SW3 and then from SW3 to SW2)), and a Full Mesh network topology can be constructed by adding a direct link at a diagonal according to the structural characteristics, and the network diameter is reduced to 1 hop, so that the communication delay can be effectively reduced and the communication performance can be improved. By connecting a first switch chip with a plurality of I/O ports to a designated port (Super IO port) of a second switch chip in the Full Mesh network topology, the Plus network can be connected to and communicate through the Full Mesh network. The Super IO port does not occupy ports of all dimensions of the interconnected Full Mesh, and the network can recognize the Plus topology according to the port type and cannot be confused with the Full Mesh network. The first switching chip and the second switching chip in the Full Mesh network have the same structure and function, and are only different in topological position, and are not responsible for data forwarding of the Full Mesh network topology and only responsible for processing I/O data. And the first switching chip is ensured to be only responsible for the first hop sending and the last hop receiving of the data through a routing algorithm, and does not participate in the intermediate Full Mesh network topology data forwarding. It should be noted that the number of the second switch chips in the fully-connected network topology is not limited to 4, and may be other values (e.g., 5, 6 … …), so that the fully-connected network topology in the above example cannot be understood as a limitation to the present application.

Taking the 48-port OPA (Omni-Path Architecture) switch chip (including the first switch chip and the second switch chip) provided by intel as an example, for fig. 1, each second switch chip in the fully-connected network topology has 24 ports for connecting to the computing nodes and the remaining 24 ports for connecting to the remaining 3 second switch chips and 1 first switch chip. In the Full Mesh network, the X dimension, the Y dimension, and the XY diagonal dimension of each second switch chip are respectively connected with 6 links to be respectively connected to the other 3 second switch chips, and the remaining 6 links (P dimension links) are connected to one first switch chip, thereby providing a high-speed I/O channel. Each first switch chip may be used to connect 42I/O nodes, with the remaining 6 ports being used to connect to corresponding second switch chips. The switch shown in fig. 1 can connect 96 computing nodes (each second switching chip can connect 24 computing nodes, and 4 second switching chips can connect 96 computing nodes) and 168I/O nodes (1 first switching chip can connect 42I/O nodes, and 4 first switching chips can connect 168I/O nodes), and can completely satisfy the interconnection of a small and medium-sized cluster. Since the I/O operations of I/O-intensive applications are mainly small data operations with large amounts of high concurrency, the bandwidth requirement is not high and 6 Super IO channels are sufficient to meet the bandwidth requirement. If the bandwidth requirement of a certain application is large, a plurality of Super IO ports can be defined to be used as I/O links to expand the I/O bandwidth, flexible configuration can be achieved, and different requirements can be met. In addition, the I/O connection capability can be further expanded by increasing the number of connected first switching chips, for example, each second switching chip is connected with 3 first switching chips, as shown in fig. 2, each second switching chip is connected with 24 computing nodes, the remaining 24 ports can be allocated with 4 ports in each direction to provide high-speed interconnection channels, 12 ports are required for connecting the remaining 3 second switching chips, and the remaining 12 ports can be connected with 3 first switching chips. Each first switch chip may be connected to 44I/O nodes and the remaining 4 ports may be connected to the second switch chip, such that the switch may be connected to 96 compute nodes and 528I/O nodes (1 first switch chip may be connected to 42I/O nodes and 12 first switch chips may be connected to 528I/O nodes).

It should be noted that the port connection situation of the second switch chip in the fully-connected network topology is not limited to the above-mentioned exemplary situation, for example, M ports are used for connecting the computing nodes, the rest M ports are used for connecting the rest second switching chips and the first switching chip, which may correspondingly increase or decrease the number of ports used to connect computing nodes, such as 12 ports for connecting 12 computing nodes, the 36 ports are allocated to 4 high-speed links (each high-speed link includes 9 ports) for connecting the remaining 3 second switching chips and 1 first switching chip, or, the 36 ports are allocated to 6 high-speed links (each high-speed link includes 6 ports) for connecting the remaining 3 second switching chips and 3 first switching chips, and therefore the above exemplary port connection situation cannot be understood as a limitation of the present application.

According to the structural characteristics of Full Mesh Plus network topology, an XY plane diagonal connecting line is defined as XY diagonal dimension on the basis of the dimension of standard X, Y, the dimension where a link connecting a second switching chip and a first switching chip is located is P dimension (Plus dimension), and a corresponding link is a P dimension link. The port connection relationships for the respective dimensions are shown in table 1. The ports 1 to 24 of each second switching chip are connected with the computing nodes, the ports 25 to 30 correspond to the X dimension, the ports 31 to 36 correspond to the Y dimension, the ports 37 to 42 correspond to the XY diagonal dimension, and the ports 43 to 48 are connected with the first switching chip and correspond to the P dimension. The ports 1 to 42 of the first switching chip are connected with the I/O nodes.

TABLE 1

It should be noted that, the port correspondence of the above example is adjustable, for example, 25 to 48 ports are connected to the computing node, the ports 1 to 6 correspond to the X dimension, the ports 7 to 12 correspond to the Y dimension, the ports 13 to 18 correspond to the XY diagonal dimension, and the ports 19 to 24 are connected to the first switch chip, so the above example cannot be understood as a limitation to the present application. In addition, the port connection relationship between the local port number and the opposite port number is also adjustable, for example, in an embodiment, the port connection relationship is as shown in table 2, so the examples in table 1 and table 2 cannot be understood as a limitation to the present application.

TABLE 2

In order to connect adjacent switch chips, as shown in fig. 3, the switch further includes: the device comprises a back plate and a plurality of page plates (main plates), wherein each page plate is provided with at least one first exchange chip and/or one second exchange chip, and the plurality of page plates are arranged on the back plate, so that the connection between the page plates is realized through the back plate. Two switch chips (2 first switch chips, 2 second switch chips, or 1 first switch chip and 1 second switch chip) are deployed on each page board, and each port in the X dimension can be connected to the page board; every two page plates form a Y dimension and are connected through a back plate; the connecting line from the second exchange chip to the first exchange chip is connected through the back plate. The thicker lines in the figure represent multiple concurrent links, which may be adjusted according to different configurations.

The front panel port structure of the large-port switch shown in fig. 1 is shown in fig. 4. The heavy boxes in the figure represent ports connecting compute nodes and the light boxes represent ports connecting I/O nodes. Each interface board (referring to an interface board formed by integrating 24 ports of a switch into one panel) has 24 ports, 4 second switch chips correspond to 4 interface boards and are connected with 96 computing nodes (one second switch chip can be connected with 24 computing nodes, and one interface board has 24 ports, so that 4 second switch chips correspond to 4 interface boards), 4 first switch chips correspond to 7 interface boards and are connected with 168I/O nodes (one first switch chip can be connected with 42I/O nodes, and one interface board has 24 ports, so that 4 first switch chips correspond to 7 interface boards), and 11 interface boards in total can be connected with 260 nodes. Accordingly, the large port switch front panel port architecture shown in FIG. 2 is shown in FIG. 5. The heavy boxes in the figure represent ports connecting compute nodes and the light boxes represent ports connecting I/O nodes. Each interface board has 24 ports, 4 second switching chips correspond to 4 interface boards connected with 96 computing nodes, 12 first switching chips correspond to 22 interface board connected with 528I/O nodes, and a total of 26 interface boards can be interconnected with 624 nodes.

The embodiment of the application also provides a message forwarding method applied to the switch, so as to ensure smooth communication among all the switch chips in the switch and avoid deadlock. The switch is formed based on a switch chip and has Full Mesh Plus network topology, so that a non-blocking network can be realized based on a shortest path routing algorithm. And coding coordinate information of each dimensionality of the switching chip and the node port according to the position relation of the switching chip and each computing node in the network topology, wherein the switch is coded into X _ Y _ P _ N. Wherein X, Y is a coordinate value of a dimension of a swap chip (including a first swap chip and a second swap chip), and P indicates whether the swap chip is a first swap chip (i.e., a Plus swap chip), if P is 0, it is defined as a second swap chip, if P is 1, it is defined as a first swap chip, and of course, the other way around is also possible, i.e., if P is 1, it is defined as a second swap chip, and if P is 0, it is defined as a first swap chip. The first switching chip has the same dimensional coordinates as the second switching chip to which it is directly connected, with the difference being the coding of P. The X, Y, P bits of the node code are encoded with the same code as the switch chip to which it is connected (i.e., X _ Y _ P _ N). The last bit N is the port number corresponding to the switch chip, if the switch chip is connected to the port, N is defined to be 0, if the node is connected to the port, the value indicates the node connected to the port, and if N is 10, the node connected to the port 10 is indicated. The code of each switching chip or node is uniquely determined, a mapping relation with a Logical IDentifier (LID) can be established according to the code, and the switching chip can acquire the equipment code according to the target LID after receiving the data to perform routing judgment.

For a standard Full Mesh network, a route is calculated based on a shortest path first principle, the position relation of a destination in a topology is determined according to codes corresponding to LIDs of a destination exchange chip and a source exchange chip, and a route path can be determined by calculating offset of each dimension of the position where the destination is located. For example, the location of the destination in the topology can be located according to X, Y coordinates in the code (X _ Y _ P _ N), and whether the destination switch chip is the second switch chip or the first switch chip can be determined according to P, and whether the port is connected to the switch chip or the node can be determined according to N, so that the routing path can be accurately determined. For Full Mesh network topology, the method can be decomposed into orthogonal X/Y dimension and XY diagonal dimension, and the routing distance (the sum of the offsets in each dimension) between the source switching chip and the destination switching chip can be easily calculated by using a dimension order routing algorithm. If the dimension is traversed according to the descending order of the dimension length, the offset of each route is reduced by 1, the offset of the next dimension is calculated after the offset of the current dimension is reduced to 0, and finally the offsets of the dimensions are summed, namely the routing distance between the source switching chip and the destination switching chip is obtained. The Full Mesh Plus network topology is obtained by extending the Full Mesh Plus network topology, output transmission only aiming at an I/O node is specified to be forwarded to the first switching chip, the first hop and the last hop of I/O data are forwarded between the second switching chip (the Full Mesh switching chip) and the first switching chip, other situations are all transmitted in the Full Mesh network, and the dimension order routing rule is uniformly followed, so that the dimension order routing algorithm is still suitable for the Full Mesh Plus network. When forwarding a data message, forwarding is directly performed based on the shortest path principle, and the message forwarding method provided in the embodiment of the present application will be described below with reference to fig. 6.

Step S101: when a data message is received, a target logic identifier carried in the data message is obtained, and the current code of the target logic identifier is obtained.

When the target switching chip receives the data message, a target logic identifier (target LID) carried in the data message is acquired, and the current code of the target switching chip is acquired.

Step S102: and acquiring a target code corresponding to the target logic identifier according to the corresponding relation between the preset logic identifier and the coding rule.

And obtaining the target code corresponding to the target LID according to the corresponding relation between the preset LID and the coding rule.

Step S103: and determining a forwarding port according to the target code and the current code, and forwarding the data message through the forwarding port.

And finally, according to the target code and the current code, the position relation of the destination exchange chip in the topology can be determined, a forwarding port is further determined, and the data message is forwarded out through the determined forwarding port.

Wherein, the target code is (Xd, Yd, Pd, Nd), and the current code is (Xs, Ys, Ps, Ns), where Xd and Yd represent the positions of the destination switch chips in the entire switch network topology, and Xs and Ys represent the positions of the target switch chips in the entire switch network topology; pd denotes a chip type of the destination swap chip (if Pd is 0, it denotes a second swap chip, and Pd is 1, it denotes a first swap chip), Ps denotes a chip type of the target swap chip, Nd denotes a port number of the destination swap chip, and Ns denotes a port number of the target swap chip.

Based on a deadlock-free routing algorithm, by detecting coordinate information of X/Y dimensionality, the dimensionality of a destination exchange chip in a target exchange chip can be judged, namely whether Xd is equal to Xs or not and whether Yd is equal to Ys or not are judged; if the X/Y dimensional coordinates of the destination switching chip are different from the X/Y dimensional coordinates of the target switching chip (namely, Xd is not equal to Xs and Yd is not equal to Ys), the destination switching chip is positioned in the XY diagonal dimension of the target switching chip, and the data message is forwarded from the port where the XY diagonal dimension link is positioned; if the dimensions X are the same and the dimensions Y are different (that is, Xd is equal to Xs and Yd is not equal to Ys), the destination switch chip is located in the dimension Y of the target switch chip, and the data message is forwarded from the port where the Y-dimension link is located; if the dimensions Y are the same and the dimensions X are different (that is, Xd is not equal to Xs and Yd is equal to Ys), the destination switching chip is located in the dimension X of the target switching chip, and the data message is forwarded from the port where the X-dimension link is located; if the dimensions X/Y are the same (i.e. Xd equals Xs and Yd equals Ys), it indicates that the destination swap chip is located in the target swap chip or in the first swap chip connected to it, and it can be determined by further determining whether the target Pd and the current Ps are equal to each other: if Ps is Pd, the destination switching chip is positioned in the target switching chip, and the data message is forwarded to the target node from the corresponding port of Nd, otherwise, the data message is forwarded to the first target switching chip from the port (Super IO port connected with Pd) where the P-dimension link is positioned. After receiving the data packet, the first switching chip determines that all the dimension information is the same as itself, which indicates that the node connected to the target switching chip is a node that can be reached by directly outputting the data packet from the port Nd, and a specific schematic diagram is shown in fig. 7. Because the internal route of the Full Mesh can be reached by one hop, the route cannot be deadlocked, the route to the Plus link reaches the target node only by the last hop, and does not participate in the route of the middle Full Mesh network, so the deadlock cannot be caused.

Because multiple concurrent high-speed communication links exist among each dimension (X dimension, Y dimension, XY diagonal dimension, or P dimension (i.e., Plus dimension in table 1 or table 2)), in order to achieve load balancing and effectively utilize link resources, a transmission link can be selected in a self-adaptive manner according to the occupation condition of Buffer cache resources of the link, so that the link utilization rate can be effectively improved, and the throughput rate can be increased. The exchange chip can exchange the utilization rate of the input cache of each link, and the exchange chip selects the port with the most idle link for output according to the occupation condition of the input cache resource of the downstream link under the condition of judging the output routing direction based on the shortest path routing algorithm, thereby achieving the purposes of dynamically allocating link resources and realizing load balance. As shown in FIG. 8, the current data transfer from SW0 to SW1 has 4 LINKs available for selection, where the input buffer of LINK4 is the most free, and SW0 will select to transfer data at LINK 4. And if the Buffer resource spaces are the same, selecting by adopting a random algorithm. The crossbar Bar is a crossbar switch matrix or a crossbar switch matrix and is a core component inside the switch chip.

In the message forwarding method applied to the switch provided in the embodiment of the present application, the implementation principle and the generated technical effect of the switch are the same as those of the foregoing device embodiment, and for brief description, for parts that are not mentioned in the method embodiment, reference may be made to corresponding contents in the foregoing device embodiment.

As shown in fig. 9, fig. 9 is a block diagram illustrating a structure of an electronic device 200 according to an embodiment of the present disclosure. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.

The elements of the transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, the components may be electrically coupled to each other via one or more communication buses 230 or signal lines. The transceiver 210 is used for transceiving configuration messages. The memory 220 is used for storing a computer program, such as a software functional module stored with an Operating System (OS) for executing the message forwarding method according to the embodiment of the present application, where the computer program or the software functional module includes at least one software functional module that can be stored in the memory 220 in a form of software or firmware (firmware) or is solidified in the OS of the electronic device 200. The processor 240 is configured to execute software functional modules or computer programs stored in the memory 220. For example, the processor 240 is configured to, when receiving a data packet, obtain a target logic identifier carried in the data packet, and obtain a current code of itself; the target code corresponding to the target logic identifier is obtained according to the corresponding relation between the preset logic identifier and the coding rule; and the data message forwarding device is also used for determining a forwarding port according to the target code and the current code and forwarding the data message through the forwarding port.

The Memory 220 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like.

The processor 240 may be an integrated circuit chip having signal processing capabilities. The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor 240 may be any conventional processor or the like.

The electronic device 200 includes, but is not limited to, the above-mentioned switch chip.

It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

In the embodiments provided in the present application, it should be understood that the disclosed method can be implemented in other ways. The embodiments described above are merely illustrative, and the flowcharts and block diagrams in the figures, for example, illustrate the architecture, functionality, and operation of possible implementations of methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a notebook computer, a server, or an electronic device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A switch, comprising:

a first switch chip;

a plurality of second switch chips, each of which is connected to each of the other second switch chips to form a fully-connected network topology, wherein each of the second switch chips in the fully-connected network topology is connected to at least one of the first switch chips, M ports of each of the second switch chips are used for connecting to a computing node, the first switch chip has a plurality of I/O ports and is connected to a designated port of the second switch chip, and M is a positive integer;

the target switch chip is the first switch chip or the second switch chip, and the target switch chip is configured to:

when a data message is received, acquiring a target logic identifier carried in the data message and acquiring the current code of the target logic identifier; acquiring a target code corresponding to the target logic identifier according to the corresponding relation between the preset logic identifier and the coding rule; determining a forwarding port according to the target code and the current code, and forwarding the data message through the forwarding port; wherein the target code is (Xd, Yd, Pd, Nd), and the current code is (Xs, Ys, Ps, Ns), where Xd and Yd represent the positions of the destination switch chips in the network topology of the switch, and Xs and Ys represent the positions of the target switch chips in the entire switch network topology; pd denotes a chip type of the destination switch chip, Ps denotes a chip type of the target switch chip, Nd denotes a port number of the destination switch chip, and Ns denotes a port number of the target switch chip.

2. The switch of claim 1, wherein each of the second switching chips has 2M ports, wherein M ports of each of the second switching chips are used for connecting to a computing node, and wherein the remaining M ports of each of the second switching chips are used for connecting to the first switching chip and the remaining second switching chips in the fully-connected network topology, wherein M is a positive integer.

3. The switch according to claim 1 or 2, characterized in that it further comprises:

a back plate;

the plurality of page plates are arranged on the back plate, so that the connection among the page plates is realized through the back plate.

4. A message forwarding method is applied to a target switching chip in a switch, and the switch comprises: the system comprises a first switching chip and a plurality of second switching chips, wherein each second switching chip is connected with the other second switching chips so as to form a fully-connected network topology, each second switching chip in the fully-connected network topology is connected with at least one first switching chip, M ports of each second switching chip are used for connecting computing nodes, the first switching chip is provided with a plurality of I/O ports and is connected with a designated port of the second switching chip, and M is a positive integer; the target switch chip is the first switch chip or the second switch chip, and the method includes:

when a data message is received, acquiring a target logic identifier carried in the data message and acquiring the current code of the target logic identifier;

acquiring a target code corresponding to the target logic identifier according to the corresponding relation between the preset logic identifier and the coding rule;

determining a forwarding port according to the target code and the current code, and forwarding the data message through the forwarding port,

wherein the target code is (Xd, Yd, Pd, Nd), and the current code is (Xs, Ys, Ps, Ns), where Xd and Yd represent the positions of the destination switch chips in the network topology of the switch, and Xs and Ys represent the positions of the target switch chips in the entire switch network topology; pd denotes a chip type of the destination switch chip, Ps denotes a chip type of the target switch chip, Nd denotes a port number of the destination switch chip, and Ns denotes a port number of the target switch chip.

5. The method of claim 4, wherein determining a forwarding port based on the target code and the current code comprises:

determining whether Xd is equal to the Xs and Yd is equal to the Ys;

when the Xd is equal to the Xs and the Yd is equal to the Ys, judging whether the Pd is equal to the Ps;

and when the Pd is equal to the Ps, the port corresponding to the Nd is the forwarding port.

6. The method of claim 4, wherein the fully-connected network topology includes 4 second switch chips, and wherein determining a forwarding port according to the target code and the current code comprises:

and when the Xd is not equal to the Xs and the Yd is not equal to the Ys, the port where the XY diagonal dimension link is located is the forwarding port.

7. The method of claim 4, wherein the fully-connected network topology includes 4 second switch chips, and wherein determining a forwarding port according to the target code and the current code comprises:

and when the Xd is equal to the Xs and the Yd is not equal to the Ys, the port where the Y-dimension link is located is the forwarding port.

8. The method of claim 4, wherein the fully-connected network topology includes 4 second switch chips, and wherein determining a forwarding port according to the target code and the current code comprises:

and when the Xd is not equal to the Xs and the Yd is equal to the Ys, the port where the X-dimension link is located is the forwarding port.

9. The method of claim 4, wherein determining a forwarding port based on the target code and the current code comprises:

and when the Pd is not equal to the Ps, a port where a P-dimension link is located is the forwarding port, wherein the P-dimension link represents a link for connecting the second switching chip and the first switching chip.

10. An electronic device, comprising:

a memory and a processor, the processor coupled to the memory;

the memory is used for storing programs;

the processor to invoke a program stored in the memory to perform the method of any of claims 4-9.