CN111900999B

CN111900999B - High-performance polarization coding method and coder for satellite discontinuous communication

Info

Publication number: CN111900999B
Application number: CN202010684940.2A
Authority: CN
Inventors: 刘荣科; 刘寅德; 黄为豪
Original assignee: Beihang University
Current assignee: Beihang University
Priority date: 2020-07-16
Filing date: 2020-07-16
Publication date: 2022-11-18
Anticipated expiration: 2040-07-16
Also published as: CN111900999A

Abstract

The invention discloses a high-performance polarization coding method and a coder for satellite discontinuous communication, wherein the method comprises the following steps: a first part: s1, dividing a polarization code freezing bit and an information bit into a plurality of code blocks, performing polarization coding on each code block, storing the information bit in a ROM1, and storing the polarization coding in a ROM 2; s2, addressing the ROM2 by using the position information of the information bits stored in the ROM 1; s3, performing bit exclusive OR on a certain line output by the ROM1 and a data AND result read from the FIFO at the moment and a data result stored in the register REG, and storing the obtained numerical value back to the register REG; and S4, writing the coding result in the step S3 into the RAM, and starting the polarization coding of the next group of code length after the register REG is cleared. A second part: the first partially encoded code blocks are exclusive-ORed according to a butterfly. The encoder of the invention consumes extremely low FPGA hardware resources; the encoder has extremely low coding time delay; the encoder throughput is high.

Description

High-performance polarization coding method and coder for satellite discontinuous communication

Technical Field

The invention relates to a high-performance polarization code encoding method and an encoder capable of realizing low resource overhead, in particular to a high-performance polarization encoding method and an encoder for satellite discontinuous communication, and belongs to the technical field of communication.

Background

In satellite communication, discontinuous communication is a very important communication mode. For the measurement and control access channel, it is very important to ensure the reliability and effectiveness of transmission in the discontinuous communication process. Therefore, channel coding is certainly adopted in satellite communication to ensure highly reliable communication. For practical applications, in the discontinuous communication process, information is generally transmitted in hundreds of bits, and there is no retransmission mechanism, so that a very high requirement is imposed on the reliability of transmission, which also puts a higher requirement on the performance of channel coding. Because, according to shannon's coding theorem, generally, the longer the code length is, the better the performance of the code is. However, in the case of a short code of several hundreds of bits, a high-performance coding scheme is required to ensure good transmission reliability.

The polarization code was 2009 by E.

The proposed new channel coding is the first constructive channel coding scheme capable of achieving channel capacity. The polarization code is realized based on channel polarization, wherein the channel polarization is realized by regarding a group of independent time slots of a binary input memoryless channel as a group of mutually independent channels, and introducing correlation through channel segmentation and channel combination operation so as to obtain a group of new binary input polarization channels with mutual dependency relationship. When the number of channels (time slots) participating in the polarization of the channel is large enough, the channel capacity of the obtained polarized channel will be polarized, i.e. the capacity of a part of the channels will tend to 1, and the remaining channels will tend to 0. Besides the reachable channel capacity, compared with Turbo codes and LDPC codes, the polarization codes also have the advantages of low coding and decoding complexity, flexible code rate adjustment and the like.

In satellite communication, because on-satellite resources are limited, an encoder with low resource overhead needs to be researched, and meanwhile, the constructed encoding scheme can be ensured to realize high performance, so that the requirement on transmission reliability in satellite communication is met. Therefore, the present invention proposes a high performance polar code encoder that achieves low resource overhead.

The polarization code is different from LDPC code, system RS code, turbo code, etc. the redundant bit generated after the information bit is coded is filled directly behind the information bit and is sent out, the coding of the polarization code firstly needs to determine the position set of the information bit, and the Gaussian approximation method is usually adopted. We can represent this set of information bit positions by the set A, A ^c Representing a set of frozen bit positions. Then for one (N, K, A) ^c ) After the set a is determined, the coding process of the polar code can be expressed as a process of multiplying the information bits by a generator matrix. If it is used

Representing the code word to be encoded, G _N A generator matrix representing the polarization code, the result of the encoding can then be represented as

And the coding matrix of the polarization code is

By a matrix

Of the n-th order Kronecker product,

representing the kronecker product operation performed on n F matrices, B _N Is a bit flipping matrix, performs a linear transformation process, so

And G _N The same rows are provided, except that the order of the rows is different. In a specific implementation, the encoding method is divided into two types, one is encoding layer by layer according to a butterfly diagram, and the other is encoding by using a generator matrix G _N And (6) coding is carried out. The former has small resource occupation but large time delay; the latter reduces the coding delay but occupies a large amount of resources. The invention combines the two methods, designs a method for coding the first half part by using the generated matrix and the second half part by using the butterfly diagram, and realizes an efficient polar code coder by using less FPGA resource overhead.

Disclosure of Invention

The invention aims to provide a high-performance polarization coding method and a coder for satellite discontinuous communication, so that on-board resources are limited and a coder with low resource overhead is needed under the condition of satellite discontinuous communication, and meanwhile, the high performance of a constructed coding scheme is ensured, so that the requirement on transmission reliability in satellite communication is met.

The invention provides a high-performance polarization coding method for satellite discontinuous communication, which comprises the following specific processes:

the polarization coding method comprises two parts:

a first part: and encoding the sub-polarization codes.

S1, dividing a polarization code freezing bit and an information bit into a plurality of code blocks, performing polarization coding on each code block, and storing the information bit in a ROM1 and the polarization coding in a ROM 2;

s2, addressing the ROM2 by using the position information of the information bits stored in the ROM 1;

s3, performing bit exclusive OR on a certain line output by the ROM1 and a data AND result read from the FIFO at the moment and a data result stored in the register REG, and storing the obtained numerical value back to the register REG;

and S4, writing the coding result in the step S3 into the RAM, and starting the polarization coding of the next group of code lengths after clearing the register REG.

A second part: the first partially encoded code blocks are exclusive-ORed according to a butterfly.

And taking each code block of the first part as a node of the polarization code coding butterfly diagram, reading the code block result stored in the RAM from the RAM according to the butterfly diagram, performing XOR operation, and storing the code block result back to the RAM to finally obtain a polarization code coding result.

Preferably, the sub-polar code is encoded, wherein the most significant bit of the first ROM is used to control whether to read from the FIFO, the encoder implementation connects it to the FIFO read enable, the sixth bit controls whether to write the current encoding result into the RAM, when it is high, the first portion of the encoding result currently stored in the register is written into the RAM, and the next set of 32-code-length polar encoding is started; the sixth bit output by the first ROM is used for addressing the second ROM and controlling which row of the generator matrix is loaded currently; wherein the second ROM is 32-bit wide, 32-depth ROM storing a 32x32 generator matrix of 32-code-length polarization codes by rows.

Preferably, the RAM in the second part adopts True-Dual-Port RAM which has two ports capable of performing read-write operation; while the first part is still accumulating, one of the ports reads the result of the previous first part that has completed 32-code long polarization encoding from the RAM, stores it in the register REG, and at the same clock, the other port of the RAM reads the value of the previous address, bitwise xors it with the value in the register, and stores the result in the address of the previous clock in the next clock.

Preferably, the second part and the first part are run in parallel, that is, the second part has already started to perform the butterfly diagram operation on the encoding result which has been previously stored in the RAM, without waiting for the first part to completely encode the 32 groups of 32-code long polarization codes.

Preferably, the second part and the first part run in parallel, which causes a conflict between the operation of writing the coding result of the first part into the RAM and the RAM operation of the second part during the butterfly operation, so that the first part transmits an interrupt signal to the second part in addition to transmitting the coding result to the second part, and stops the butterfly operation performed by the second part at the moment, thereby avoiding the conflict.

The invention provides a high-performance polarization code encoder for satellite discontinuous communication, which mainly comprises: the device comprises a CRC coding module, a FIFO, a first-stage polarization code coding module and a second-stage polarization code coding module; the first-stage polarization code encoding module further comprises a ROM1, a ROM2, an AND module, an XOR module, a register REG and a MUX; the second-stage polarization code encoding module comprises a RAM, an exclusive OR module and a register REG;

the CRC encoding module is used to add CRC check to the information bits to support CA-SCL decoding, and this module is implemented by using a division circuit, as shown in fig. 3;

the FIFO is used for buffering the information bits after the CRC is added, and is compatible with a large number of burst information bit inputs.

Wherein, the first-stage polarization code coding module comprises:

ROM1 stores polarization code corresponding to each information bit

The number of rows of the matrix is used to address the ROM 2.

ROM2 stores code generation matrix of M code long polarization code

And outputting a certain row corresponding to the generating matrix according to the row number output by the ROM 1.

The AND module bitwise AND-operates the ROM2 output and the FIFO output.

The exclusive-or module performs a bitwise exclusive-or operation on the result of the and module and the result in the REG.

The REG is an M-bit register and is used for storing the operation result of the XOR module.

The MUX is a 1-out-of-2 selector that clears REG each time before the next code block polar code encoding is performed.

Wherein, the second-stage polarization code coding module comprises:

the RAM is used for storing the code blocks coded by the first-stage polarization codes and reading the code blocks to perform second-stage polarization coding.

The REG is a register module, and the part has two REGs, wherein one part of REGs is used for temporarily storing the code block read out from the RAM, and the other part of REGs is used for completing parallel-to-serial conversion.

The XOR module is used for writing the code block read out from the RAM and the REG of the code block read out from the temporary storage RAM into the RAM in a bitwise XOR mode.

The invention relates to a high-performance polarization coding method and a coder for satellite discontinuous communication, which have the advantages that:

1. the FPGA hardware resource consumed by the encoder is extremely low, and the comprehensive result of using a Xilinx ISE14.7 comprehensive tool to Xilinx Kintex-7xc7k325t, speed grade-2L chips is shown in Table 1;

2. the encoder coding time delay realized by the polarization code coding method is extremely low, and table 1 compares the encoder provided by the invention with the traditional butterfly diagram realization scheme, so that the coding time delay is reduced by 64%;

3. the polar code encoder has high throughput rate, and realizes the information bit throughput rate of 102.5Mbps under a 100MHz clock.

Table 1 comparison of the inventive encoder and the conventional encoder

Drawings

FIG. 1 is a block diagram of interface signals for RTL implementation of a polar code encoder designed in the present invention

FIG. 2 is a block diagram of a polar encoder according to the present invention

FIG. 3 is a circuit for implementing CRC encoding part of the inventive polar code encoder

FIG. 4 is a diagram illustrating a data structure defined in the polar encoder ROM1 according to the present invention

FIG. 5 shows a ROM2 according to the present invention

(Black square-1, white square-0)

FIG. 6 is a circuit diagram illustrating the operation of the polar code encoder of the present invention

FIG. 7 is a circuit diagram of an XOR operation performed by the polar code encoder of the present invention

FIG. 8 is a diagram illustrating an example of the logic control of the second part of the polar encoder of the present invention using ROM2

FIG. 9 is a circuit diagram of a polar code encoder of the present invention for performing parallel-to-serial conversion and puncturing operations

Table 1 shows the resource consumption and coding delay data of the coder realized on FPGA

TABLE 2 function description of interface signals of polar code encoder designed by the present invention

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

Setting the code length of the polarization code as N, the number of information bits as K, and the length of the divided sub-polarization code blocks as M, wherein M can divide N completely; n-long vector for polar code frozen bit and information bit position information

To represent，

It means that the ith bit is an information bit, whereas the ith bit is a frozen bit.

The first step is as follows: and encoding the sub-polarization codes.

S1, dividing N code long polarization codes into

Group M code long polarization codes. The ROM1 stores control instructions of the encoder, the control instructions having bit widths log ₂ (M + 1) +1 (rounding up), the lowest bit of which indicates whether the current information bit is the last information bit of the M-bit sub-polarization code (1-yes, 0-no), the remaining higher bits indicate the number of rows of the M-code long sub-polarization code generation matrix corresponding to the sub-polarization code information bit, and if all zero, the sub-code has no information bit. According to the fact that i is from small to large, if the M code long subcode has no information bit, the lowest position of the control instruction is 1, and the rest positions are 0; otherwise, will cause

Mod (i, M + 1) as the higher bit of the control instruction, the lowest bit depending on whether the current information bit is the last information bit of 0 or 1 of the sub-polarization code. ROM2 stores M-code long sub-polarization code generating matrix

Each row of the matrix is stored in sequence starting from address 1 to address M, address 0 storing all zeros.

S2, log using the higher bits of ROM1 ₂ (M + 1) (rounded up) bits address ROM2, if the higher order log of ROM1 ₂ Reading an information bit from the FIFO when the (M + 1) bit is not all zero; otherwise, not reading information bits from the FIFO; the address of ROM1 is set to zero if it reaches the last address, otherwise it is increased by 1.

S3, performing AND operation on the information bits output by the FIFO and each bit output by the ROM2, performing bitwise XOR operation on the result and the value stored in the register REG, and storing the obtained result back into the register REG;

s4, if the lowest bit output by the ROM1 is 1, writing the encoding result in the step S3 into the RAM (from the address 0 to the address 0)

Store), the register REG is cleared to zero and then the polarization encoding of the next set of code length is started.

The second step: the code blocks of the first step encoding are xor-ed according to a butterfly.

For the code block of the first step into RAM, address j (from 0 to

) Are read out and stored into REG, and then sequentially will make

The code block of RAM address k is read out, and bit-wise XOR with the code block in REG is performed, and the result is stored into the k-th address of RAM again. When the code blocks of all the addresses k meeting the condition are updated, j is added with 1, and the steps are repeated until j is equal to the address k

Set j to 0.

The encoding process of the present invention is exemplified below with N =1024, m =32, k = 460. Firstly, a CRC check implementation method is introduced, the CRC length is 8, and the adopted coding generator polynomial is G (x) = x ⁸ +x ² + x +1. As shown in fig. 3, the boxes represent registers (1 bit wide),

representing an exclusive or operation. After 8 registers are reset and cleared, K3 and K1 are closed, K2 is opened, and information bits are input in series. After all information bits are input, the CRC check bits of K3 and K1 are switched off, the CRC check bits of K2 and 8 are switched on, and the CRC coding process is completed.

Then, we use the FIFO buffer CRC encoded block configured in COMMON-CLK mode, waiting for the next level of polar encoding.

In the poleA polarization coding part for instantiating two ROM modules, one for storing the position of polarization code information bit and logic control information, and the other for storing 32x32 polarization coding matrix

Fig. 4 is a diagram of a ROM1 data structure, where the most significant bit is used to control whether to read from the FIFO, which is connected to the FIFO read enable in the encoder implementation, the sixth bit controls whether to write the current encoded result into the RAM, when it is high the first portion of the encoded result currently stored in the register will be written into the RAM, and the next set of 32-code length polar encoding will begin. The sixth bit of the ROM1 output is used to address the ROM2, controlling which row of the generator matrix is currently loaded. The ROM2 is a 32-bit wide, 32-depth ROM, and stores a 32 × 32 generator matrix of 32-code-length polarization codes by rows, and fig. 5 is a generator matrix map, where black squares represent 1 and white squares represent 0.

TABLE 2 codec Module interface definitions

The operation of the first part of the polarization encoding is described below.

The serial data read from the FIFO is subjected to an and operation with 32 bits output from the ROM2 at that time, and the 32-bit operation result is output, and the specific implementation circuit is shown in fig. 6.

The result of the above-mentioned AND is XOR-ed with the value stored by the time Register (REG), and the circuit implementation of the XOR unit is shown in FIG. 7.

A2-to-1 data selector MUX is additionally arranged in front of a Register (REG) in the first part of the encoder, and the data selector MUX is used for automatically resetting the data selector MUX to be 0 under the control of SEL control signals after the 32-length polarization encoding is completed, and then carrying out the next 32-length polarization encoding.

The second part of the polar code encoder performs a 5-layer butterfly diagram operation. The RAM adopts True-Dual-Port RAM, and has two ports for reading and writing. In the first partWhen lines are added, one port reads out the result of the 32 code length polarization coding completed by the previous first part from the RAM, and stores the result into the register REG, and at the same clock, the other port reads out the value of the previous address, and the value in the register is subjected to bitwise exclusive-OR, and then the result is stored into the address of the previous clock at the next clock. In order to reduce the time delay as much as possible, the second part and the first part of the encoder are run in parallel, that is, the second part has already started to perform the butterfly diagram operation on the encoding result which has been previously stored in the RAM without waiting for the first part to completely encode the 32 groups of 32 code length polarization codes. However, this may cause a conflict between the writing of the first part of the encoded result into the RAM and the RAM operation when the second part performs the butterfly operation, so that the first part of the encoder may transmit an interrupt signal to the second part in addition to transmitting the encoded result to the second part, and stop the butterfly operation performed by the second part, thereby avoiding the conflict. The control signals for the second part of the butterfly diagram operation multiplex the generator matrix of the first part of the encoder stored in ROM2

Since it can be noted that if the butterfly graph drawn by regarding 32 bits as a node is identical to the butterfly graph of the 32-code-length-polarization code, the operation performed by the second part of RAM is to correspond the current address to the generating matrix of fig. 5

Reading a certain row from the ROM2 (in practice, addressing the ROM2 by using the current RAM address), reading a 32-bit numerical value of the row vector read from the ROM2, wherein the first element is a column index (counted from 0) corresponding to 1 as an address, performing a bitwise exclusive-or operation with the value of the register, storing the numerical value back to the address addressed previously, updating the address to be a column index corresponding to the next element 1, and in order to better explain the above operation steps, as shown in fig. 8, assuming that the current address addr =6, first reading data with the RAM address of 6 and assigning the data to the Register (REG), and then reading the data from the ROM2, wherein the data is assigned to the Register (REG) and then assigning the data to the Register (REG) according to the current address addr =6

Row 6 (counted from 0), ROM2 outputs a row vector [1,0,1,0,1,0,1,0, …,0]Then, looking for element 1 in the row vector from left to right, we find that column 0 is an element 1, so we read out the data with RAM address 0, bitwise exclusive-or with the data previously stored in the Register (REG), compute the result back to address 0 of RAM; continuing to look for 1 element to the right and row vector is listed as 1 at column 2, so we read the data at RAM address 2, XOR it with the Register (REG) and write the result back to RAM address 2, repeating the above process until we traverse to row (addr-1) since after that the vector has all elements zero. After traversing the row vector, the address (addr) is added with 1, the value of the address is read from the RAM and assigned to the Register (REG), and the above operation is repeated.

After the second part completes the butterfly operation of the 32 nd block, the encoding is completed, the dataout _ valid is set to high level, and then the parallel-to-serial conversion is performed, and the circuit is implemented as shown in fig. 8, each clock performs the shift operation to the right, 32 bits of values are read out from the RAM every 32 clocks and assigned to the register, and after 1024 clocks are output, the dataout _ valid is reset to 0.

Claims

1. A high-performance polarization coding method for satellite discontinuous communication is characterized in that: the polarization coding method comprises two parts:

a first part: encoding a sub-polarization code;

s1, dividing a polarization code freezing bit and an information bit into a plurality of code blocks, performing polarization coding on each code block, and storing the information bit in a first ROM and the polarization coding in a second ROM;

s2, addressing the second ROM by using the position information of the information bit stored in the first ROM;

s3, performing bit exclusive OR on a certain line output by the first ROM and a data AND result read from the FIFO at the moment and a data result stored in the register REG, and storing the obtained numerical value back to the register REG;

s4, writing the coding result of the step S3 into an RAM, and starting the polarization coding of the next group of code length after the register REG is cleared;

a second part: carrying out XOR operation on the code blocks coded in the first step according to the butterfly diagram;

2. The method of claim 1, wherein the method comprises: the sub-polarization code encoding is carried out, wherein the most significant bit of the first ROM is used for controlling whether reading is carried out from the FIFO or not, the encoder is connected to FIFO read enable in implementation, the sixth bit controls whether the current encoding result is written into the RAM or not, when the current encoding result is in a high level, the first part of the encoding result currently stored in the register is written into the RAM, and the next group of 32-code-length polarization encoding is started; the sixth bit output by the first ROM is used for addressing the second ROM and controlling which row of the generator matrix is loaded currently; the second ROM is 32-bit wide, 32-depth ROM, and stores a 32 × 32 code length polarization code generating matrix by rows.

3. The method of claim 1, wherein the method comprises: the RAM in the second part adopts True-Dual-Port RAM which has two ports for reading and writing; while the first part is still accumulating, one of the ports reads the result of the previous first part that has completed 32-code long polarization encoding from the RAM, stores it in the register REG, and at the same clock, the other port of the RAM reads the value of the previous address, bitwise xors it with the value in the register, and stores the result in the address of the previous clock in the next clock.

4. The method of claim 1, wherein the method comprises: the second part and the first part are run in parallel, that is, the second part starts to carry out the butterfly diagram operation on the coding result which is stored in the RAM before, without waiting for the first part to completely code the 32 groups of 32 code long polarization codes.

5. The method of claim 4, wherein the method comprises: the parallel operation of the second part and the first part can cause the conflict between the operation of writing the coding result of the first part into the RAM and the RAM operation of the second part during butterfly operation, so that the first part can transmit an interrupt signal to the second part besides transmitting the coding result to the second part, stop the butterfly operation performed by the second part at the moment and avoid the conflict.

6. A high-performance polar code encoder facing satellite discontinuous communication is characterized in that: the encoder mainly comprises: the device comprises a CRC coding module, a FIFO, a first-level polar code coding module and a second-level polar code coding module;

the CRC coding module is used for adding CRC check to information bits;

wherein, the FIFO is used for buffering the information bits after CRC is added;

wherein, the first-stage polarization code coding module comprises:

a first ROM for storing a polarization code corresponding to each information bit

The number of rows of the matrix, used to address the second ROM;

a second ROM storing a code generation matrix of M-code long polarization codes

Outputting a certain row corresponding to the generating matrix according to the row number output by the first ROM;

the AND module carries out bitwise AND operation on the output of the second ROM and the output of the FIFO;

the exclusive OR module is used for carrying out bitwise exclusive OR operation on the result of the AND module and the result in the REG;

the REG is an M-bit register and is used for storing the operation result of the XOR module;

a MUX (multiplexer) which is a 1-from-2 selector and is used for clearing the REG before the next code block polarization code coding is carried out each time;

wherein, the second-stage polarization code coding module comprises:

the RAM is used for storing the code blocks coded by the first-stage polarization codes and reading the code blocks to perform second-stage polarization coding;

REG, which is a register module, and a part of the register module has two REGs in total, wherein one REG is used for temporarily storing a code block read out from the RAM, and the other REG is used for completing parallel-to-serial conversion;

and the exclusive-OR module is used for writing the REGs of the code blocks read out from the RAM and the code blocks read out from the temporary storage RAM into the RAM in a bitwise exclusive-OR mode.