CN111879998B - PT secondary loop voltage drop synchronous sampling method based on digital phase compensation - Google Patents
PT secondary loop voltage drop synchronous sampling method based on digital phase compensation Download PDFInfo
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Abstract
The application discloses a PT secondary circuit pressure drop synchronous sampling method based on digital phase compensation, which comprises the following steps: acquiring the system time of the device; the method comprises the steps that a host and a slave sequentially receive and transmit synchronous frames to obtain a host transmitting time, a slave receiving time, a slave transmitting time and a host receiving time of the receiving and transmitting synchronous frames; calculating the receiving and transmitting time delay and time offset of the host and the slave according to the obtained receiving and transmitting time; calculating a first angle difference value generated by data movement through time offset of a slave, calculating a second angle difference value generated by line delay through receiving and transmitting delay of the slave, and calculating a total first phase angle needing to be compensated from the slave to the time of a master clock 0 through a preset fifth formula; and calculating the angular difference of the PT secondary loop according to the first phase angle and the amplitude of the slave. According to the method and the device, the synchronous frame is sent by the power line carrier communication technology, and the phase angle difference is calculated by obtaining the sending and receiving time of the synchronous frame, so that clock synchronization can be realized without adding a time pulse modulation and demodulation hardware circuit.
Description
Technical Field
The application relates to the technical field of voltage transformers, in particular to a PT secondary circuit voltage drop synchronous sampling method based on digital phase compensation.
Background
When the PT secondary voltage drop of a traditional gateway metering secondary loop is tested, a PT secondary voltage drop tester is firstly connected to a combined wiring terminal box manually on a test site, and then a cable up to hundreds of meters is temporarily laid manually to connect the voltage of a local terminal box of a mutual inductor to the tester so as to test the secondary voltage drop. Although this method effectively solves the problem of synchronous sampling, extra test cables need to be laid, and especially, the test cables need to pass through a high-pressure area sometimes, so that the workload is high and the safety problem exists.
The power line carrier communication technology can realize reliable communication among multiple machines only through a power supply line, is widely applied to low-voltage power user centralized meter reading in recent years, and is verified in communication reliability and convenience through years of application practice. In the PT secondary circuit, connected equipment or loads are single, work is stable, interference is less, communication in a power line carrier mode becomes a preferred communication mode, but clock synchronization between a master extension set and a slave extension set or ADC (analog to digital converter) synchronous sampling between the master extension set and the slave extension set are achieved in the power line carrier mode, and the problem is great.
Due to the advantages of power line carrier communication, there are some related products, and communication and clock synchronization of the related products are completed in a power line carrier manner. The working principle is as follows: data communication and synchronous sampling are divided into two basically independent structures, a carrier module for data communication is responsible for data communication between a master extension set and a slave extension set, and a synchronization unit is only used for synchronous sampling of an ADC. When PT secondary voltage drop calculation is needed, a host controls and generates sampling pulses of an ADC, the sampling pulses are simultaneously divided into two paths for output, one path of the sampling pulses is directly output to the ADC of the host and is controlled to finish sampling, the other path of the sampling pulses is subjected to carrier modulation through a special carrier control circuit and then is sent to an extension, a special carrier demodulation circuit of the extension demodulates the sampling pulses, the sampling pulses at the moment are divided into two paths, one path of the sampling pulses finishes ADC sampling of a local extension, the other path of the sampling pulses is re-modulated and then is sent back to the host, the sampling pulses are received by the host and then are compared with original sent initial sampling pulses to calculate time difference of the sampling pulses, and delay compensation parameters of sampling of a master extension and a slave extension are calculated according to the time difference; and finishing the calculation result, and realizing communication through a carrier communication line so as to finish the measurement and calculation of the PT secondary voltage drop. However, the scheme of performing synchronization by using carrier communication can better solve the problem of synchronous sampling, but the scheme also needs to specially design another set of special pulse transceiving carrier circuit besides the carrier circuit for communication, and the circuit is complicated and has a large volume, so that the volume of the intelligent junction box is increased, and adverse effects are brought to the installation of the intelligent junction box.
Disclosure of Invention
The application provides a PT secondary circuit voltage drop synchronous sampling method based on digital phase compensation, so that clock synchronization can be realized without adding a time pulse modulation and demodulation hardware circuit.
In view of the above, the present application provides, in a first aspect, a digital phase compensation-based PT secondary loop voltage drop synchronous sampling apparatus, including:
a master machine on the ammeter side and a slave machine on the PT side;
the host and the slave comprise power line carrier modules and multi-channel synchronous sampling circuits;
the host and the slave are communicated through the power line carrier module, and the power line carrier module is also used for sending a synchronization frame to the host or the slave;
and sampling the host and the slave through the multi-channel synchronous sampling circuit.
Optionally, the master and the slave each further include a high-precision constant-temperature crystal oscillator for providing a stable clock frequency to the device.
Optionally, the master and the slave each further include a timer 1 and a port;
the timer 1 is used for controlling the sampling of ADC in the master machine and the slave machine;
and the SPORT port obtains sampling points in a DMA interrupt mode.
The second aspect of the present application provides a digital phase compensation-based PT secondary loop voltage drop synchronous sampling method, including:
acquiring system time of a host and a slave;
the host and the slave sequentially receive and transmit the synchronous frame to obtain a host transmitting time, a slave receiving time, a slave transmitting time and a host receiving time for receiving and transmitting the synchronous frame;
substituting the master machine sending time, the slave machine receiving time, the slave machine sending time and the master machine receiving time into a preset first formula to calculate the receiving and sending time delay of the master machine and the slave machine;
substituting the master machine sending time, the slave machine receiving time, the slave machine sending time and the master machine receiving time into a preset second formula to calculate the time offset of the master machine and the slave machine;
calculating a first angle difference value generated by data movement according to a preset third formula by the time offset of the slave, calculating a second angle difference value generated by line delay according to a preset fourth formula by the transceiving delay of the slave, and calculating a first phase angle of the slave at the time of virtually reaching a master clock 0 by a preset fifth formula;
and respectively substituting the first phase angle and the amplitude of the slave machine into a preset sixth formula to calculate the angle difference of the PT secondary circuit.
Optionally, the acquiring the system time of the master and the slave specifically includes:
acquiring accumulated values of sampling counters of the host and the slave;
the system time of the host is:
TMn＝MSampCnts*Ts+tmcnt
the system time of the slave machine is as follows:
TSn＝SSampCnts*Ts+tscnt
in the formula (TM)nIndicating the system time, TS, of the hostnIndicating the system time of the extension; tmcntThe count register value, ts, of timer 1 representing the hostcntA count register value representing a timer 1 of the slave; t issRepresenting the sampling periods of the master and the slave.
Optionally, the master and the slave sequentially receive and transmit the synchronization frame, and obtain a master sending time, a slave receiving time, a slave sending time, and a master receiving time of receiving and transmitting the synchronization frame, specifically:
the master machine sends a time setting pulse containing the master machine sending time to the slave machine at the signal zero crossing time, and when the slave machine receives pulse data, the slave machine records the slave machine receiving time in an interruption mode;
the slave sends the pulse data containing the slave sending time to the master at the signal zero-crossing time, and the slave records the slave sending time;
when the host receives the pulse data, recording the host receiving time in an interrupt mode;
and the master machine sends the pulse data containing the master machine receiving time to the slave machine, so that the slave machine obtains the master machine receiving time.
Optionally, the master sending time, the slave receiving time, the slave sending time, and the master receiving time are substituted into a preset first formula to calculate the sending and receiving delays of the master and the slave, where the preset first formula is:
Delay＝0.5*mean(TMR[0,n-1]-TMS[0,n-1]+TSR[0,n-1]-TSS[0,n-]1)
wherein TMR, TMS, TSR and TSS respectively represent the master sending time, the slave receiving time, the slave sending time and the master receiving time; TMR [ ] represents that the sliding window mode is adopted and is obtained by the nearest n time sequence points of the sending time of the host, wherein [0, n-1] represents a one-dimensional array containing n elements.
Optionally, the time offset between the master and the slave is calculated by substituting the master sending time, the slave receiving time, the slave sending time, and the master receiving time into a preset second formula, where the preset second formula is:
in an Offset-0.5 mean (TMR [0, n-1] -TMS [0, n-1] -TSR [0, n-1] -TSS [0, n-1]), TMR, TMS, TSR, and TSS respectively indicate the master transmission time, the slave reception time, the slave transmission time, and the master reception time; representing that the method adopts a sliding window mode and is obtained by the nearest n time sequence points, wherein [0, n-1] represents a one-dimensional array containing n elements; mean () represents the arithmetic mean of the sequences in parentheses.
Optionally, the time offset of the slave computer calculates a first angle difference value generated by data movement according to a preset third formula, the transceiving delay of the slave computer calculates a second angle difference value generated by line delay according to a preset fourth formula, and a preset fifth formula calculates a first phase angle at a time when the slave computer virtually reaches a master clock 0, where the preset third formula is:
Qtmod＝(360.0*freq*t_mod_Offset)/(1*10-9)
the preset fourth formula is as follows:
Qdelay＝-(360.0*freq*Delay)/(1*10-9)
the preset fifth formula is as follows:
Qslave＝Q1+Qtmod+Qdelay
in the formula (f)reqRepresenting the frequency of the sampled signal; q1 is the amplitude of the slave at the fundamental frequency; and TsThe sampling rate is the reciprocal of the sampling rate, and N is the number of sampling points per second; t _ mod _ Offset is given by:
N_Offset＝INT(Offset/(N*Ts))
t_mod_Offset＝Offset-N_Offset*Ts。
optionally, the first phase angle and the amplitude of the slave are respectively substituted into a preset sixth formula to calculate an angle difference and a ratio difference of the PT secondary circuit, where the preset sixth formula specifically is:
DeltaQ＝Qmast-Qslave
DeltaRMS＝RMSmast-RMSslave
in the formula, the phase value Q of the hostmastAmplitude RMSmast(ii) a Amplitude of slave is RMSslave。
According to the technical scheme, the method has the following advantages:
in the embodiment of the application, a digital phase compensation-based synchronous sampling method for the pressure drop of a PT secondary loop is provided, which comprises the following steps: acquiring system time of a host and a slave; the method comprises the steps that a host and a slave sequentially receive and transmit synchronous frames to obtain a host transmitting time, a slave receiving time, a slave transmitting time and a host receiving time of the receiving and transmitting synchronous frames; substituting the sending time of the host, the receiving time of the slave, the sending time of the slave and the receiving time of the host into a preset first formula to calculate the receiving and sending time delay of the host and the slave; substituting the master machine sending time, the slave machine receiving time, the slave machine sending time and the master machine receiving time into a preset second formula to calculate the time offset of the master machine and the slave machine; calculating a first angle difference value generated by data transfer according to a preset third formula by using the time offset of the slave, calculating a second angle difference value generated by line delay according to a preset fourth formula by using the receiving and transmitting delay of the slave, and calculating a first phase angle at the moment from the slave to the master clock 0 in a virtual mode by using a preset fifth formula; and respectively substituting the first phase angle and the amplitude of the slave machine into a preset sixth formula to calculate the angle difference of the PT secondary circuit.
According to the method, the receiving and sending time of the host and the slave for receiving and sending the synchronous frames is obtained through the time sequence of the host and the slave for sequentially receiving and sending the synchronous frames through the power line carrier communication technology, the receiving and sending time of the host and the slave for receiving and sending the synchronous frames is shifted through the receiving and sending time of the host and the slave, the phase angle difference is calculated, the first angle difference value generated by data shifting is calculated through the time shifting, the second angle difference value generated by line delay is calculated through the receiving and sending time delay, and therefore the total phase difference needing to be compensated is obtained, and therefore the clock synchronization can be achieved without adding a time pulse modulation and demodulation hardware circuit.
Drawings
Fig. 1 is a device structure diagram of an embodiment of a PT secondary loop voltage drop synchronous sampling device based on digital phase compensation according to the present application;
fig. 2 is a schematic time delay diagram of data transmission and reception between a master and a slave according to an embodiment of the present application;
FIG. 3 is a flow chart of a method of an embodiment of a digital phase compensation based synchronous sampling method for PT secondary loop voltage drop according to the present application;
fig. 4 is a schematic diagram of a transmission flow and each transceiving time of a synchronization frame between a host and an extension in the embodiment of the present application;
FIG. 5 is a timing diagram illustrating data movement according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a block diagram of an embodiment of a digital phase compensation-based PT secondary loop voltage drop synchronous sampling device according to the present invention, as shown in fig. 1, where fig. 1 includes:
the intelligent junction box (host) on the electric meter side is 1, the PT secondary loop monitoring unit (slave) is 2, and data communication is carried out between the host and the slave through the power line carrier modules 103 and 203 through the PT secondary voltage outlet 3.
In addition, the host and the extension both comprise a CPU processing chip and an ADC chip. Specifically, the CPU may adopt BF609 processor, and the ADC may adopt AD7608 chip. The processor is a dual-core DSP processor, the running speed of the processor is up to 500Mhz, task management, alternating current sampling calculation and the like are respectively completed by different cores, and the real-time performance of task processing is guaranteed.
In a specific implementation manner, in order to ensure the clock precision and stability of the master-slave units in the operation process, in the design of the clock circuits of the master unit and the slave units, high-precision constant-temperature crystal oscillators of the same model and specification are used as the master clock source of the device. Specifically, the main indexes of the high-precision constant-temperature crystal oscillation are as follows: initial error 0.5 x 10-9In normal working range, the influence of supply voltage, temperature and load is not more than 0.1 x 10-9Aging was 0.5 x 10-9So that if the device is not calibrated, its maximum clock deviation after one year does not exceed 1.3 x 10-9。
In addition, a standard clock source, such as a GPS time service device, may be used to calibrate the crystal oscillator. The specific calibration method can continuously acquire the period of the standard pulse-per-second signal within 5 minutes by using a capture mode of a BF609 timer, and the standard pulse-per-second period can be obtained by averaging the periods of the standard pulse-per-second signal within 5 minutes. Comparing the standard second pulse period with the second pulse period of the machine to obtain the system time of the deviceThe clock calibration coefficients. Because of the total accumulated number of second pulse periods captured continuously by the BF609 timer in 5 minutes, the total error is not more than 1 pulse theoretically, namely the acquisition error of the second pulse frequency is 8 Ns/300-0.026 Ns, and the error is far smaller than the deviation caused by voltage, temperature and the like. After the system clock is calibrated, the influences of initial errors, power supply voltage and the like can be basically and completely corrected, so that the maximum deviation of the system clock of the device in one year after calibration can not exceed 0.5 x 10-9I.e. the frequency deviation between master and slave extensions does not exceed 1 x 10 at the maximum-9Thus, the 1000-second synchronization error between the master and the slave is ensured to be not more than 1 mu s. Experiments show that the time-keeping error of 30 minutes can be guaranteed not to exceed 1 mu s after GPS calibration is adopted.
In a specific embodiment, the master and the slave each include a power line carrier module and a multi-channel synchronous sampling circuit, the master and the slave communicate with each other through the power line carrier module, and the power line carrier module is further configured to send a synchronous frame to the master or the slave; and the ADC of the master machine and the slave machine are sampled by a multi-channel synchronous sampling circuit.
Specifically, data communication between the host and the extension and receiving and sending of synchronous pulse signals are achieved through a power line carrier module commonly used by a low-voltage power distribution user centralized meter reading system, data interaction between a chip of the power line carrier module and a CPU is achieved through an asynchronous communication serial port, and accurate time scales of improvement and receiving of the power line carrier module are recorded in an independent IO interruption mode.
In a specific embodiment, the master and the slave each further include a timer 1 and a port; the timer 1 is used for controlling the sampling of the ADC in the master computer and the slave computer; the SPORT port obtains sampling points through a DMA interrupt mode.
Specifically, ADC sampling of the master slave extension and the slave extension is controlled by timers 1 in the host and the extension respectively, and is collected into a cache in a DMA (direct memory access) interruption mode of a SPORT (port order port), so that the time of each sampling point is completely accurate and no point is lost. Since the count value of the BF609 timer can be read at any time, the count value of the timer 1 is read in an interrupt manner when the clock tick is sent. In a specific programming, a 64-bit integer variable sampling clock counter msampcounts (master) and ssampcounts (master) may be set to store all count accumulated values of the timers 1 in the master and the slave after the start-up.
FIG. 2 is a schematic time-delay diagram of data transmission and reception between the master and the slave, where Ts1i,TL,TR1iRespectively representing the internal time delay of a power line carrier module in the host, the time delay on a power line and the internal time delay of the power line carrier module in the slave when the data pulse is sent from the host to the slave; t iss2i，TL，TR2iThe time delay method comprises the steps of respectively representing the internal time delay of a power line carrier module in the slave machine, the time delay on a power line and the internal time delay of the power line carrier module in the host machine when data pulses are sent from the slave machine to the host machine. Besides the uncertain jitter of the transceiving time of the power line carrier module, other delays can be determined.
Due to the mechanisms of task processing, zero-crossing detection, data modulation and transmission and the like in the common power line carrier module, the receiving and transmitting of the power line carrier module have a maximum delay jitter of about 20 Ms. In order to eliminate the influence as much as possible, the invention adopts several measures, one is that the power line carrier module of the host computer or the slave computer adopts the same module; one is to shut down the functions of ad hoc networks, multi-level routing and the like and only use the point-to-point data transparent transmission function; then, a power line fast carrier module is added to increase the task processing speed so as to improve the real-time performance of communication; and finally, when the PT secondary voltage drop measuring device is communicated with the PT secondary voltage drop measuring device, the signal zero-crossing time is obtained according to the internal ADC sampling result, and the transmission is started by a time difference which is fixed relative to the zero-crossing point when the synchronous frame is transmitted each time. Thus, under the same transceiving characteristics, the average value of the transceiving delay of the master module and the slave module tends to a constant value. For convenient calculation, the receiving and transmitting Delay of the master slave extension set can be called Delay collectively, and the following requirements are met:
according to the method, the receiving and sending time of the host and the slave for receiving and sending the synchronous frames is obtained through the time sequence of the host and the slave for sequentially receiving and sending the synchronous frames through the power line carrier communication technology, the receiving and sending time of the host and the slave for receiving and sending the synchronous frames is shifted through the receiving and sending time of the host and the slave, the phase angle difference is calculated, the first angle difference value generated by data shifting is calculated through the time shifting, the second angle difference value generated by line delay is calculated through the receiving and sending time delay, and therefore the total phase difference needing to be compensated is obtained, and therefore the clock synchronization can be achieved without adding a time pulse modulation and demodulation hardware circuit.
Referring to fig. 3, fig. 3 is a flowchart illustrating a method for synchronously sampling PT secondary loop voltage drop based on digital phase compensation according to an embodiment of the present invention, as shown in fig. 3, where fig. 3 includes:
101. acquiring system time of a host and a slave;
in fig. 1, the master and slave timers 1 start ADC sampling for the master and slave, respectively, and record the accumulated count values of the master and slave.
After the device is powered on firstly, the host computer and the slave computer are in a fixed sampling period TsThe ADC sampling is started by the timers 1 of the host and the slave, and sampling points can be collected into a buffer area by a DMA (direct memory access) interruption mode of SPORT (port order counter) ports in the host and the slave, so that the time of each sampling point can be accurate and points cannot be lost. When the buffer area is full, the device generates an interrupt, and records the accumulated value of the sampling number of the first sampling point in the buffer area in the variable MSampcnts (host) and SSampcnts (extension) of the sampling counter.
Calculating the frequency of sampling signals in the host and the slave, the zero crossing point time of the signals (the zero crossing point time of the signals is used for the subsequent host or the slave to receive and send data pulse signals) and the counting register value of the timer 1; the ADC sampling timer records the system time of the host and the slave as:
TMn＝MSampCnts*Ts+tmcnt
TSn＝SSampCnts*Ts+tscnt
in the formula (TM)nIndicating the system time, TS, of the hostnSystem for representing extensionsTime; tmcntThe count register value, ts, of timer 1 representing the hostcntA count register value representing a timer 1 of the slave; specifically, the resolution may be set to 8 Ns.
102. The method comprises the steps that a host and a slave sequentially receive and transmit synchronous frames to obtain a host transmitting time, a slave receiving time, a slave transmitting time and a host receiving time of the receiving and transmitting synchronous frames;
it should be noted that the specific steps of acquiring the master sending time, the slave receiving time, the slave sending time, and the master receiving time may include:
s1: the method comprises the steps that a master machine sends a time setting pulse containing the master machine sending time to a slave machine at the signal zero crossing point time, when the slave machine receives pulse data, the slave machine records the slave machine receiving time in an interruption mode, and at the moment, the slave machine obtains the master machine sending time and the slave machine receiving time;
s2: the slave machine sends pulse data containing the sending time of the slave machine to the host machine at the signal zero crossing time, the slave machine records the sending time of the slave machine, and the slave machine obtains the sending time of the slave machine at the moment;
s3: when the host receives the pulse data, recording the host receiving time in an interrupt mode;
s4: the master machine sends the pulse data containing the receiving time of the master machine to the slave machine, so that the slave machine obtains the receiving time of the master machine.
Through the steps, the slave can obtain complete master sending time, slave receiving time, slave sending time and master receiving time. The above steps can refer to fig. 4, where fig. 4 includes the transmission and reception of 4 frame data, and tms (n), tmr (n), tss (n), and tsr (n) in the figure respectively represent master transmission time, slave reception time, slave transmission time, and master reception time.
103. Substituting the sending time of the host, the receiving time of the slave, the sending time of the slave and the receiving time of the host into a preset first formula to calculate the receiving and sending time delay of the host and the slave;
104. substituting the master machine sending time, the slave machine receiving time, the slave machine sending time and the master machine receiving time into a preset second formula to calculate the time offset of the master machine and the slave machine;
it should be noted that the transceiving Delay between the host and the extension can be set as Delay and time Offset;
the following calculation formula and result can be obtained according to the principle of E2E:
TMR(n)＝TMS(n)+offset+Delay
TSR(n)＝TSS(n)-offset+Delay
the first preset formula is:
Delay＝0.5*mean(TMR[0,n-1]-TMS[0,n-1]+TSR[0,n-1]-TSS[0,n-]1)
the second preset formula is:
the master-slave unit is calculated from the master transmission time, the slave reception time, the slave transmission time, and the master reception time in the expression 0.5 mean (TMR [0, n-1] -TMS [0, n-1] -TSS [0, n-1]), and is obtained from the nearest n time-series points by using a sliding window method, where [0, n-1] represents a one-dimensional array having n elements. Delay is obtained by averaging (or low-pass filtering) the calculated one-dimensional arrays of the arrays, so as to compensate the phase angle difference in the subsequent steps, wherein the Delay is mainly generated by the line Delay. Offset is time Offset, i.e. the obtained Offset and the time synchronization sequence can be used to complete the time synchronization operation for the slave unit, where the time Offset is mainly generated by data movement.
105. Calculating a first angle difference value generated by data transfer according to a preset third formula by using the time offset of the slave, calculating a second angle difference value generated by line delay according to a preset fourth formula by using the receiving and transmitting delay of the slave, and calculating a first phase angle at the moment from the slave to the master clock 0 in a virtual mode by using a preset fifth formula;
data transfer may be performed according to a time offset. Specifically, in the slave, the time Offset is modulo one second to obtain a synchronous sampling Offset value OffsetMod after the second alignment:
OffsetMod＝8*(Offset％125000000)
the aim of synchronization is achieved by copying the memory. The clock frequency of the timer is 125MHz, i.e. each count value is 8Ns, and the operator "%" indicates modulo.
As shown in fig. 4, a point is taken at one second intervals to start the calculation. Before calculation, the sampling time of the slave computer is virtualized to the phase of 0 time of the master clock second, and the virtual 0 sampling point (namely the reference second alignment point) of the slave computer is moved. If the original sampling Data of the slave is Data [0, n-1], the shifted Data is:
N_Offset＝INT(Offset/(N*Ts))
in the formula, TsIs the reciprocal of the sampling rate, N is the number of samples per second, and INF () is the rounding operation.
t_mod_Offset＝Offset-N_Offset*Ts
If the remainder part obtained by the above formula calculation is used for compensation during phase calculation, the data cache array DataCal to be calculated is as follows:
DataCal[0,N-N_Offset-1]＝Data[N_Offset,N-1]
DataCal[N-N_Offset,N_Offset]＝Data[0,N_Offset]
calculating the phase angle of the sampled data, and performing corresponding compensation to make the shifted data cached as DataCal [0, N-1], performing Discrete Fourier Transform (DFT) operation on the data, to obtain the angular difference Q1 and the amplitude RMSslave of the DataCal sampled sequence relative to the time 0, specifically, comprising:
the DFT of the known N-point sequence x (N) is:
further transformation is as follows:
and substituting x (N) in DataCal [0, N-1] into the above formula, and performing DFT to obtain transformed x (k), and when only the amplitude and phase of the fundamental frequency need to be calculated, that is, k is 1, further obtaining from the above formula:
Q1＝atan2(Imag,Real)*180.0/π
RMSslave＝K*sqrt(Real2+Imag2)
wherein Q1 represents the phase, RMS, of the fundamental frequency of the slaveslaveRepresenting the magnitude of the slave fundamental frequency; atan2(y, x) calls the arctan function and can calculate the phase angle of a complex number; and K is a calibration coefficient corresponding to the voltage amplitude, and calibration is carried out before delivery.
When the buffer data is moved, the buffer data is moved according to an integral point, the remainder part left when the sampling point is taken is calculated and needs to be converted into a corresponding angular difference value to compensate the phase, and then a compensation value obtained by a third preset formula is as follows:
Qtmod＝(360.0*freq*t_mod_Offset)/(1*10-9)
in which the frequency f of the sampled signalreq。
The angular difference value converted by the preset fourth formula for calculating the line delay is as follows:
Qdelay＝-(360.0*freq*Delay)/(1*10-9)
finally, the total phase angle Q from the slave virtual to the master clock 0 time needs to be calculatedslaveThat is, the total phase compensation value can be obtained by presetting the fifth formula as follows:
Qslave＝Q1+Qtmod+Qdelay。
106. respectively substituting the first phase angle and the amplitude of the slave machine into a preset sixth formula to calculate the angle difference of the PT secondary circuit;
it should be noted that the host calculates the virtual phase value and amplitude value of the sampling value of the host with respect to the PPS zero point according to the virtual 0 point of the sampling, i.e. the PPS zero point of the system. Similarly, the phase value Q of the host can be obtained by the calculation formula in step 105mastAmplitude RMSmast；
When slave is set as PT side, the angle difference of PT secondary loop is:
DeltaQ＝Qmast-Qslave
DeltaRMS＝RMSmast-RMSslave
according to the method, the receiving and sending time of the host and the slave for receiving and sending the synchronous frames is obtained through the time sequence of the host and the slave for sequentially receiving and sending the synchronous frames through the power line carrier communication technology, the receiving and sending time of the host and the slave for receiving and sending the synchronous frames is shifted through the receiving and sending time of the host and the slave, the phase angle difference is calculated, the first angle difference value generated by data shifting is calculated through the time shifting, the second angle difference value generated by line delay is calculated through the receiving and sending time delay, and therefore the total phase difference needing to be compensated is obtained, and therefore the clock synchronization can be achieved without adding a time pulse modulation and demodulation hardware circuit.
On one hand, the long-time stability of the high-precision constant-temperature crystal oscillator is utilized, and the long-time stability of the high-precision constant-temperature crystal oscillator can be guaranteed to be 0.5 x 10 after the high-time stability is calibrated by using a standard clock-9To ensure that the sampling frequency of the slave does not need to be calibrated when the system clock is synchronized. On the other hand, the host and the extension adopt the same power line carrier modules, then the functions of the power line carrier modules are simplified and the real-time performance is optimized, when a CPU of the monitoring equipment sends synchronous data frames to the power line carrier modules, the synchronous data frames are sent according to fixed zero-crossing time every time, the statistical value of receiving and sending delay is guaranteed to be a measurable constant, and the receiving and sending stages are equal, so that the sampling synchronization can be realized only by running for a long time for synchronization. And finally, sampling by the timer 1 for the host machine and the extension machines, and calculating the phase angle and the amplitude of the slave machine relative to the virtual zero moment by using a digital phase compensation method after the sampling synchronization of the host machine and the extension machines, thereby realizing the online measurement of the PT secondary voltage drop.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The terms "first," "second," "third," "fourth," and the like in the description of the application and the above-described figures, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (7)
1. A PT secondary loop voltage drop synchronous sampling method based on digital phase compensation is characterized by comprising the following steps:
acquiring system time of a host and a slave;
the host and the slave sequentially receive and transmit the synchronous frame to obtain a host transmitting time, a slave receiving time, a slave transmitting time and a host receiving time for receiving and transmitting the synchronous frame;
substituting the master machine sending time, the slave machine receiving time, the slave machine sending time and the master machine receiving time into a preset first formula to calculate the receiving and sending time delay of the master machine and the slave machine;
substituting the master machine sending time, the slave machine receiving time, the slave machine sending time and the master machine receiving time into a preset second formula to calculate the time offset of the master machine and the slave machine;
calculating a first angle difference value generated by data movement according to a preset third formula by the time offset of the slave, calculating a second angle difference value generated by line delay according to a preset fourth formula by the receiving and transmitting delay of the slave, and calculating a first phase angle of the slave at the time of virtually reaching a master clock 0 by a preset fifth formula;
and respectively substituting the first phase angle and the amplitude of the slave machine into a preset sixth formula to calculate the angle difference of the PT secondary circuit.
2. The digital phase compensation-based PT secondary loop voltage drop synchronous sampling method of claim 1, wherein the obtaining system time of the master and slave specifically comprises:
acquiring accumulated values of sampling counters of the host and the slave;
the system time of the host is:
TMn＝MSampCnts*Ts+tmcnt
the system time of the slave machine is as follows:
TSn＝SSampCnts*Ts+tscnt
in the formula (TM)nIndicating the system time, TS, of the hostnIndicating the system time of the extension; tmcntThe count register value of timer 1 representing the host,tscnta count register value representing a timer 1 of the slave; t issRepresenting the sampling periods of the master and the slave.
3. The digital phase compensation-based PT secondary loop voltage drop synchronous sampling method of claim 1, wherein the master and the slave sequentially receive and transmit a synchronous frame, and obtain a master transmission time, a slave reception time, a slave transmission time and a master reception time for receiving and transmitting the synchronous frame, specifically:
the master machine sends a time setting pulse containing the master machine sending time to the slave machine at the signal zero crossing time, and when the slave machine receives pulse data, the slave machine records the slave machine receiving time in an interruption mode;
the slave sends the pulse data containing the slave sending time to the master at the signal zero-crossing time, and the slave records the slave sending time;
when the host receives the pulse data, recording the host receiving time in an interrupt mode;
and the master machine sends the pulse data containing the master machine receiving time to the slave machine, so that the slave machine obtains the master machine receiving time.
4. The digital phase compensation-based PT secondary loop voltage drop synchronous sampling method of claim 1, wherein said substituting said master transmit time, slave receive time, slave transmit time and master receive time into a preset first formula calculates the transmit and receive delays of said master and said slave, said preset first formula is:
Delay＝0.5*mean(TMR[0,n-1]-TMS[0,n-1]+TSR[0,n-1]-TSS[0,n-1])
wherein TMR, TMS, TSR and TSS respectively represent the master sending time, the slave receiving time, the slave sending time and the master receiving time; TMR [ ] represents that the system is obtained by using a sliding window mode from the nearest n time sequence points of the sending time of the host, wherein [0, n-1]
Representing a one-dimensional array comprising n elements.
5. The digital phase compensation-based PT secondary loop voltage drop synchronous sampling method of claim 1, wherein the time offsets of the master and the slave are calculated by substituting the master transmission time, the slave reception time, the slave transmission time and the master reception time into a preset second formula, the preset second formula is:
Offset＝0.5*mean(TMR[0,n-1]-TMS[0,n-1]-TSR[0,n-1]-TSS[0,n-1])
wherein TMR, TMS, TSR and TSS respectively represent the master sending time, the slave receiving time, the slave sending time and the master receiving time; representing that the method adopts a sliding window mode and is obtained by the nearest n time sequence points, wherein [0, n-1] represents a one-dimensional array containing n elements; mean () represents the arithmetic mean of the sequences in parentheses.
6. The digital phase compensation-based PT secondary loop voltage drop synchronous sampling method of claim 1, wherein said time offset of said slave computer calculates a first angle difference value generated by data migration according to a preset third formula, said transceiving delay of said slave computer calculates a second angle difference value generated by line delay according to a preset fourth formula, a preset fifth formula calculates a first phase angle of a virtual-to-master clock 0 time of said slave computer, and said preset third formula is:
Qtmod＝(360.0*freq*t_mod_Offset)/(1*10-9)
the preset fourth formula is as follows:
Qdelay＝-(360.0*freq*Delay)/(1*10-9)
the preset fifth formula is as follows:
Qslave＝Q1+Qtmod+Qdelay
in the formula (f)reqRepresenting the frequency of the sampled signal; q1 is the amplitude of the slave at the fundamental frequency; and TsThe sampling rate is the reciprocal of the sampling rate, and N is the number of sampling points per second; t _ mod _ Offset fromThe formula is obtained:
N_Offset＝INT(Offset/(N*Ts))
t_mod_Offset＝Offset-N_Offset*Ts。
7. the digital phase compensation-based PT secondary loop voltage drop synchronous sampling method of claim 1, wherein the first phase angle and amplitude of the slave are respectively substituted into a preset sixth formula to calculate an angle difference and a ratio difference of a PT secondary loop, the preset sixth formula is specifically as follows:
DeltaQ＝Qmast-Qslave
DeltaQRMS＝RMSmast-RMSslave
in the formula, the phase value Q of the hostmastAmplitude RMSmast(ii) a Amplitude of slave is RMSslave。
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