CN111798889A

CN111798889A - Data reading method, storage controller and storage device

Info

Publication number: CN111798889A
Application number: CN201910274380.0A
Authority: CN
Inventors: 萧又华
Original assignee: Shenzhen Daxin Electronic Technology Co ltd
Current assignee: Shenzhen Daxin Electronic Technology Co ltd
Priority date: 2019-04-08
Filing date: 2019-04-08
Publication date: 2020-10-20

Abstract

The invention provides a data reading method, a storage controller and a storage device. The method comprises the following steps: performing a read operation on the target word line; reading a plurality of target entity pages of the target word line to obtain a plurality of hard bit code words respectively corresponding to the target entity pages; generating respective soft information for a plurality of target memory cells of the target word line based on the plurality of hard bit codewords; identifying a plurality of confidence degrees of the target storage units corresponding to the target entity pages respectively according to a plurality of confidence tables and a plurality of soft information of the target storage units; and executing the adjusted preset decoding operation according to the confidence degrees and the soft information to obtain a plurality of final decoded code words respectively corresponding to the target entity pages, and finishing the reading operation.

Description

Data reading method, storage controller and storage device

Technical Field

The present invention relates to a data reading method, and more particularly, to a data reading method suitable for a memory device configured with a rewritable nonvolatile memory module and a memory controller thereof.

Background

Generally, when an iterative decoding operation (e.g., a low density parity check code decoding operation) performed on a codeword read from a physical side of a rewritable non-volatile memory module fails, a memory controller of a memory device attempts to correct a log-likelihood ratio table corresponding to the iterative decoding operation according to verification data (e.g., known data stored in advance in the rewritable non-volatile memory module) so as to perform the iterative decoding operation on the read codeword again by using the corrected log-likelihood ratio table.

However, since the conventional method requires additional preparation of the known verification data (i.e., storing the known verification data in a plurality of word lines of the rewritable nonvolatile memory module), the conventional method uses the free space of the rewritable nonvolatile memory module to store the verification data, thereby reducing the remaining available space of the rewritable nonvolatile memory module, and further causing the operating efficiency of the memory device to be reduced due to the reduced remaining available space (since many management operations of the memory device require the use of the remaining available space).

Therefore, it is one of the subjects studied by those skilled in the art to efficiently use other methods to replace the conventional log-likelihood ratio table corresponding to the iterative decoding operation without preparing verification data, so as to improve the defects of the conventional method, improve the performance of the decoding operation, and improve the data reading efficiency of the rewritable nonvolatile memory module.

Disclosure of Invention

The invention provides a data reading method, a storage controller and a storage device, which can utilize a plurality of target entity pages of a read target word line to obtain a plurality of hard bit code words under the condition of not preparing verified data, utilize the plurality of hard bit code words to generate respective soft information of a plurality of target storage units of the target word line and find out a plurality of confidence degrees of the plurality of target storage units corresponding to the plurality of target entity pages, and further execute an adjusted iterative decoding operation according to the plurality of confidence degrees so as to strengthen the decoding capability and improve the efficiency of the reading operation.

An embodiment of the present invention provides a data reading method for a storage device configured with a rewritable nonvolatile memory module. The rewritable non-volatile memory module has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells comprises a plurality of physical pages, and each of the plurality of physical pages is configured to be programmed to a bit value. The method comprises the following steps: selecting a target word line to perform a read operation on the target word line; reading a plurality of target entity pages of the target word line by using a preset reading voltage group to obtain a plurality of hard bit code words respectively corresponding to the target entity pages; generating respective soft information for a plurality of target memory cells of the target word line based on the plurality of hard bit codewords; identifying a plurality of confidence levels of the target storage units corresponding to the target entity pages respectively according to a plurality of confidence tables respectively corresponding to the target entity pages and a plurality of soft information of the target storage units, wherein the plurality of confidence tables respectively have a plurality of preset confidence levels respectively corresponding to a plurality of threshold voltage distribution areas, and the plurality of threshold voltage distribution areas correspond to a plurality of Golay code patterns; and replacing the plurality of confidence degrees of the plurality of target storage units with a plurality of log-likelihood ratio values corresponding to the plurality of target storage units in the preset decoding operation, and performing an adjusted preset decoding operation with the replaced plurality of log-likelihood ratio values on the plurality of soft information to obtain a plurality of final decoded code words respectively corresponding to the plurality of target entity pages, and completing the reading operation.

An embodiment of the present invention provides a memory controller for controlling a memory device configured with a rewritable non-volatile memory module. The storage controller includes: the circuit comprises a connection interface circuit, a memory interface control circuit, a reading auxiliary circuit unit, an error checking and correcting circuit and a processor. The connection interface circuit is used for being coupled to a host system. The memory interface control circuit is configured to be coupled to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of word lines, each of the plurality of word lines is coupled to a plurality of memory cells, each of the plurality of memory cells includes a plurality of physical pages, and each of the plurality of physical pages is configured to be programmed to a bit value. The processor is coupled to the connection interface circuit, the memory interface control circuit, the read assist circuit unit, and the error checking and correcting circuit. The processor is used for selecting a target word line in the word lines of the rewritable nonvolatile memory module so as to execute read operation on the target word line. The read assist circuit unit is configured to read a plurality of target physical pages of the target word line using the set of preset read voltages to obtain a plurality of hard bit codewords corresponding to the plurality of target physical pages, respectively, wherein the read assist circuit unit is further configured to generate soft information of each of a plurality of target memory cells of the target word line according to the plurality of hard bit codewords, wherein the read assist circuit unit is further configured to identify a plurality of confidence levels of each of the plurality of target memory cells corresponding to the plurality of target physical pages according to a plurality of confidence tables corresponding to the plurality of target physical pages and the plurality of soft information of each of the plurality of target memory cells, wherein each of the plurality of confidence tables has a plurality of preset confidence levels corresponding to a plurality of threshold voltage distribution areas, respectively, wherein the plurality of threshold voltage distribution areas correspond to a plurality of gray code patterns, the error checking and correcting circuit is configured to replace the plurality of confidence levels of the plurality of target memory cells with a plurality of log-likelihood ratios corresponding to the plurality of target memory cells in the preset decoding operation, and perform an adjusted preset decoding operation with the replaced plurality of log-likelihood ratios on the plurality of soft information to obtain a plurality of final decoded codewords corresponding to the plurality of target entity pages, respectively, thereby completing the reading operation.

An embodiment of the present invention provides a memory device. The storage device comprises a rewritable nonvolatile memory module, a memory interface control circuit and a processor. The rewritable non-volatile memory module has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells comprises a plurality of physical pages, and each of the plurality of physical pages is configured to be programmed to a bit value. The memory interface control circuit is used for being coupled to the rewritable nonvolatile memory module. The processor is coupled to the memory interface control circuit, and loads and executes the reading auxiliary program code module to realize the data reading method. The data reading method comprises the following steps: selecting a target word line to perform a read operation on the target word line; reading a plurality of target entity pages of the target word line by using the preset reading voltage group to obtain a plurality of hard bit code words respectively corresponding to the target entity pages; generating respective soft information for a plurality of target memory cells of the target word line based on the plurality of hard bit codewords; identifying a plurality of confidence levels of the target storage units corresponding to the target entity pages respectively according to a plurality of confidence tables respectively corresponding to the target entity pages and a plurality of soft information of the target storage units, wherein the plurality of confidence tables respectively have a plurality of preset confidence levels respectively corresponding to a plurality of threshold voltage distribution areas, and the plurality of threshold voltage distribution areas correspond to a plurality of Golay code patterns; and replacing the plurality of confidence degrees of the plurality of target storage units with a plurality of log-likelihood ratio values corresponding to the plurality of target storage units in the preset decoding operation, and performing an adjusted preset decoding operation with the replaced plurality of log-likelihood ratio values on the plurality of soft information to obtain a plurality of final decoded code words respectively corresponding to the plurality of target entity pages, and completing the reading operation.

Based on the above, the data reading method, the memory controller and the memory device provided in the embodiments of the present invention can utilize a plurality of target physical pages of a read target word line to obtain a plurality of hard bit code words without preparing verified data, and utilize the plurality of hard bit code words to generate respective soft information of a plurality of target memory cells of the target word line. Then, the data reading method, the memory controller and the memory device provided in the embodiments of the present invention may further obtain the confidence levels of the target memory cells corresponding to the target entity pages by searching the confidence tables corresponding to the target entity pages using the soft information, and further perform the adjusted iterative decoding operation according to the confidence levels of the target memory cells corresponding to the target entity pages, so as to enhance the decoding capability and improve the efficiency of the reading operation. Therefore, the correctness and the reliability of the data read from the target word line can be improved, the load of the decoding operation performed on the read data is reduced, and the overall efficiency of the data reading operation is improved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a block diagram illustrating a host system and a storage device according to an embodiment of the invention;

FIG. 2 is a flow chart illustrating a data reading method according to an embodiment of the invention;

FIG. 3A is a diagram illustrating a threshold voltage distribution and corresponding Gray code pattern of a first read voltage pattern 1/2/4 according to one embodiment of the present invention;

FIG. 3B is a diagram illustrating a threshold voltage distribution and a corresponding Gray code pattern of a second read voltage pattern (2/3/2), according to one embodiment of the invention;

FIG. 4A is a diagram illustrating a confidence table for setting a first read voltage pattern (1/2/4), according to one embodiment of the invention;

FIG. 4B is a diagram illustrating a confidence table corresponding to a first read voltage pattern (1/2/4), according to one embodiment of the invention;

FIG. 5A is a schematic diagram illustrating a table of confidence in setting a second read voltage pattern (2/3/2) according to one embodiment of the invention;

FIG. 5B is a diagram illustrating a confidence table corresponding to a second read voltage pattern 2/3/2 according to an embodiment of the invention.

Description of the reference numerals

10: host system

20: storage device

110. 211: processor with a memory having a plurality of memory cells

120: host memory

130: data transmission interface circuit

210: storage controller

212: data management circuit

213: memory interface control circuit

214: error checking and correcting circuit

215: read assist circuit unit

2151: soft information management circuit

2152: confidence table management circuit

218: buffer memory

219: power management circuit

220: rewritable nonvolatile memory module

230: connection interface circuit

S21, S22, S23, S24, S25: flow steps of data reading method

V(1)₁～V(i)₇: read voltage

L: bit value of lower entity page

M: bit value of middle entity page

U: bit value of upper entity page

G1-G8: region of critical voltage distribution

SL1, SL 2: storage state of lower entity page

SM1, SM2, SM 3: memory state of middle entity page

SU1, SU2, SU3, SU4, SU 5: memory state of upper entity page

400. 500: soft information

410. 420, 430, 510, 520, 530: confidence watch

410(1) - (410 (8), 420(1) - (420 (8), 430(1) - (430 (8)), 510(1) - (510 (8), 520(1) - (520 (8)), 530(1) - (530 (8)): preset confidence level

Detailed Description

In the embodiment, the memory device includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a memory device controller (also referred to as a memory controller or a memory control circuit). Further, the storage device is used with a host system so that the host system can write data to or read data from the storage device.

FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention.

Referring to fig. 1, a Host System (Host System)10 includes a Processor (Processor)110, a Host Memory (Host Memory)120, and a Data Transfer Interface Circuit (Data Interface Circuit) 130. In the present embodiment, the data transmission interface circuit 130 is coupled (also referred to as electrically connected) to the processor 110 and the host memory 120. In another embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 are coupled to each other by a System Bus (System Bus).

The Memory device 20 includes a Memory Controller (Storage Controller)210, a Rewritable Non-Volatile Memory Module (Rewritable Non-Volatile Memory Module)220, and a connection interface Circuit (connection interface Circuit) 230. The Memory controller 210 includes a processor 211, a data management Circuit (DataManagement Circuit)212, and a Memory Interface Control Circuit (Memory Interface Control Circuit) 213.

In the present embodiment, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operation. For example, the host system 10 may store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.

In the present embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 may be disposed on a motherboard of the host system 10. The number of the data transmission interface circuits 130 may be one or more. The motherboard can be coupled to the memory device 20 via a wired or wireless connection via the data transmission interface circuit 130. The storage device 20 may be, for example, a usb disk, a memory card, a Solid State Drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon), which are based on various wireless Communication technologies. In addition, the motherboard may also be coupled to various I/O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, and the like through a System bus.

In the present embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the PCI Express (Peripheral Component Interconnect Express) standard. The data transmission interface circuit 130 and the connection interface circuit 230 transmit data by using a Non-Volatile Memory interface (NVMe) protocol.

However, it should be understood that the present invention is not limited thereto, and the data transmission interface circuit 130 and the connection interface circuit 230 may also conform to Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Serial Advanced Technology Attachment (SATA) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed (UHS-eMI) interface standard, Ultra High Speed (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, Multi-Chip Package (Multi-P Package) interface standard, multimedia Memory Card (Multi-Media) interface, flash Memory standard (MMC) interface, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In addition, in another embodiment, the connection interface circuit 230 may be packaged with the memory controller 210 in a chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210.

In the present embodiment, the host memory 120 is used for temporarily storing instructions or data executed by the processor 110. For example, in the present exemplary embodiment, the host Memory 120 may be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), and the like. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may be other suitable memories.

The memory controller 210 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 220 according to commands of the host system 10.

More specifically, the processor 211 in the memory controller 210 is computing hardware for controlling the overall operation of the memory controller 210. Specifically, the processor 211 has a plurality of control commands, and the control commands are executed to write, read and erase data when the memory device 20 is in operation.

It should be noted that, in the embodiment, the Processor 110 and the Processor 211 are, for example, a Central Processing Unit (CPU), a Microprocessor (micro-Processor), or other Programmable Processing Unit (Microprocessor), a Digital Signal Processor (DSP), a Programmable controller, an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), or other similar circuit elements, and the invention is not limited thereto.

In one embodiment, the memory controller 210 further has a read only memory (not shown) and a random access memory (not shown). In particular, the rom has a boot code (bootstrap code), and when the memory controller 210 is enabled, the processor 211 executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 220 into the ram of the memory controller 210. Then, the processor 211 operates the control commands to perform data writing, reading, and erasing operations. In another embodiment, the control instructions of the processor 211 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 220, for example, in a physical storage unit of the rewritable nonvolatile memory module 220 dedicated for storing system data.

In the present embodiment, as described above, the memory controller 210 further includes the data management circuit 212 and the memory interface control circuit 213. It should be noted that the operations performed by the components of the storage controller 210 may also be referred to as operations performed by the storage controller 210.

The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used for receiving an instruction from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written into the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation is performed according to a write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more memory cells of the one or more physical units), and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read command from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

The memory interface control circuit 213 is used to receive an instruction from the processor 211, and cooperate with the data management circuit 212 to perform a writing (also called Programming) operation, a reading operation or an erasing operation on the rewritable nonvolatile memory module 220.

For example, the processor 211 can execute a write command sequence to instruct the memory interface control circuit 213 to write data into the rewritable nonvolatile memory module 220; the processor 211 can execute a read instruction sequence to instruct the memory interface control circuit 213 to read data from one or more physical units (also called target physical units) of the corresponding read instruction of the rewritable nonvolatile memory module 220; the processor 211 can execute an erase command sequence to instruct the memory interface control circuit 213 to perform an erase operation on the rewritable nonvolatile memory module 220. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 220 to perform corresponding operations of writing, reading, and erasing. In one embodiment, the processor 211 may also issue other types of instruction sequences to the memory interface control circuit 213 to perform corresponding operations on the rewritable nonvolatile memory module 220.

In addition, the data to be written into the rewritable nonvolatile memory module 220 is converted into a format accepted by the rewritable nonvolatile memory module 220 through the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable nonvolatile memory module 220, the processor 211 transmits a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, the command sequences may include a write command sequence indicating to write data, a read command sequence indicating to read data, an erase command sequence indicating to erase data, and corresponding command sequences for indicating various memory operations (e.g., changing a plurality of preset read voltage values of a preset read voltage set for performing a read operation or a read assist operation, or performing a garbage collection procedure, etc.). The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

The rewritable nonvolatile memory module 220 is coupled to the memory controller 210 (the memory interface control circuit 213) and is used for storing data written by the host system 10. The rewritable nonvolatile memory module 220 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), a three-dimensional NAND flash memory module (3D NAND flash memory), or a Vertical NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), or other flash memory modules having the same characteristics. The memory cells in the rewritable nonvolatile memory module 220 are arranged in an array.

In the embodiment, the rewritable nonvolatile memory module 220 has a plurality of word lines, wherein each of the word lines is coupled to a plurality of memory cells. Multiple memory cells on the same word line constitute one or more physical programming units. In addition, a plurality of physical programming units can be combined into one physical unit (a physical block or a physical erasing unit). In the present embodiment, a Triple Level Cell (TLC) NAND flash memory module is taken as an example, i.e., in the following embodiments, a memory Cell capable of storing 3 bit values is taken as a Physical programming unit (i.e., in each programming operation, a programming voltage is applied to the Physical programming unit and then the Physical programming unit to program data), wherein each memory Cell can be divided into a Lower Physical Page (Lower Physical Page), a Middle Physical Page (Middle Physical Page), and an Upper Physical Page (Upper Physical Page) which can respectively store one bit value.

In this embodiment, the memory cell is used as the minimum unit for writing (programming) data. The physical cells are the minimum unit of erase, i.e., each physical cell contains the minimum number of memory cells that are erased together.

The following embodiments are examples of read assist operations (i.e., performing read assist operations on a plurality of memory cells of a specific word line) performed in a three-level flash memory module. The data reading method used in the read assist operation is also described below. However, the read assist operation and data reading method provided by the embodiments of the present invention can also be applied to other types of flash memory modules.

The memory controller 210 configures a plurality of logic units to the rewritable nonvolatile memory module 220. The host system 10 accesses the user data stored in the plurality of physical units through the configured logical unit. Here, each logical unit may be composed of one or more logical addresses. For example, a Logical unit may be a Logical block (Logical block), a Logical Page (Logical Page), or a Logical Sector (Logical Sector). A logical unit may be mapped to one or more physical units, where a physical unit may be one or more physical addresses, one or more physical sectors, one or more physical programming units, or one or more physical erasing units. In this embodiment, the logic units are logic blocks, and the logic sub-units are logic pages. Each logic unit has a plurality of logic sub-units.

In addition, the memory controller 210 establishes a Logical To Physical address mapping table (Logical To Physical address mapping table) and a Physical To Logical address mapping table (Physical To Logical address mapping table) To record an address mapping relationship between a Logical unit (e.g., a Logical block, a Logical page, or a Logical sector) and a Physical unit (e.g., a Physical erase unit, a Physical program unit, a Physical sector) allocated To the rewritable nonvolatile memory module 220. In other words, the memory controller 210 may look up the entity unit mapped by a logic unit through the logical-to-entity address mapping table, and the memory controller 210 may look up the logic unit mapped by an entity unit through the entity-to-logic address mapping table. However, the technical concepts related to the mapping of the logical units and the physical units are conventional technical means for those skilled in the art and are not the technical solutions to be described in the present invention, and are not described herein again.

In the present embodiment, the error checking and correcting circuit 214 is coupled to the processor 211 and is used for performing an error checking and correcting procedure to ensure the correctness of the data. Specifically, when the processor 211 receives a write command from the host system 10, the ECC and ECC circuit 214 generates an Error Correction Code (ECC) and/or an EDC (EDC) for data corresponding to the write command, and the processor 211 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 220. Thereafter, when the processor 211 reads data from the rewritable nonvolatile memory module 220, the corresponding error correction code and/or error check code is simultaneously read, and the error checking and correcting circuit 214 performs an error checking and correcting process on the read data according to the error correction code and/or error check code. In addition, after the error checking and correcting process, if the read data is successfully decoded, the error checking and correcting circuit 214 may return the number of error bits to the processor 211.

In the present embodiment, the error checking and correcting circuit 214 performs an iterative decoding operation (also referred to as an LDPC iterative decoding operation) using a Low Density Parity Code (LDPC) algorithm. Specifically, after receiving the codeword to be decoded (also referred to as a target codeword or an original codeword), the error checking and correcting circuit 214 starts an iterative decoding operation on the received codeword, identifies a plurality of data bits of the received codeword, queries a Log Likelihood Ratio (LLR) table (also referred to as an LLR table) according to the plurality of data bits to obtain a plurality of Log Likelihood Ratio values corresponding to the plurality of data bits, and performs a round of iterative decoding operation on the codeword through the Log Likelihood Ratio values and soft information corresponding to the codeword. The iterative decoding operation performed on the codeword via the log-likelihood ratio values and the soft information corresponding to the codeword may also be referred to as a soft decoding operation.

In this embodiment, each time the error checking and correcting circuit 214 completes one iteration of decoding operation performed on one of the codewords, the error checking and correcting circuit 214 may obtain the decoded codeword corresponding to the codeword and the syndrome corresponding to the decoded codeword. The error checking and correcting circuit 214 can determine whether the iterative decoding operation currently performed is decoding success or decoding failure according to the syndrome.

If the decoding fails, the error checking and correcting circuit 214 may determine whether to perform one or more subsequent iterative operations again according to the counted total number of iterative decoding operations performed on the codeword and a predetermined threshold value of iterative operations. If the total number is greater than the threshold number of iterations, the error checking and correcting circuit 214 determines that a predetermined decoding operation (the predetermined decoding operation may include one or more iterative decoding operations) of the codeword has failed, and outputs a decoded codeword obtained last and a corresponding syndrome; if the total number of times is not greater than the predetermined threshold value of iteration times, the error checking and correcting circuit 214 performs a new iteration decoding operation again by using the obtained decoded codeword and the corresponding syndrome. The manufacturer can set the threshold value of the iteration number according to the requirement, but the invention is not limited to this.

At the end of each (every) iteration of the decoding operation, the error checking and correcting circuit 214 calculates the syndrome corresponding to the decoded codeword that should be obtained last before to determine whether the iteration of the decoding operation is successful. If the decoding is successful (the generated code word after decoding is correct, namely, an effective code word), ending the iteration operation at this time and also ending the preset decoding operation of the code word; if the decoding fails (the codeword generated after decoding is an error, i.e., an invalid codeword), ending the current iteration operation and restarting a new iteration operation (next round) if the total number of times is not greater than the preset iteration time threshold value.

More specifically, during each iterative decoding operation, the error checking and correcting circuit 214 determines whether all of the bit values of the syndrome corresponding to the decoded codeword are zero. If the plurality of bit values of the syndrome are all zero (i.e., "0"), the error checking and correcting circuit 214 determines that the decoded codeword is correct, completes the iterative decoding operation of this time, completes the preset decoding operation corresponding to the codeword, and outputs the decoded codeword that is a valid codeword, thereby completing the reading operation corresponding to the original codeword.

Otherwise, if the bit values of the syndrome are not all zero (i.e., have one or more "1"), the error checking and correcting circuit 214 determines that the decoded codeword is erroneous, and ends the iterative decoding operation and the predetermined decoding operation of the codeword. In the present embodiment, the error checking and correcting circuit 214 further determines whether the total number of bit values "1" of the syndrome corresponding to the decoded codeword is smaller than the total number of bit values "1" of the syndrome obtained by the iterative decoding operation performed before. If so, the error checking and correcting circuit 214 identifies the decoded codeword as the minimum syndrome codeword, identifies the corresponding syndrome as the minimum syndrome, and outputs the minimum syndrome codeword and the minimum syndrome. The minimum syndrome codeword and the minimum syndrome may be stored to a corresponding buffer of a buffer memory.

It should be noted that the above description is only used to explain the corresponding relationship between the original codeword and the decoded codeword and the corresponding syndrome, and the details of the iterative decoding operation of the low density parity check code algorithm, the original codeword, the syndrome and the decoded codeword are not technical solutions of the present invention and are not described herein again.

In one embodiment, the memory controller 210 further includes a buffer memory 218 and a power management circuit 219. The buffer memory is coupled to the processor 211 and is used for temporarily storing data and instructions from the host system 10, data from the rewritable nonvolatile memory module 220, or other system data (e.g., log likelihood ratio table, confidence table) for managing the storage device 20, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 218. The power management circuit 219 is coupled to the processor 211 and is used for controlling the power of the storage device 20.

In the present embodiment, the read assist circuit unit 215 includes a soft information management circuit 2151 and a confidence table management circuit 2152. The read assist circuit unit 215 is used to perform read assist operations on a particular physical page of a plurality of word lines. More specifically, the processor 211 may select one of the word lines (also referred to as a target word line) belonging to the physical units of the rewritable nonvolatile memory module 220 at a specific time point, and instruct the read assist circuit unit 215 to perform a read assist operation on the target word line.

For example, the particular points in time include, but are not limited to: (1) when the decoding operation fails; (2) when the word line with a poor physical state (for example, the word line with a large number of erase times, a large number of read times, a long retention time (retention time) or a large number of error bits) is read; or (3) when the number of bits error of data read from a wordline exceeds a threshold number of bits error.

Specifically, when the number of bits of error of data read from a physical page corresponding to a wordline exceeds a threshold number of bits of error, the wordline is selected as the target wordline. It should be noted that the selected target word line has stored data, i.e., programmed data. In this embodiment, the stored data is not known data or verification data preset by a manufacturer or a system, for example, the stored data is user data.

In this embodiment, the soft information management circuit 2151 can perform a soft information operation on the target word line to obtain soft information of each of a plurality of target memory cells of the target word line. Before describing the operation of soft information, the concept of memory states is described. In the present embodiment, as described above, the target word line stores data. Specifically, the plurality of memory cells of each wordline may have one or more physical pages (each storing one bit value), and each memory cell is programmed to store a bit value corresponding to one of a plurality of different Gray Code (Gray Code) patterns, and the total number of the Gray Code patterns is P, wherein the total number of the bit values stored in each of the Gray Code patterns is equal to the total number of the physical pages of each memory cell. P is a first predetermined positive integer greater than 2, and the value of P is predetermined according to the type of the rewritable nonvolatile memory module 220. For example, if the rewritable nonvolatile memory module 220 is an MLC, P is 4, and the total number of bit values stored in each gray code pattern is equal to 2; if the rewritable nonvolatile memory module 220 is SLC, P is 2, and the total number of bit values stored in each gray code pattern is equal to 1; if the rewritable nonvolatile memory module 220 is QLC, P is 16, and the total number of bit values stored in each gray code pattern is equal to 4.

For the sake of uniform description, the embodiment is exemplified by a three-level flash memory module, and a plurality of memory cells of the target word line can store bit values corresponding to 8 gray code patterns (P ═ 8), and the total number of bit values stored in each of the gray code patterns is equal to 3. The following first describes details of the plurality of Golay code patterns with reference to FIG. 3A.

FIG. 3A is a diagram illustrating a threshold voltage distribution and corresponding Gray code patterns of a first read voltage pattern 1/2/4 according to one embodiment of the invention. Since the exemplary embodiment is described with reference to the rewritable non-volatile memory module 220 being a three-level cell NAND flash memory module, where P is equal to 8 (i.e., 2)³). Each memory cell of the three-rank memory cell NAND type flash memory module has three Physical pages for respectively storing bit data, and each memory cell includes a Lower Physical Page (L), a Middle Physical Page (M), and an Upper Physical Page (U) that can respectively store one bit value. Assume that processor 211 converts the read voltages V (i) through a predetermined set of read voltages V (i)₁～V(i)₇Reading a plurality of memory cells (target memory cells) of a target word line of a three-level cell NAND type flash memory module, and thereby identifying different bit values (ratios respectively corresponding to different Gray code patterns) stored in the plurality of memory cellsA special value). The gate voltage of each memory cell can be read according to the converted read voltage V (i) in the preset read voltage set V (i)₁～V(i)₇The 8 Gray code patterns are distinguished, such as 8 Gray code patterns of L:1M:1U:1, L:1M:1U:0, L:1M:0U:1, L:0M:0U:0, L:0M:1U:0, and L:0M:1U:1 (L: ' indicates the bit value of the lower entity page, M: ' indicates the bit value of the middle entity page, and U: ' indicates the bit value of the upper entity page). The 8 gray code patterns can also be expressed as "111", "110", "100", "101", "001", "000", "010" and "011", 8 bit value combinations, wherein the bit values in each bit value combination are ordered according to the sequence of the lower, middle and upper physical pages. That is, by applying the read voltages V (i) of different voltage values of the read voltage group V (i)₁～V(i)₇To a memory cell of the target word line, the processor 211 may respectively determine that the bit value (also referred to as bit data or read bit value) stored in the memory cell corresponds to one of a plurality of different gray code patterns ("111", "110", "100", "101", "001", "000", "010", and "011") according to whether the channel of the memory cell is turned on (i.e., the read bit value is read from a memory cell of the target word line by using the preset read voltage group v (i)).

In the present embodiment, the threshold voltage distribution of the word line can be divided into a plurality of threshold voltage distribution regions according to the corresponding converted read voltages. The threshold voltage distribution areas and the Gray code patterns are in one-to-one mapping relation. Referring to fig. 3A, the threshold voltage distribution region G1 corresponds to the gray code pattern "111"; the threshold voltage distribution region G2 corresponds to the Gray code pattern "110"; the threshold voltage distribution region G3 corresponds to the gray code pattern "100"; the threshold voltage distribution region G4 corresponds to the gray code pattern "101"; the threshold voltage distribution region G5 corresponds to the Gray code pattern "001"; the threshold voltage distribution region G6 corresponds to the Gray code pattern "000"; the threshold voltage distribution region G7 corresponds to the gray code pattern "010"; the threshold voltage distribution region G8 corresponds to the Gray code pattern "011". In addition, in the embodiment, if the storage state of a memory cell corresponds to the gray code pattern of "011", the memory cell can be considered to belong to the threshold voltage distribution region G8, or the threshold voltage distribution of the memory cell can be considered to belong to the threshold voltage distribution region G8.

It should be noted that, according to a total number of the plurality of gray code patterns that the memory cells of the rewritable non-volatile memory module 220 can have (in this example, 8), the processor 211 may determine a total number of the plurality of converted read voltages of the preset read voltage set, wherein the total number of the plurality of converted read voltages of the preset read voltage set is equal to the total number of the plurality of gray code patterns minus one (in this example, 7, i.e., P-1-8-1-7). In addition, the total number of the plurality of threshold voltage distribution regions is also equal to the total number of the plurality of Golay patterns.

In more detail, the storage state (also called "gray code") corresponding to a gray code pattern stored in a storage unit may be sequentially combined by the storage State (SL) of the lower physical page, the storage State (SM) of the lower physical page, and the storage State (SU) of the upper physical page of the storage unit (as shown by the arrows in fig. 3A).

In the present embodiment, the read voltage V (i) is converted₄A storage state SL1 ("1") to distinguish the lower physical page from SL2 ("0"); converting read Voltage V (i)₂And V (i)₆Memory states SM1 ("1"), SM2 ("0"), and SM3 ("1") to distinguish the middle entity pages; converting read Voltage V (i)₁、V(i)₃、V(i)₅、V(i)₇The storage states SU1 ("1"), SU2 ("0"), SU3 ("1"), SU4 ("0"), and SU5 ("1") to distinguish the upper entity page.

The processor 211 (or the read assist circuit unit 215) may sequentially read the word lines by using the converted read voltages corresponding to the lower physical page, the middle physical page, and the upper physical page in the preset read voltage set, so as to obtain the storage states of the lower physical page, the middle physical page, and the upper physical page of the plurality of memory cells of the word lines, and further obtain the gray codes of the plurality of memory cells. For example, assume that the processor 211 (or the read assist circuit unit 215) reads a word line using a set of preset read voltages v (i) to obtain a plurality of gray codes of a plurality of memory cells of the word line. The processor 211 (or the read assist circuit unit 215) first uses the converted read voltage V (i)₄To identify whether the memory state of the lower physical page of all the memory cells is the memory state SL1 or the memory state SL 2; next, the processor 211 (or the read assist circuit unit 215) further uses the converted read voltage V (i)₂、V(i)₆To identify whether the storage state of the middle physical page of such memory cells is storage state SM1, storage state SM3, or storage state SM 3; next, the processor 211 (or the read assist circuit unit 215) further uses the converted read voltage V (i)₁、V(i)₃、V(i)₅、V(i)₇The storage state to identify the upper physical page of such storage units is storage state SU1, storage state SU2, storage state SU3, storage state SU4, or storage state SM 5. In this way, the processor 211 (or the read assist circuit unit 215) can identify the lower real of all the memory cellsAnd identifying the storage states of the body page, the middle entity page and the upper entity page so as to identify the Golay codes stored in all the storage units.

It should be noted that the identified bit values of the storage states of the upper physical pages of all the memory cells of the wordline can be combined together into one hard bit codeword corresponding to the upper physical page of the wordline; the identified bit values of the storage states of the middle entity pages of all the storage units of the word line can be combined together into one hard bit code word corresponding to the middle entity page of the word line; the identified bit values of the storage states of the lower physical page of all the memory cells of the wordline may be combined together into one hard bit codeword corresponding to the lower physical page of the wordline. The hard bit code words respectively corresponding to the entity pages have not been subjected to a predetermined decoding operation, and may also be referred to as original code words respectively corresponding to the entity pages.

In addition, the rewritable nonvolatile memory module 220 with the above characteristics of multiple physical pages and the corresponding number of converted read voltages can also be regarded as a rewritable nonvolatile memory module 220 (three-level cell NAND-type flash memory module) with the first read voltage pattern (1/2/4). The "1/2/4" corresponds to the total number of converted read voltages that the "lower/middle/upper physical pages" have, respectively. The present invention is not limited to the rewritable nonvolatile memory module 220 with the first read voltage pattern, and the data reading method, the memory controller and the memory device provided by the present invention can also be applied to the rewritable nonvolatile memory module 220 with other read voltage patterns. This will be described below with reference to fig. 3B.

FIG. 3B is a diagram illustrating a threshold voltage distribution and a corresponding Gray code pattern of a second read voltage pattern 2/3/2 according to one embodiment of the invention. Referring to FIG. 3B, the second read voltage pattern (2/3/2) is applied to the rewritable nonvolatile memory module 220 (three-level cell NAND flash memory module), read voltage V (i)₁And V (i)₅Memory state for distinguishing lower entity pageSL1 ("1"), SL2 ("0"), and SL3 ("1"); read Voltage V (i)₂、V(i)₄And V (i)₆Memory states SM1 ("1"), SM2 ("0"), SM3 ("1"), and SM4 ("0") to distinguish the middle entity pages; read Voltage V (i)₃And V (i)₇The memory states SU1 ("1"), SU2 ("0"), and SU3 ("1") to distinguish the upper entity page. The "2/3/2" corresponds to the total number of converted read voltages that the "lower/middle/upper physical pages" have, respectively.

The gate voltage of each memory cell of the rewritable non-volatile memory module 220 of the second read voltage pattern (2/3/2) is based on the converted read voltage V (i) of the predetermined read voltage group V (i)₁～V(i)₇The method can be divided into 8 Gray code patterns, such as 8 Gray code patterns of "L: 1M:1U: 1", "L: 0M:0U: 0", "L: 0M:1U: 0", "L: 1M:0U: 0" and "L: 1M:0U: 1". The 8 gray code patterns can also be expressed as "111", "110", "100", "101", "001", "000", "010" and "011", 8 bit value combinations, wherein the bit values in each bit value combination are ordered according to the storage states of the lower, middle and upper physical pages of the memory cell.

In addition, referring to fig. 3B, the threshold voltage distribution region G1 corresponds to the gray code pattern "111"; the threshold voltage distribution region G2 corresponds to the Gray code pattern "011"; the threshold voltage distribution region G3 corresponds to the Gray code pattern "001"; the threshold voltage distribution region G4 corresponds to the Gray code pattern "000"; the threshold voltage distribution region G5 corresponds to the gray code pattern "010"; the threshold voltage distribution region G6 corresponds to the Gray code pattern "110"; the threshold voltage distribution region G7 corresponds to the gray code pattern "100"; the threshold voltage distribution region G8 corresponds to the gray code pattern "101". In addition, in the embodiment, if the storage state of a memory cell corresponds to the gray code pattern of "011", the memory cell can be considered to belong to the threshold voltage distribution region G8, or the threshold voltage distribution of the memory cell can be considered to belong to the threshold voltage distribution region G2.

In the present embodiment, the threshold voltage distribution of the physical page of the memory cells of the word line may be shifted from the predetermined threshold voltage distribution. Due to the shift of the threshold voltage distribution, the predetermined converted read voltage originally corresponding to the predetermined threshold voltages of the plurality of physical pages is no longer suitable for distinguishing the storage states of the corresponding physical pages. In other words, in this case, the read bit values stored in the plurality of memory cells of the originally read and identified physical page are distorted. At this time, it is necessary to perform a soft information operation to obtain soft information corresponding to the plurality of memory cells, so as to assist the processor 211 or the error checking and correcting circuit 214 to further identify the read bit values or corresponding degrees of confidence stored in the plurality of physical pages of the plurality of memory cells through the soft information and corresponding confidence tables of the plurality of memory cells. Thus, the error checking and correcting circuit 214 can perform a predetermined decoding operation (LDPC decoding operation) according to the confidence and soft information of each memory cell. The following description will be made with reference to fig. 2.

Fig. 2 is a flowchart illustrating a data reading method according to an embodiment of the invention. Referring to fig. 2, in step S21, the processor 211 selects a target word line to perform a read operation on the target word line. Specifically, the selection and timing of the target word line have been described in detail above, and are not described herein again. However, in another embodiment, the target word line may also refer to the word line corresponding to the read data indicated by the read command.

Next, in step S22, the read assist circuit unit 215 (or the soft information management circuit 2151) reads a plurality of target physical pages of the target word line using the preset read voltage set to obtain a plurality of hard bit code words respectively corresponding to the plurality of target physical pages.

Specifically, a plurality of read bit values read for a plurality of target memory cells belonging to the same target physical page by using the corresponding converted read voltages in the preset read voltage group constitute a hard bit codeword corresponding to the target physical page. For example, in the example of FIG. 3A, the target wordline would have three target physical pages (upper, middle, and lower physical pages). The lower physical pages of all target memory cells of the target word line are read by using the converted read voltage v (i)4, and the hard bit code words of the corresponding lower physical pages of the target word line are obtained.

Next, in step S22, the read assist circuit unit 215 (or the soft information management circuit 2151) generates respective soft information for a plurality of target memory cells of the target word line based on the plurality of hard bit codewords.

Specifically, in the present embodiment, the soft information may include three aspects: the first state soft information, the second state soft information and the third state soft information. The processor 211 may preset the state of the soft information to be one of the three.

In more detail, in response to the soft information being preset as the first-mode soft information, the step of generating the soft information of each of the target memory cells of the target word line according to the hard bit code words comprises: performing a predetermined decoding operation on the hard bit code words via the error checking and correcting circuit 214 to obtain the minimum syndrome code words respectively corresponding to the hard bit code words; and composing, via soft information management circuit 2151, a plurality of soft information for the plurality of target storage units from the plurality of minimum syndrome codewords for the plurality of target storage units that respectively correspond to the plurality of target entity pages. The syndromes corresponding to the minimum syndrome codeword may have a total number of bit values of "1" greater than or equal to 0. The valid codeword can also be considered a minimum syndrome codeword.

That is, for a first predetermined decoding operation performed on a first hard bit codeword of the plurality of hard bit codewords (the first predetermined decoding operation comprising a plurality of iterative decoding operations), the error checking and correction circuit obtains a decoded hard bit codeword and a hard bit syndrome corresponding to the decoded hard bit codeword each time one of the plurality of iterative decoding operations is completed. The error checking and correcting circuit 214 selects a minimum one of the plurality of hard bit syndromes obtained from the completed plurality of iterative decoding operations as a minimum hard bit syndrome and identifies a decoded hard bit codeword corresponding to the minimum hard bit syndrome from a plurality of decoded hard bit codewords as a minimum syndrome codeword, wherein a total number of the plurality of iterative decoding operations is less than or equal to an iteration number threshold.

In other words, after the preset decoding operation performed on the hard bit code word of the lower physical page is completed, the error checking and correcting circuit 214 can obtain the minimum syndrome code word corresponding to the lower physical page; after the preset decoding operation performed on the hard bit code word of the middle entity page is completed, the error checking and correcting circuit 214 may obtain the minimum syndrome code word of the corresponding middle entity page; after the predetermined decoding operation performed on the hard bit code word of the upper physical page is completed, the error checking and correcting circuit 214 may obtain the minimum syndrome code word corresponding to the upper physical page.

Then, for a certain memory cell, the soft information management circuit 2151 may identify a read bit value of the lower entity page of the memory cell from the minimum syndrome codeword corresponding to the lower entity page, and identify the read bit value as a soft bit of the soft information of the memory cell corresponding to the lower entity page; identifying a read bit value of the middle entity page of the memory cell in the minimum syndrome codeword of the corresponding middle entity page, and identifying the read bit value as a soft bit of the corresponding middle entity page of the soft information of the memory cell; the read bit value of the upper physical page of the memory cell is identified in the minimum syndrome codeword of the corresponding upper physical page, and the read bit value is identified as the soft bit of the corresponding upper physical page of the soft information of the memory cell.

It should be noted that, in this embodiment, each target entity page of one target storage unit corresponds to one soft bit of the soft information of the one target storage unit, and the total number of all soft bits of the soft information of the one target storage unit is equal to the total number of all target entity pages of the one target storage unit. For example, for one memory cell of a three-level memory cell NAND-type flash memory module, the memory cell has upper, middle and lower physical pages, and the total number of the upper, middle and lower physical pages is 3. Therefore, the soft information of one memory cell of the three-level memory cell NAND type flash memory module has 3 bit values, and each bit value of the memory cell corresponds to the upper, middle and lower physical pages respectively.

On the other hand, in response to the soft information being preset as the second-aspect soft information, the generating the soft information of each of the target memory cells of the target word line according to the hard bit code words comprises: directly combining the plurality of hard bit code words respectively corresponding to the target entity pages into the plurality of soft information of the plurality of target storage units. Specifically, if the soft information is the second-mode soft information, for a certain memory cell, the soft information management circuit 2151 may identify a read bit value (also referred to as a hard bit value) of the lower physical page of the memory cell from the hard bit code word corresponding to the lower physical page, and identify the read bit value as a soft bit of the corresponding lower physical page of the soft information of the memory cell; identifying a read bit value of the middle entity page of the memory cell in the hard bit code word of the corresponding middle entity page, and identifying the read bit value as a soft bit of the corresponding middle entity page of the soft information of the memory cell; read bit values of the upper physical page of the memory cell are identified at the hard bit code word of the corresponding upper physical page, and the read bit values are identified as soft bits of the corresponding upper physical page of the soft information of the memory cell. Next, soft information management circuit 2151 may combine the plurality of soft bits into soft information for the memory cell.

In another aspect, in response to the soft information being preset as the third bit-like soft information, the generating the soft information for each of the target memory cells of the target word line according to the hard bit code words comprises: soft information management circuit 2151 selects one of the plurality of hard bit codewords, instructs error checking and correction circuit 214 to perform the preset decoding operation on the selected hard bit codeword to obtain a minimum syndrome codeword corresponding to the selected hard bit codeword; and composing a plurality of soft information of the plurality of target storage units according to the minimum syndrome codeword of the selected hard bit codeword and all other hard bit codewords of the plurality of hard bit codewords which are not selected. In other words, for the third parity bit information, the soft information of a target memory cell at least comprises a bit value from the syndrome codeword and a bit value from the hard bit codeword. In an embodiment, the selected minimum syndrome codeword may be a valid codeword. In one embodiment, the number of error bits of the selected minimum syndrome codeword may be greater than a threshold number of error bits. In an embodiment, the total number of the selected smallest syndrome codewords may be greater than one.

After obtaining the soft information of each of the target storage units, in step S24, the read assist circuit unit 215 (or the confidence table management circuit 2152) may identify a plurality of confidence levels of each of the target storage units corresponding to the target entity pages according to a plurality of confidence tables respectively corresponding to the target entity pages and a plurality of soft information of each of the target storage units.

The following describes the setting rule of the confidence table with reference to fig. 4A and 5A.

In this embodiment, the confidence table of one target entity page includes a plurality of confidence levels respectively corresponding to a plurality of threshold voltage distribution regions. The absolute values of the predetermined confidences corresponding to the threshold voltage distribution regions in the confidence table (e.g., the first confidence table) of a target physical page (e.g., the first target physical page) are set by the read assist circuit unit 215 (or the confidence table management circuit 2152) according to the voltage relationships between the converted read voltage (also referred to as the first converted read voltage) corresponding to the first target physical page in the predetermined read voltage group and the threshold voltage distribution regions, wherein the absolute values of the predetermined confidences corresponding to one or more threshold voltage distributions closer to the first converted read voltage in the threshold voltage distribution regions are smaller.

The positive or negative of the preset confidence levels are set by the reading auxiliary circuit unit according to the bit value of the first target entity page in the plurality of bit values of the gray code pattern corresponding to the plurality of threshold voltage distribution areas, wherein the bit value corresponding to the first target entity page in the plurality of bit values of the gray code pattern corresponding to one threshold voltage distribution region (e.g., the first threshold voltage distribution region) is "1", the first predetermined confidence level corresponding to the first threshold voltage distribution region is set to a negative value by the read assist circuit unit, wherein the bit value corresponding to the first target entity page among the plurality of bit values in response to the gray code pattern corresponding to the first threshold voltage distribution area is "0", the first predetermined confidence corresponding to the first threshold voltage distribution region is set to a positive value by the read assist circuit unit.

FIG. 4A is a diagram illustrating a confidence table for setting the first read voltage pattern (1/2/4), according to one embodiment of the invention.

Referring to fig. 4A, for example, assume that the confidence table managing circuit 2152 sets the confidence table 410 of the lower entity page. The confidence table 410 includes predetermined confidence levels 410(1) to 410(8) respectively corresponding to the threshold voltage distribution regions G1 to G8. First, the confidence table managing circuit 2152 recognizes the read voltage V (i) of the next physical page conversion₄According to the threshold voltage distribution regions G1-G8 and the converted read voltages V (i)₄The threshold voltage distribution regions G1-G8 are sorted from small to large (the smaller the voltage difference between the threshold voltage distribution region and the transition read voltage, the closer the threshold voltage distribution region is to the transition read voltage). Next, the confidence table managing circuit 2152 converts the corresponding closest reading voltage V (i) in the confidence table 410₄The absolute values of the predetermined confidences 410(4), 410(5) of the threshold voltage distribution regions G4, G5 are set to "a"; setting the absolute values of the predetermined confidences 410(3), 410(6) of the threshold voltage distribution regions G3 and G6 as "B"; pre-treating the critical voltage distribution regions G2, G7The absolute value of confidence 410(2), 410(7) is set as "C"; the absolute values of the predetermined confidences 410(1), 410(8) of the threshold voltage distribution regions G1, G8 are set to "D". The terms "A", "B", "C" and "D" are intended to mean four different values, where | A<|B|<|C|<L D l. That is, since the read bit value stored in the memory cell closer to the converted read voltage has a higher probability of being misjudged, the confidence of the threshold voltage distribution region closest to the converted read voltage is the smallest, and the confidence of the threshold voltage distribution region farthest from the converted read voltage is the largest.

Next, the confidence table managing circuit 2152 identifies that the bit value of the lower physical page of the gray code pattern corresponding to the threshold voltage distribution areas G1, G2, G3, and G4 is "1", and sets the predetermined confidence levels 410(1), (410), (2), (410), (3), (410), (4) corresponding to the threshold voltage distribution areas G1, G2, G3, and G4 to negative values, respectively. That is, the predetermined confidence levels 410(1), 410(2), 410(3), 410(4) corresponding to the threshold voltage distribution regions G1, G2, G3, G4 are finally set to "-D", "-C", "-B", "-a".

Conversely, the confidence table managing circuit 2152 recognizes that the bit value of the lower physical page of the gray code pattern corresponding to the threshold voltage distribution areas G5, G6, G7, and G8 is "0", and correspondingly sets the predetermined confidence levels 410(5), (6), (7), (410), (8) corresponding to the threshold voltage distribution areas G5, G6, G7, and G8 to positive values. That is, the predetermined confidence levels 410(5), (410), (6), (410), (7), (410), (8) corresponding to the threshold voltage distribution regions G5, G6, G7, G8 are finally set to "+ a", "+ B", "+ C", "+ D".

By analogy, the predetermined confidence levels 420(1) to 420(8) of the corresponding threshold voltage distribution regions G1 to G8 of the confidence table 420 of the corresponding middle entity page of the first read voltage pattern are set to "-B", "-a", "+ B", "+ a", "-" B "; the predetermined confidence levels 430(1) to 430(8) of the corresponding threshold voltage distribution regions G1 to G8 of the confidence table 430 of the corresponding upper entity page of the first read voltage pattern are set to "-A", "+ A", "-A".

FIG. 5A is a diagram illustrating a confidence table for setting a second read voltage pattern (2/3/2) according to one embodiment of the invention. Referring to FIG. 5A, similarly, the predetermined confidence levels 510(1) to 510(8) of the corresponding threshold voltage distribution areas G1-G8 of the confidence table 510 of the corresponding lower entity page of the second read voltage pattern are set to "-A", "+ B", "+ A", "-" B "," - "C"; the predetermined confidence levels 520(1) to 520(8) of the threshold voltage distribution regions G1 to G8 of the confidence table 520 of the corresponding middle entity page of the second read voltage pattern are set to "-B", "-A", "+ B"; the predetermined confidence 530(1) to 530(8) of the corresponding threshold voltage distribution regions G1 to G8 of the confidence table 530 corresponding to the upper physical page of the second read voltage pattern is set to "-C", "-B", "-A", "+ B", "+ A", "-A". The confidence table managing circuit 2152 may store a plurality of set confidence tables.

FIG. 4B is a diagram illustrating a confidence table corresponding to a first read voltage pattern (1/2/4), according to one embodiment of the invention. FIG. 5B is a diagram illustrating a confidence table corresponding to a second read voltage pattern 2/3/2 according to an embodiment of the invention.

In detail, step S24 may include the following steps: for a first confidence table corresponding to a first target entity page of the target entity pages and first soft information of a first target storage unit of the target storage units, identifying a first critical voltage distribution area to which the first target storage unit belongs in the critical voltage distribution areas according to the first soft information; searching a first preset confidence corresponding to the first critical voltage distribution region from the first confidence table according to the first critical voltage distribution region; and identifying the first preset confidence as the first confidence corresponding to the first target entity page in the plurality of confidence of the first target storage unit.

Referring to fig. 4B, for example, assume that a is 2; b is 4; c ═ 6; d ═ 8. A plurality of confidence tables 410-430 of the set first read voltage pattern are shown in FIG. 4B. If the soft information of the first target memory cell is "111", the confidence table managing circuit 2152 may identify that the first target memory cell belongs to the threshold voltage distribution region G1, and find out the confidence level of the corresponding lower physical page of the first target memory cell as "-8" from the confidence table 410 of the corresponding lower physical page; finding out the confidence degree of the corresponding middle entity page of the first target storage unit as '-4' from the confidence table 420 of the corresponding middle entity page; the confidence level of the corresponding upper physical page of the first target storage unit is found to be "-2" from the confidence table 430 of the corresponding upper physical page.

For another example, referring to fig. 5B, assume that a is 2; b is 4; and C is 6. A plurality of confidence tables 510-530 of the set second read voltage pattern are shown in FIG. 5B. If the soft information of the first target memory cell is "010", the confidence table managing circuit 2152 may identify that the first target memory cell belongs to the threshold voltage distribution region G5, and find out that the confidence level of the corresponding lower physical page of the first target memory cell is "+ 2" from the confidence table 510 of the corresponding lower physical page; finding out the confidence degree of the corresponding middle entity page of the first target storage unit as '-2' from the confidence table 520 of the corresponding middle entity page; the confidence level of the corresponding upper physical page of the first target memory location is found to be "+ 4" from the confidence table 530 of the corresponding upper physical page.

Referring back to fig. 2, after the confidences of the target memory cells corresponding to the target entity pages are identified, in step S25, the confidence of the target memory cells is substituted for log-likelihood ratios of the target memory cells in the predetermined iterative decoding operation by the error checking and correcting circuit 214, and the adjusted predetermined iterative decoding operation with the substituted log-likelihood ratios is performed on the soft information to obtain final decoded codewords corresponding to the target entity pages, so as to complete the reading operation.

Specifically, the default decoding operation corresponding to the target word line is to perform a plurality of iterative decoding operations according to a plurality of log likelihood ratios corresponding to the target memory cells and the original soft information corresponding to the target memory cells. The original soft information is not identical to the soft information generated in step S23. The original soft information is obtained via a plurality of auxiliary read voltage sets corresponding to a plurality of converted read voltages, wherein one auxiliary read voltage set corresponding to one converted read voltage has a pair of two auxiliary read voltages, one of which is smaller than the converted read voltage by a voltage deviation value and the other of which is larger than the converted read voltage by a voltage deviation value.

However, in step S25, the error checking and correcting circuit 214 replaces the log-likelihood ratios of the target memory cells with the confidence levels of the target memory cells, replaces the soft information of the target memory cells generated in step S23 with the original soft information, and re-performs the predetermined decoding operation (also called adjusted predetermined decoding operation) on the soft information of the target memory cells. After the adjusted default decoding operation is completed, the error checking and correcting circuit 214 may obtain a final decoded codeword (valid codeword), and complete the read operation corresponding to the target word line.

It should be noted that, in the above embodiments, the read assist circuit unit 215 is implemented by a hardware circuit, but the invention is not limited thereto. For example, in one embodiment, the read assist circuit unit 215 may be implemented in software as a read assist code module having the functionality of the read assist circuit unit 215. The read assist code module may include a soft information management code module and a confidence table management code module. The soft information management program code module is a program code module with the function of the soft information management circuit 2151; the credit table management program code module is a program code module having the function of the credit table management circuit 2152. The processor 211 can access and execute the reading assistance code module (or the soft information management code module and the confidence table management code module) to implement the data reading method (or the reading assistance method) provided by the present invention.

In summary, the data reading method, the memory controller and the memory device provided in the embodiments of the invention can obtain a plurality of hard bit code words by reading a plurality of target physical pages of a target word line without preparing verified data, and generate respective soft information of a plurality of target memory cells of the target word line by using the plurality of hard bit code words. Then, the data reading method, the memory controller and the memory device provided in the embodiments of the present invention may further obtain the confidence levels of the target memory cells corresponding to the target entity pages by searching the confidence tables corresponding to the target entity pages using the soft information, and further perform the adjusted iterative decoding operation according to the confidence levels of the target memory cells corresponding to the target entity pages, so as to enhance the decoding capability and improve the efficiency of the reading operation. Therefore, the correctness and the reliability of the data read from the target word line can be improved, the load of the decoding operation performed on the read data is reduced, and the overall efficiency of the data reading operation is improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A data reading method applied to a storage device configured with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of word lines, each of the plurality of word lines is coupled to a plurality of memory cells, each of the plurality of memory cells includes a plurality of physical pages, and each of the plurality of physical pages is programmed to a bit value, the method comprising:

selecting a target word line to perform a read operation on the target word line;

reading a plurality of target entity pages of the target word line by using a preset reading voltage group to obtain a plurality of hard bit code words respectively corresponding to the target entity pages;

generating respective soft information for a plurality of target memory cells of the target word line based on the plurality of hard bit codewords;

identifying a plurality of confidence levels of the target storage units corresponding to the target entity pages respectively according to a plurality of confidence tables respectively corresponding to the target entity pages and a plurality of soft information of the target storage units, wherein the plurality of confidence tables respectively have a plurality of preset confidence levels respectively corresponding to a plurality of threshold voltage distribution areas, and the plurality of threshold voltage distribution areas correspond to a plurality of Golay code patterns; and

replacing the plurality of confidence degrees of the plurality of target storage units with a plurality of log-likelihood ratio values corresponding to the plurality of target storage units in the preset decoding operation, and performing an adjusted preset decoding operation with the replaced plurality of log-likelihood ratio values on the plurality of soft information to obtain a plurality of final decoded codewords respectively corresponding to the plurality of target entity pages, and completing the reading operation.

2. A method of data reading according to claim 1, wherein the preset decoding operation comprises a plurality of iterative decoding operations applying a low density parity check algorithm.

3. A data reading method according to claim 1, wherein the soft information is preset as first-like soft information, second-like soft information or third-like soft information, wherein

In response to the soft information being preset as the first-mode soft information, the generating the soft information for each of the target memory cells of the target word line according to the hard bit codewords comprises:

performing a preset decoding operation on the plurality of hard bit code words respectively to obtain a plurality of minimum syndrome code words respectively corresponding to the plurality of hard bit code words; and

composing a plurality of soft information of the plurality of target storage units according to the plurality of minimum syndrome codewords of the plurality of target storage units respectively corresponding to the plurality of target entity pages,

wherein, in response to the soft information being preset as the second-aspect soft information, the generating the soft information for each of the target memory cells of the target word line according to the hard bit codewords comprises:

directly combining the plurality of hard bit code words respectively corresponding to the target entity page into the plurality of soft information of the plurality of target storage units;

wherein, in response to the soft information being preset as the third bit-like soft information, the step of generating the soft information for each of the target memory cells of the target word line according to the hard bit codewords comprises:

selecting one of the hard bit code words to execute the preset decoding operation so as to obtain a minimum syndrome code word corresponding to the selected hard bit code word; and

forming a plurality of soft information of the plurality of target storage units according to the minimum syndrome codeword of the selected hard bit codeword and all other hard bit codewords of the plurality of hard bit codewords which are not selected.

4. A data reading method according to claim 3, wherein the step of performing the preset decoding operation on the plurality of hard bit code words respectively to obtain the plurality of minimum syndrome code words corresponding to the plurality of hard bit code words respectively comprises:

for a first pre-set decoding operation performed on a first hard bit codeword of the plurality of hard bit codewords, the first pre-set decoding operation comprising a plurality of iterative decoding operations,

obtaining a decoded hard bit codeword and a hard bit syndrome corresponding to the decoded hard bit codeword each time one of the plurality of iterative decoding operations is completed; and

selecting a smallest one of a plurality of hard bit syndromes as a smallest hard bit syndrome, and identifying a decoded hard bit codeword corresponding to the smallest hard bit syndrome from a plurality of decoded hard bit codewords as a smallest syndrome codeword, wherein a total number of the plurality of iterative decoding operations is less than or equal to an iteration number threshold value.

5. A data reading method according to claim 4, wherein each target entity page of one target storage unit corresponds to one soft bit of the soft information of the one target storage unit, and the total number of all soft bits of the soft information of the one target storage unit is equal to the total number of all target entity pages of the one target storage unit.

6. A data reading method according to claim 1, wherein the step of identifying the plurality of degrees of confidence that the plurality of target storage units respectively correspond to the plurality of target entity pages according to the plurality of confidence tables respectively corresponding to the plurality of target entity pages and the plurality of soft information of the plurality of target storage units comprises:

for a first confidence table corresponding to a first target entity page of the plurality of target entity pages and first soft information for a first target storage unit of the plurality of target storage units,

identifying a first threshold voltage distribution region to which the first target memory cell belongs among the plurality of threshold voltage distribution regions according to the first soft information;

searching a first preset confidence corresponding to the first critical voltage distribution region from the first confidence table according to the first critical voltage distribution region;

and identifying the first preset confidence as the first confidence corresponding to the first target entity page in the plurality of confidence of the first target storage unit.

7. The data reading method according to claim 6, wherein the absolute value of the predetermined confidence levels corresponding to the threshold voltage distribution regions in the first confidence table of the first target physical page is set according to the voltage relationships between the first converted read voltage corresponding to the first target physical page and the threshold voltage distribution regions in the predetermined read voltage group,

wherein the absolute value of one or more predetermined confidences corresponding to one or more threshold voltage distributions closer to the first converted read voltage in the plurality of threshold voltage distribution regions is smaller,

wherein the predetermined confidence levels are set according to a bit value of the first target entity page in the plurality of bit values of the gray code pattern corresponding to the threshold voltage distribution regions,

wherein the bit value corresponding to the first target physical page is "1" in a plurality of bit values in response to the gray code pattern corresponding to the first threshold voltage distribution region, the first predetermined confidence corresponding to the first threshold voltage distribution region is set to a negative value,

wherein the bit value corresponding to the first target entity page among the plurality of bit values corresponding to the gray code pattern corresponding to the first threshold voltage distribution region is "0", and the first predetermined confidence corresponding to the first threshold voltage distribution region is set to a positive value.

8. A memory controller for controlling a memory device configured with a rewritable non-volatile memory module, the memory controller comprising:

a connection interface circuit for coupling to a host system;

a memory interface control circuit coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of word lines, each of the plurality of word lines is coupled to a plurality of memory cells, each of the plurality of memory cells includes a plurality of physical pages, and each of the plurality of physical pages is programmed to a bit value;

a read assist circuit unit;

an error checking and correcting circuit; and

a processor coupled to the connection interface circuit, the memory interface control circuit, the read assist circuit unit, and the error checking and correcting circuit,

wherein the processor is configured to select a target word line of the plurality of word lines of the rewritable non-volatile memory module to perform a read operation on the target word line,

wherein the read assist circuit unit is configured to read a plurality of target physical pages of the target word line using a preset set of read voltages to obtain a plurality of hard bit codewords corresponding to the plurality of target physical pages, respectively,

wherein the read assist circuit unit is further configured to generate respective soft information for a plurality of target memory cells of the target word line based on the plurality of hard bit codewords,

wherein the read assist circuit unit is further configured to identify a plurality of confidence levels of the target memory cells corresponding to the target physical pages according to a plurality of confidence tables corresponding to the target physical pages and a plurality of soft information of the target memory cells, wherein the plurality of confidence tables each have a plurality of predetermined confidence levels corresponding to a plurality of threshold voltage distribution regions corresponding to a plurality of Gray code patterns,

the error checking and correcting circuit is configured to replace the plurality of confidence levels of the plurality of target memory cells with a plurality of log-likelihood ratios corresponding to the plurality of target memory cells in the preset decoding operation, and perform an adjusted preset decoding operation with the replaced plurality of log-likelihood ratios on the plurality of soft information to obtain a plurality of final decoded codewords corresponding to the plurality of target entity pages, respectively, thereby completing the reading operation.

9. The storage controller of claim 8, wherein the preset decoding operation comprises a plurality of iterative decoding operations that apply a low density parity check algorithm.

10. The memory controller of claim 8, wherein the soft information is preset as a first, second, or third state-like soft information, wherein

In response to the soft information being preset as the first-mode soft information,

the error checking and correcting circuit performs a predetermined decoding operation on the hard bit code words to obtain the minimum syndrome code words corresponding to the hard bit code words respectively,

wherein the read assist circuit unit composes a plurality of soft information of the plurality of target memory cells according to the plurality of minimum syndrome codewords of the plurality of target memory cells respectively corresponding to the plurality of target entity pages,

wherein in response to the soft information being preset as the second-aspect soft information,

the reading auxiliary circuit unit directly combines the plurality of hard bit code words respectively corresponding to the target entity pages into the plurality of soft information of the plurality of target storage units,

wherein in response to the soft information being preset as the third sample soft information,

the error checking and correcting circuit selects one of the plurality of hard bit code words to perform the predetermined decoding operation to obtain a minimum syndrome code word corresponding to the selected hard bit code word,

wherein the read assist circuit unit composes the plurality of soft information of the plurality of target memory cells according to the minimum syndrome codeword of the selected hard bit codeword and all other hard bit codewords of the plurality of hard bit codewords that are not selected.

11. The memory controller of claim 10, wherein in operation of the error checking and correcting circuit performing the predetermined decoding operations on the hard bit codewords to obtain the syndrome codewords corresponding to the hard bit codewords,

a first pre-set decoding operation performed on a first hard bit codeword of the plurality of hard bit codewords, wherein the first pre-set decoding operation comprises a plurality of iterative decoding operations,

the error checking and correction circuit obtains a decoded hard bit codeword and a hard bit syndrome corresponding to the decoded hard bit codeword each time one of the plurality of iterative decoding operations is completed,

wherein the error checking and correcting circuit selects a smallest one of a plurality of hard bit syndromes as a smallest hard bit syndrome and identifies a decoded hard bit codeword corresponding to the smallest hard bit syndrome from a plurality of decoded hard bit codewords as a smallest syndrome codeword, wherein a total number of the plurality of iterative decoding operations is less than or equal to an iteration number threshold.

12. The storage controller of claim 11, wherein each target entity page of one target storage unit corresponds to one soft bit of soft information of the one target storage unit, and a total number of all soft bits of the soft information of the one target storage unit is equal to a total number of all target entity pages of the one target storage unit.

13. The memory controller according to claim 8, wherein in an operation in which the read assist circuit unit identifies the plurality of degrees of confidence of the plurality of target memory cells respectively corresponding to the plurality of target entity pages according to the plurality of confidence tables respectively corresponding to the plurality of target entity pages and the plurality of soft information of the plurality of target memory cells,

the read-assist circuit unit identifies a first threshold voltage distribution area to which the first target memory cell among the plurality of threshold voltage distribution areas belongs according to the first soft information,

wherein the read assist circuit unit searches a first predetermined confidence corresponding to the first threshold voltage distribution region from the first confidence table according to the first threshold voltage distribution region,

wherein the read assist circuit unit identifies the first predetermined confidence as a first confidence of the plurality of confidences of the first target storage unit corresponding to the first target entity page.

14. The memory controller according to claim 13, wherein absolute values of a plurality of predetermined confidence levels corresponding to the plurality of threshold voltage distribution regions in the first confidence table of the first target physical page are set by the read assist circuit unit according to a plurality of voltage relative relationships between a first converted read voltage corresponding to the first target physical page in the predetermined read voltage group and the plurality of threshold voltage distribution regions,

wherein the positive or negative of the predetermined confidence levels is set by the reading auxiliary circuit unit according to the bit value of the first target entity page in the plurality of bit values of the gray code pattern corresponding to the plurality of threshold voltage distribution areas,

wherein the bit value corresponding to the first target physical page is "1" in a plurality of bit values in response to the gray code pattern corresponding to the first threshold voltage distribution region, the first predetermined confidence corresponding to the first threshold voltage distribution region is set to a negative value by the read assist circuit unit,

wherein the bit value corresponding to the first target physical page in the plurality of bit values corresponding to the gray code pattern corresponding to the first threshold voltage distribution region is "0", and the first predetermined confidence corresponding to the first threshold voltage distribution region is set to a positive value by the read assist circuit unit.

15. A storage device, the storage device comprising:

a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of word lines, wherein each of the word lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells comprises a plurality of physical pages, and each of the plurality of physical pages is programmed to a bit value;

a memory interface control circuit for coupling to the rewritable nonvolatile memory module; and

a processor coupled to the memory interface control circuit, wherein the processor loads and executes the read assist code module to implement a data reading method, the data reading method comprising the steps of: