CN111681996B - High-safety chip packaging structure and packaging method - Google Patents
High-safety chip packaging structure and packaging method Download PDFInfo
- Publication number
- CN111681996B CN111681996B CN202010572609.1A CN202010572609A CN111681996B CN 111681996 B CN111681996 B CN 111681996B CN 202010572609 A CN202010572609 A CN 202010572609A CN 111681996 B CN111681996 B CN 111681996B
- Authority
- CN
- China
- Prior art keywords
- chip
- layer
- metal
- metal shielding
- shielding layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a high-safety chip packaging structure and a packaging method, wherein a buried groove is prepared on a semiconductor substrate, a first metal shielding layer is prepared at the bottom of the buried groove, a chip is placed in the buried groove, the first metal shielding layer is combined with a second metal shielding layer in a rewiring layer to jointly form a three-dimensional metal shielding net for the chip, high-safety protection is provided for the chip, and therefore the high-safety chip packaging structure is realized. The technical scheme of the invention can provide three-dimensional physical protection for the chip and effectively resist physical invasion attack aiming at the chip. Meanwhile, the three-dimensional metal shielding net structure can isolate the chip from the outside by electromagnetic signals, so that electromagnetic radiation signals generated when the chip works are shielded on one hand, the capability of the chip for resisting electromagnetic side channel attacks is enhanced, on the other hand, the interference of the outside electromagnetic signals on the normal work of the chip is reduced, and the working reliability of the chip is improved.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a high-safety chip packaging structure and a high-safety chip packaging method.
Background
With the continuous development of science and technology, various electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.
The control core of the electronic device for realizing various functions is a chip, and in order to ensure safe and reliable operation of the chip and avoid damage to the chip, the chip needs to be packaged and protected to form a packaging structure. In the prior art, a chip is generally protected by simple plastic package only through a plastic package layer.
Disclosure of Invention
In view of this, the technical solution of the present invention provides a high-security chip packaging structure and a packaging method, which can provide three-dimensional physical protection for a chip, effectively resist physical intrusion attack to the chip, and not only can realize packaging protection of the chip, but also can prevent the chip from electromagnetic interference.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
a high security chip package structure, the package structure comprising:
a semiconductor substrate having a first surface;
the embedded groove is arranged on the first surface, and a first metal shielding layer is arranged on the surface of the embedded groove;
a chip disposed in the embedding slot;
a rewiring layer disposed on the first surface;
solder balls disposed on the rewiring layer;
wherein the rewiring layer includes: a first insulating layer covering the first surface and the chip; a second insulating layer disposed between the first insulating layer and the solder balls; the second metal shielding layer and the metal interconnection line are positioned between the first insulating layer and the second insulating layer, the metal interconnection line is used for connecting the pins of the chip and the solder balls, and the second metal shielding layer is insulated from the metal interconnection line.
Preferably, in the above package structure, the first metal shielding layer is connected to the second metal shielding layer.
Preferably, in the above package structure, the first metal shielding layer and the second metal shielding layer are electrically connected to each other, and the metal wiring structure is connected to a pin of the chip.
Preferably, in the above package structure, the second metal shielding layer is on the same layer as the metal interconnection line;
or the second metal shielding layer and the metal interconnection line are in different layers, and a third insulating layer is arranged between the second metal shielding layer and the metal interconnection line.
Preferably, in the above package structure, the package further includes: and the insulating medium is filled between the chip and the side wall of the embedded groove.
Preferably, in the above package structure, the insulating medium is any one of polyimide, epoxy resin, and benzocyclobutene.
Preferably, in the above package structure, the semiconductor substrate is a silicon-based wafer, and the crystal orientation is <100 >.
Preferably, in the above package structure, the depth of the buried trench is 20 μm to 200 μm.
Preferably, in the above package structure, the package further includes: and the insulating medium layer covers the side wall and the bottom surface of the embedded groove.
Preferably, in the above package structure, the insulating dielectric layer is silicon oxide and has a thickness of 0.1 μm to 5 μm.
Preferably, in the above package structure, the first metal shielding layer and the second metal shielding layer each include an adhesion layer and a preset metal layer disposed on a surface of the adhesion layer.
Preferably, in the above package structure, the thickness of the adhesion layer is 100nm to 10000nm, and the thickness of the predetermined metal layer is 5000 nm.
Preferably, in the above package structure, the chip is fixed at the bottom of the embedding groove by an adhesive layer or eutectic bond.
Preferably, in the above package structure, the first insulating layer and the second insulating layer are made of polyimide or benzocyclobutene;
the metal interconnection line is any one of Cu, Al or Au.
Preferably, in the above package structure, the first insulating layer and the second insulating layer have a thickness of 0.5 μm to 5 μm.
Preferably, in the above package structure, the first surface has one or more buried grooves, and one or more chips are disposed in the buried grooves.
The invention also provides a high-safety chip packaging method, which comprises the following steps:
forming a buried trench on a first surface of a semiconductor substrate;
forming a first metal shielding layer on the surface of the embedded groove;
fixing a chip in the embedding groove;
forming a rewiring layer on the first surface;
forming a solder ball on the surface of the rewiring layer;
wherein the rewiring layer includes: a first insulating layer covering the first surface and the chip; a second insulating layer disposed between the first insulating layer and the solder balls; the second metal shielding layer and the metal interconnection line are positioned between the first insulating layer and the second insulating layer, the metal interconnection line is used for connecting the pins of the chip and the solder balls, and the second metal shielding layer is insulated from the metal interconnection line.
As can be seen from the above description, in the high-security chip packaging structure and the packaging method provided in the technical solution of the present invention, the embedded groove is prepared on the semiconductor substrate, the first metal shielding layer is prepared at the bottom of the embedded groove, the chip is placed in the embedded groove, and the first metal shielding layer is combined with the second metal shielding layer in the rewiring layer to form the three-dimensional metal shielding mesh for the chip, so as to provide high security protection for the chip, thereby implementing the high-security chip packaging structure. The technical scheme of the invention can provide three-dimensional physical protection for the chip and effectively resist physical invasion attack aiming at the chip. Meanwhile, the three-dimensional metal shielding net structure can isolate the chip from the outside by electromagnetic signals, so that electromagnetic radiation signals generated when the chip works are shielded on one hand, the capability of the chip for resisting electromagnetic side channel attacks is enhanced, on the other hand, the interference of the outside electromagnetic signals on the normal work of the chip is reduced, and the working reliability of the chip is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of a high-security chip package structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a redistribution layer according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for packaging a high-security chip according to an embodiment of the present invention;
fig. 4-9 are flow charts of a chip packaging process according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The chip is used as the bottom core hardware of the modern information society and plays an important role in the fields of calculation, storage and the like. However, attack methods for chips are also emerging, and particularly, attack means and methods for cryptographic chips for providing tasks such as information encryption, decryption, authentication and the like are more endlessly developed. In the current attack methods for chips, the methods can be roughly divided into two main categories: invasive attacks and non-invasive attacks. The invasive attack is to tamper the internal structure of the chip or read important information by methods such as opening a cover, corroding, drilling and the like on the packaging structure of the chip and then using focused ion beams, microprobes, photographs and the like; the non-invasive attack is to collect and process information such as power consumption and electromagnetic radiation generated during the operation of the chip, and analyze and crack data running inside the chip. Therefore, how to effectively protect the chip has become more and more important.
The packaging structure of the chip is used as a first barrier for protecting the chip, and has important significance on the safety and the attack resistance of the chip. However, the conventional chip package structure and form usually only provides an electrical connection path for the chip, so as to protect the chip from the external environment, and the chip package structure and form are not fully considered and reasonably designed in terms of the attack resistance of the chip.
The existing anti-attack security chip packaging structure in the prior art is mostly realized by adopting ceramic packaging, and the integrity of a metal wire can be damaged by physical invasion attack aiming at a chip by carrying out metal protection wiring on a packaged ceramic substrate and a packaged cover plate, so that the chip can be detected. However, the implementation method of the ceramic package has high cost and large volume after packaging, and cannot well meet the development direction of miniaturization and light weight of the chip at present. Meanwhile, due to the limitation of the processing technology precision of ceramic packaging, the width and the interval of the internal metal protection wiring cannot be made to be small. Therefore, the attack detection precision is limited, and the security threat of increasingly fine, accurate and efficient attack means cannot be overcome.
In view of the security threat faced by the current chip and the defects of the existing packaging technology, the technical scheme of the invention fully utilizes the existing advanced packaging technology, fully considers the security requirement of the chip, and provides a chip packaging structure and a packaging method with high security and small volume, which are not only suitable for packaging a single chip, but also can be used for system-in-package of a plurality of chips, thereby solving the threat of intrusive attack faced by the current chip, and simultaneously greatly improving the difficulty of non-intrusive attack.
Therefore, in order to solve the above problems, the present invention provides a chip packaging structure with high security and a packaging method thereof, wherein the packaging method comprises:
a semiconductor substrate having a first surface;
the embedded groove is arranged on the first surface, and a first metal shielding layer is arranged on the surface of the embedded groove;
a chip disposed in the embedding slot;
a rewiring layer disposed on the first surface;
solder balls disposed on the rewiring layer;
wherein the rewiring layer includes: a first insulating layer covering the first surface and the chip; a second insulating layer disposed between the first insulating layer and the solder balls; the second metal shielding layer and the metal interconnection line are positioned between the first insulating layer and the second insulating layer, the metal interconnection line is used for connecting the pins of the chip and the solder balls, and the second metal shielding layer is insulated from the metal interconnection line.
As can be seen from the above description, in the high-security chip packaging structure and the packaging method provided in the technical solution of the present invention, the embedded groove is prepared on the semiconductor substrate, the first metal shielding layer is prepared at the bottom of the embedded groove, the chip is placed in the embedded groove, and the first metal shielding layer is combined with the second metal shielding layer in the rewiring layer to form the three-dimensional metal shielding mesh for the chip, so as to provide high security protection for the chip, thereby implementing the high-security chip packaging structure. The technical scheme of the invention can provide three-dimensional physical protection for the chip and effectively resist physical invasion attack aiming at the chip. Meanwhile, the three-dimensional metal shielding net structure can isolate the chip from the outside by electromagnetic signals, so that electromagnetic radiation signals generated when the chip works are shielded on one hand, the capability of the chip for resisting electromagnetic side channel attacks is enhanced, on the other hand, the interference of the outside electromagnetic signals on the normal work of the chip is reduced, and the working reliability of the chip is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic diagram of a high-security chip package structure provided in an embodiment of the present invention, and fig. 2 is a schematic diagram of a re-wiring layer provided in an embodiment of the present invention.
As shown in fig. 1 and 2, the package structure includes:
a semiconductor substrate 11 having a first surface; the embedded groove 12 is arranged on the first surface, and a first metal shielding layer 13 is arranged on the surface of the embedded groove 12; a chip 14 disposed in the buried trench 12; a rewiring layer 15 provided on the first surface; and solder balls 16 disposed on the re-wiring layer 15.
Wherein the rewiring layer 15 includes: a first insulating layer 21 covering the first surface and the chip 14; a second insulating layer 23 disposed between the first insulating layer 21 and the solder ball 16; a second metal shielding layer 22 and a metal interconnection line 17 located between the first insulating layer 21 and the second insulating layer 23, the metal interconnection line 17 is used for connecting the pin of the chip 14 and the solder ball 16, and the second metal shielding layer 22 is insulated from the metal interconnection line 17.
The first metal shielding layer 13 includes a wiring located on the bottom surface of the embedded groove 12 and a climbing line located on the sidewall of the embedded groove 12. The metal interconnection lines 17 are shown in fig. 1, the second metal shield layer 22 not being shown. The metal interconnection line 17 is not shown in fig. 2, showing the second metal shield layer 22.
The first metal shielding layer 13 is connected with the second metal shielding layer 22, and the first metal shielding layer 13 can be connected with the second metal shielding layer 22 through a climbing line on the side wall of the embedded groove 12 to jointly form a three-dimensional metal shielding net, so that high safety protection on the chip is realized.
The first metal shielding layer 13 and the second metal shielding layer 22 are electrically connected metal wiring structures, and the metal wiring structures are connected with pins of the chip 14. Electrical parameters of the metal wiring structure, such as current and/or voltage, may be detected by a detection circuit inside the chip 14 to determine whether the metal wiring structure has a broken portion, thereby determining whether the package structure of the chip 14 is physically damaged.
In the embodiment of the invention, the embedded groove 12 is prepared on the semiconductor substrate 11, the first metal shielding layer 13 is prepared on the surface of the embedded groove 12, then the chip 14 is placed in the embedded groove 12, and the first metal shielding layer 13 is combined with the second metal shielding layer 22 in the rewiring layer 15, so that three-dimensional protection for the chip 14 is formed, not only can the packaging protection of the chip be realized, but also the chip can be prevented from being subjected to electromagnetic interference.
In the embodiment of the present invention, the second metal shielding layer 22 is on the same layer as the metal interconnection line 17; or, the second metal shielding layer 22 and the metal interconnection line 17 are different layers, and a third insulating layer (not shown) is disposed between the second metal shielding layer 22 and the metal interconnection line 17, and the second metal shielding layer 22 is insulated from the metal interconnection line 17.
The first insulating layer 21 and the second insulating layer 23 may be made of common encapsulation organic dielectric materials such as polyimide, benzocyclobutene, or the like; the metal interconnection line 17 may be any one of Cu, Al, or Au.
Wherein the first insulating layer 21 and the second insulating layer 23 may have a thickness of 0.5 μm to 5 μm.
In an embodiment of the present invention, the package structure further includes: an insulating medium 18 filled between the chip 14 and the side wall of the buried trench 12. The insulating medium 18 may be filled by a coating method such as spin coating or spray coating.
Further, the insulating medium 18 may be any one of common encapsulating organic medium materials such as polyimide, epoxy resin, benzocyclobutene, and the like.
In the embodiment of the present invention, the semiconductor substrate 11 is a silicon-based wafer, and the crystal orientation is <100 >.
Further, the depth of the buried trench 12 may be 20 μm to 200 μm. The buried trench 12 is prepared by a wet etching method such as KOH (potassium hydroxide), TMAH (tetramethylammonium hydroxide), etc., the buried trench 12 having an inverted trapezoid shape is formed on a silicon-based wafer substrate having a crystal orientation of <100>, the chip 14 can be thinned to 20 μm to 200 μm according to actual requirements, and the depth of the buried trench 12 can be 20 μm to 200 μm according to the difference in the thickness of the chip 14.
In an embodiment of the present invention, the package structure further includes: an insulating dielectric layer (not shown in fig. 1) covering the sidewalls and bottom surface of the buried trench 12. An insulating dielectric layer may be formed on the surface of the semiconductor substrate 11 and on the sidewall and the bottom surface of the buried trench 12 by a dry oxidation method, wherein the insulating dielectric layer may be silicon oxide and may have a thickness of 0.1 μm to 5 μm.
Further, the first metal shielding layer 13 and the second metal shielding layer 22 each include an adhesion layer and a preset metal layer disposed on the surface of the adhesion layer. It should be noted that the adhesion layer may be Ti or TiW alloy, the predetermined metal layer may be Cu or Au, and the first metal shielding layer 13 and the second metal shielding layer 22 may be prepared by sputtering Ti/Cu, and performing photolithography and etching.
The thickness of the adhesion layer may be 100nm to 10000nm, such as 500nm, and the thickness of the predetermined metal layer may be 5000 nm.
In the embodiment of the present invention, the chip 11 may be fixed at the bottom of the embedding slot 12 through an adhesive layer or a eutectic bond.
In the embodiment of the present invention, the first surface has one or more embedded grooves 12, and one or more chips 14 are disposed in the embedded grooves 12. If the chip 14 has a plurality of chips 14 in its package structure, the chips 14 may be electrically interconnected by metal interconnection lines 17 in the redistribution layer 15.
As can be seen from the above description, in the high-security chip packaging structure provided by the technical solution of the present invention, the embedded groove 12 is prepared on the semiconductor substrate 11, the chip 14 is placed in the embedded groove 12, and the first metal shielding layer 13 and the second metal shielding layer 22 are prepared, and the first metal shielding layer 13 is connected to the second metal shielding layer 22 through the slope climbing line on the sidewall of the embedded groove 12, so as to form a three-dimensional protection for the chip 14.
According to the technical scheme, the chip is protected in a three-dimensional mode by the metal shielding layer, the process is simple, the practicability is high, physical invasion attack aiming at the chip can be effectively resisted, the chip and the outside can be isolated by the three-dimensional metal shielding net structure, on one hand, electromagnetic radiation generated when the chip works is shielded, the capability of the chip for resisting electromagnetic side channel attack is enhanced, on the other hand, interference of the outside electromagnetic signal on normal work of the chip is reduced, the reliability of work of the chip is improved, the packaging protection of the chip is realized, and the chip is prevented from being subjected to electromagnetic interference.
Based on the foregoing embodiment, another embodiment of the present invention further provides a high-security chip packaging method, where the packaging method is shown in fig. 3, fig. 3 is a high-security chip packaging method provided in an embodiment of the present invention, and fig. 4 to fig. 9 are flowcharts of a chip packaging process provided in an embodiment of the present invention.
As shown in fig. 3 to 9, the packaging method includes:
step S11: as shown in fig. 4 and 5, a buried trench 12 is formed on a first surface of a semiconductor substrate 11.
First, as shown in fig. 4, a semiconductor substrate 11 is provided, the semiconductor substrate 11 has a first surface and a second surface opposite to each other, and then, as shown in fig. 5, a buried trench 12 having an inverted trapezoid shape is prepared on the first surface of the semiconductor substrate 11 by using a wet etching method, and one or more buried trenches 12 may be formed according to actual requirements.
Step S12: as shown in fig. 6, a first metal shielding layer 13 is formed on the surface of the buried trench 12.
The first metal shielding layer 13 is prepared at the bottom of the buried trench 12 and at the same time, a ramp line (not shown in fig. 6) for interconnection is formed, and the first metal shielding layer 13 can be prepared by sputtering Ti/Cu, photolithography and etching.
Step S13: as shown in fig. 7, the chip 14 is fixed in the embedding slot 12.
The chip 14 is fixed at the bottom of the buried groove 12 through an adhesive layer, or eutectic bond, and is bonded with the first metal shielding layer 13 at the bottom of the buried groove 12.
Step S14: as shown in fig. 8, a rewiring layer 15 is formed on the first surface.
A rewiring layer 15 is prepared on the first surface of the semiconductor substrate 11 to realize interconnection of the second metal shielding layer and the internal pins of the chip 14. Before the redistribution layer 15 is formed, the remaining space in the buried trench 12 is filled with an insulating dielectric 18.
Step S15: as shown in fig. 9, solder balls 16 are formed on the surface of the redistribution layer 15; wherein the rewiring layer 15 includes: a first insulating layer covering the first surface and the chip 14; a second insulating layer disposed between the first insulating layer and the solder balls 16; a second metal shielding layer and a metal interconnection line 17 located between the first insulating layer and the second insulating layer, wherein the metal interconnection line 17 is used for connecting the pin of the chip 14 and the solder ball 16, and the second metal shielding layer is insulated from the metal interconnection line 17.
The solder ball 16 can be prepared by adopting the conventional solder ball preparation technology in packaging, the packaging is completed, and the pins of the external interconnection of the whole packaging structure can be led out through the solder ball 16 above the rewiring layer 15.
In the embodiment of the invention, a wet etching method is adopted to prepare and form a buried groove 12 on a semiconductor substrate 11, then a first metal shielding layer 13 and a climbing line for interconnecting with a second metal shielding layer are formed on the surface of the buried groove 12, a chip 14 is placed in the buried groove 12, the back of the chip 14 is bonded and bonded with the first metal shielding layer 13, then an insulating medium 18 is adopted to fill the residual space in the buried groove 12, then a rewiring layer 15 is prepared on the first surface of the semiconductor substrate 11, the rewiring layer can be used for preparing an internal electrical interconnection structure between the second metal shielding layer and one or more pins of the chip 14, and finally a solder ball 16 structure is prepared on the surface of the rewiring layer 15 to complete packaging.
As can be seen from the above description, in the high-security chip packaging method provided in the technical solution of the present invention, the embedded groove is prepared on the semiconductor substrate, the first metal shielding layer is prepared at the bottom of the embedded groove, the chip is placed in the embedded groove, and the first metal shielding layer is combined with the second metal shielding layer in the rewiring layer to form a three-dimensional metal shielding mesh for the chip, so as to provide high security protection for the chip, thereby implementing a high-security chip packaging structure. The technical scheme of the invention can provide three-dimensional physical protection for the chip and effectively resist physical invasion attack aiming at the chip. Meanwhile, the three-dimensional metal shielding net structure can isolate the chip from the outside by electromagnetic signals, so that electromagnetic radiation signals generated when the chip works are shielded on one hand, the capability of the chip for resisting electromagnetic side channel attacks is enhanced, on the other hand, the interference of the outside electromagnetic signals on the normal work of the chip is reduced, and the working reliability of the chip is improved.
All the embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from other embodiments. Particularly, for the embodiment of the chip packaging method, since it is substantially similar to the embodiment of the chip packaging structure, the description is simple, and the relevant points can be referred to the partial description of the embodiment of the chip packaging structure.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (15)
1. A high-security chip package structure, comprising:
a semiconductor substrate having a first surface;
the embedded groove is arranged on the first surface, the surface of the embedded groove is provided with a first metal shielding layer, and the first metal shielding layer comprises a wiring positioned on the bottom surface of the embedded groove and a climbing line positioned on the side wall of the embedded groove;
a chip disposed in the embedding slot;
a rewiring layer disposed on the first surface;
solder balls disposed on the rewiring layer;
wherein the rewiring layer includes: a first insulating layer covering the first surface and the chip; a second insulating layer disposed between the first insulating layer and the solder balls; the second metal shielding layer and the metal interconnection line are positioned between the first insulating layer and the second insulating layer, the metal interconnection line is used for connecting a pin of the chip and the solder ball, and the second metal shielding layer is insulated from the metal interconnection line;
the first metal shielding layer is connected with the second metal shielding layer through the climbing line; the first metal shielding layer and the second metal shielding layer are electrically connected metal wiring structures to form a three-dimensional metal shielding net for isolating the chip from the outside by electromagnetic signals; the metal wiring structure is connected with the pins of the chip and is also used for detecting the electrical parameters of the metal wiring structure through a detection circuit in the chip and judging whether the metal wiring structure has a disconnected part or not.
2. The package structure of claim 1, wherein the second metal shielding layer is in the same layer as the metal interconnection line;
or, the second metal shielding layer and the metal interconnection line are in different layers, and a third insulating layer is arranged between the second metal shielding layer and the metal interconnection line.
3. The package structure of claim 1, further comprising: and the insulating medium is filled between the chip and the side wall of the embedded groove.
4. The package structure of claim 3, wherein the insulating medium is any one of polyimide, epoxy, and benzocyclobutene.
5. The package structure of claim 1, wherein the semiconductor substrate is a silicon-based wafer with a crystal orientation of <100 >.
6. The package structure of claim 1, wherein the buried trench has a depth of 20 μm to 200 μm.
7. The package structure of claim 1, further comprising: and the insulating medium layer covers the side wall and the bottom surface of the embedded groove.
8. The package structure of claim 7, wherein the insulating dielectric layer is silicon oxide and has a thickness of 0.1 μm to 5 μm.
9. The package structure according to claim 8, wherein the first metal shielding layer and the second metal shielding layer each comprise an adhesion layer and a preset metal layer disposed on a surface of the adhesion layer.
10. The package structure according to claim 9, wherein the adhesion layer has a thickness of 100nm to 10000nm, and the predetermined metal layer has a thickness of 5000 nm.
11. The package structure of claim 1, wherein the chip is fixed to the bottom of the buried trench by an adhesive layer or eutectic bonding.
12. The package structure of claim 1, wherein the first and second insulating layers are polyimide or benzocyclobutene;
the metal interconnection line is any one of Cu, Al or Au.
13. The package structure of claim 1, wherein the first insulating layer and the second insulating layer have a thickness of 0.5 μ ι η to 5 μ ι η.
14. The package structure according to any one of claims 1 to 13, wherein the first surface has one or more of the buried trenches, and one or more chips are disposed in the buried trenches.
15. A high-security chip packaging method is characterized by comprising the following steps:
forming a buried trench on a first surface of a semiconductor substrate;
forming a first metal shielding layer on the surface of the embedded groove, wherein the first metal shielding layer comprises a wiring on the bottom of the embedded groove and a climbing line on the side wall of the embedded groove;
fixing a chip in the embedding groove;
forming a rewiring layer on the first surface;
forming a solder ball on the surface of the rewiring layer;
wherein the rewiring layer includes: a first insulating layer covering the first surface and the chip; a second insulating layer disposed between the first insulating layer and the solder balls; the second metal shielding layer and the metal interconnection line are positioned between the first insulating layer and the second insulating layer, the metal interconnection line is used for connecting a pin of the chip and the solder ball, and the second metal shielding layer is insulated from the metal interconnection line;
the first metal shielding layer is connected with the second metal shielding layer through the climbing line; the first metal shielding layer and the second metal shielding layer are electrically connected metal wiring structures to form a three-dimensional metal shielding net for isolating the chip from the outside by electromagnetic signals; the metal wiring structure is connected with the pins of the chip and is also used for detecting the electrical parameters of the metal wiring structure through a detection circuit in the chip and judging whether the metal wiring structure has a disconnected part or not.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010572609.1A CN111681996B (en) | 2020-06-22 | 2020-06-22 | High-safety chip packaging structure and packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010572609.1A CN111681996B (en) | 2020-06-22 | 2020-06-22 | High-safety chip packaging structure and packaging method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111681996A CN111681996A (en) | 2020-09-18 |
| CN111681996B true CN111681996B (en) | 2022-09-27 |
Family
ID=72436300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010572609.1A Active CN111681996B (en) | 2020-06-22 | 2020-06-22 | High-safety chip packaging structure and packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111681996B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114566489A (en) * | 2022-04-27 | 2022-05-31 | 珠海市人民医院 | Fan-out type packaging structure with electromagnetic shielding function and packaging method |
| CN117133724A (en) * | 2023-03-20 | 2023-11-28 | 荣耀终端有限公司 | Packaged chip structure, processing method thereof and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101656244A (en) * | 2009-07-10 | 2010-02-24 | 中国科学院上海微系统与信息技术研究所 | Multilayer interconnection packaging structure of silica-based embedded microwave multi chip module and manufacturing method |
| CN102110673A (en) * | 2010-10-27 | 2011-06-29 | 中国科学院上海微系统与信息技术研究所 | Wafer level MMCM (microwave multichip module) packaging structure using photosensitive BCB (benzocyclobutene) as dielectric layer and method |
| CN209029359U (en) * | 2018-11-23 | 2019-06-25 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip chamber full-shield encapsulating structure based on substrate embedment technical module |
| CN110634842A (en) * | 2019-08-22 | 2019-12-31 | 上海先方半导体有限公司 | Packaging structure with electromagnetic shielding function and preparation method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201477600U (en) * | 2009-07-29 | 2010-05-19 | 深圳国微技术有限公司 | Tampered detecting circuit for protecting chip |
-
2020
- 2020-06-22 CN CN202010572609.1A patent/CN111681996B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101656244A (en) * | 2009-07-10 | 2010-02-24 | 中国科学院上海微系统与信息技术研究所 | Multilayer interconnection packaging structure of silica-based embedded microwave multi chip module and manufacturing method |
| CN102110673A (en) * | 2010-10-27 | 2011-06-29 | 中国科学院上海微系统与信息技术研究所 | Wafer level MMCM (microwave multichip module) packaging structure using photosensitive BCB (benzocyclobutene) as dielectric layer and method |
| CN209029359U (en) * | 2018-11-23 | 2019-06-25 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip chamber full-shield encapsulating structure based on substrate embedment technical module |
| CN110634842A (en) * | 2019-08-22 | 2019-12-31 | 上海先方半导体有限公司 | Packaging structure with electromagnetic shielding function and preparation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111681996A (en) | 2020-09-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7768005B2 (en) | Physically highly secure multi-chip assembly | |
| CN108597998B (en) | Wafer level system packaging method and packaging structure | |
| CN101772775B (en) | Tamper-resistant semiconductor device and methods of manufacturing thereof | |
| CN111681996B (en) | High-safety chip packaging structure and packaging method | |
| KR101394177B1 (en) | Package-on-package secure module having bga mesh cap | |
| US8455990B2 (en) | Systems and methods of tamper proof packaging of a semiconductor device | |
| CN102257516B (en) | For the equipment making electronic integrated circuit shell invade from physics or chemistry | |
| CN101393907B (en) | Protection for circuit boards | |
| KR100946074B1 (en) | Semiconductor device for fingerprint recognition | |
| CN102820274B (en) | There is stress and reduce 3D integrated micro assembly of interconnection and preparation method thereof | |
| US7952478B2 (en) | Capacitance-based microchip exploitation detection | |
| US7772679B2 (en) | Magnetic shielding package structure of a magnetic memory device | |
| CN102820282A (en) | 3D integration microelectronic assembly for integrated circuit devices and method of making same | |
| Borel et al. | A novel structure for backside protection against physical attacks on secure chips or sip | |
| JP2010004038A (en) | Neutron detection structure | |
| CN102544040B (en) | Method utilizing TSV (Through-Silicon-Via) to realize wafer level package of GaAs (gallium arsenide) image sensor | |
| CN109192706B (en) | Chip packaging structure and chip packaging method | |
| EP2889901B1 (en) | Semiconductor device with through-substrate via and corresponding method | |
| CN207651469U (en) | A kind of encapsulating structure of fingerprint chip | |
| JP2004296812A (en) | Semiconductor device and method of manufacturing the same | |
| TW202106605A (en) | Sensor and package assembly thereof | |
| WO2020047976A1 (en) | Wafer level system packaging method and packaging structure | |
| CN102420211B (en) | Image sensor package structure of micro salient point interconnection structure and realization method of image sensor package structure | |
| US11355456B2 (en) | Electronic chip with protected rear face | |
| Borel et al. | Backside Shield against Physical Attacks for Secure ICs |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |