CN111639436B - System fault propagation model modeling method - Google Patents
System fault propagation model modeling method Download PDFInfo
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Abstract
The invention provides a system fault propagation model modeling method, which comprises the following steps: step 1: constructing different level architecture models, and representing different level compositions and interactive relations thereof in a graphical and mathematical model mode; step 2: the method comprises the steps of expanding and defining module states, input/output port states and fault logic relations of the module states through graphs and mathematical models, realizing construction of fault propagation models of different levels, and forming a whole system fault propagation graphical and mathematical model based on internal interactive relations and mathematical expressions of different levels of a system; and step 3: a critical hardware failure mode is identified based on a system failure propagation model. The invention solves the problems of inaccuracy and incompleteness of the traditional reliability modeling method; and accurately positioning hardware failure modes causing the key functions of the system to fail in a graphical mode and a mathematical model mode.
Description
Technical Field
The invention belongs to the technical field of computer aided design, and particularly relates to a system fault propagation model modeling method which is suitable for a method for automatically analyzing a fault influence transfer relation by using a computer.
Background
The reliability is the inherent design attribute of the equipment product, and must be synchronously designed and effectively fused with the functional performance of the product. Reliability is a task of combating a fault, and designers need to find various defects and weak links of a product through continuous analysis and adopt effective improvement and compensation measures to improve the reliability level. On one hand, in the conventional Reliability design analysis method, a modeled fault propagation relation description method is lacked, for example, a Reliability Block Diagram (RBD) modeling method only considers binary states (normal and fault) of a system or equipment, and cannot be used for analyzing a multi-fault mode and a transfer relation thereof. Considering that a complex system has the characteristics of multiple fault modes, complex fault influence relation and the like, the accuracy and the integrity of reliability analysis work cannot be ensured only by representing the propagation relation among faults through a simple series-parallel relation. On the other hand, the functional FMEA based on manual deduction is disjointed with the hardware FMEA analysis work, and the key hardware fault mode cannot be positioned and identified according to the key functional fault mode list identified by the functional FMEA analysis, so that the design of the fault control measures of finished products cannot be effectively carried out.
Therefore, the invention provides a fault propagation relation graphical and mathematical modeling method suitable for a complex system, and can realize the fault mode influence analysis based on a model and identify a key fault mode.
Disclosure of Invention
The invention aims to provide a modeling method of a system fault propagation model, provides a modeling method for describing a fault propagation relation by a graphical display and a mathematical model in a reliability analysis process, aims to solve the problems of multiple fault modes, complex fault influence relation and the like of a complex system, provides an accurate and effective fault propagation relation, and is convenient for a designer to rapidly position a key fault mode to guide the designer to provide design improvement measures.
The invention provides a system fault propagation model modeling method, which comprises the following implementation steps:
1. a system fault propagation model modeling method comprises the following steps:
the method comprises the following steps: architecture model construction
(1) Defining and dividing appointed layers, wherein the appointed layers comprise a system, a subsystem, an external field replaceable unit, an internal field replaceable unit, a functional circuit and components, and the appointed layers are sequentially from a layer 1 to a layer 6;
(2) Constructing a system model, constructing a graph and a mathematical model on the basis of module elements, wherein the constructed content comprises a system module, system output port information and a system function state, and establishing a system module N C With { F I c ，F O c ，S c And dom } is represented by I c Presentation System Module N C Input port of (1), F O c Presentation System Module N C Output port of, S c Presentation System Module N C Functional space, F I c 、F O c And S c Collectively referred to as system model variables, dom is a full set of functions of dom (x), meaning that all possible values are taken when the variable is x, where x can be taken as the system model variable S c 、F I c 、F O c ；
(3) Constructing an internal architecture model, namely constructing a graph and a mathematical model on the basis of module elements aiming at a system, a subsystem, an LRU (least recently used) module and an SRU (remote unit) module, wherein the constructed content comprises each level of composition units, component input/output port information and component state information; aiming at a functional circuit module, components contained in a functional circuit are constructed on the basis of module elements, but port information is not constructed, and the ith product node N of the ith layer is set ij In { FI ij ，F O ij ，S ij And dom } is represented by I ij Denotes the input port of the jth internal module of the ith layer, F O ij Represents the output port of the ith inner module, S ij The module is expressed in a normal function state, and the last layer of component module only needs to define the state S 6j ，F I ij 、F O ij And S ij Collectively referred to as internal module model variables, where dom is also the full set function of dom (x), x is an internal module model variable, and dom represents all possible values taken for the internal module model variable;
(4) Constructing an internal module interactive relation, namely, performing graph construction according to the signal transmission relation among modules aiming at the subsystems, the LRU, the SRU and the functional circuit modules, and reflecting the interactive relation of input and output ports of each module; for each module mathematical model, set
Wherein p is i Is a module N ij Number of input ports of q j Is a module N ij The number of output ports of (a) is,
the representing module N ij The p-th input port of (a),
representing a module N ij The qth output port of (1); if the module N ij Q th output port of (2)
And module N ik P th input port of (2)
When connected, the connection relationship of the ports is defined as
(5) Establishing a connection relation between the component port and the system port, and graphically establishing a connection relation between the subsystem port and the system port on the basis of a signal transmission relation between modules aiming at a system and the subsystem module; for the module mathematical model, if the system module N is divided 2j Input port of (2)
And system module N C Is connected to the input port
When they are connected, the mathematical relationship between them is defined as
If subsystem module N 2j Of the output port
And system module N c Of the output port
When they are connected, the mathematical relationship between them is defined as
Step two: fault propagation model construction
(1) Definition of system function failure state aiming at system module N C S in (1) C Carrying out extension definition on the state elements, and constructing the content as each function fault state of the system;
(2) Component failure mode definition, building blocks N for each hierarchy ij S in (1) ij Performing extension definition on the state elements, and constructing the content as a fault mode of each component;
(3) The module port expansion definition of each layer is specific to the system module, subsystem, LRU, SRU and functional circuit module port variable F I ij 、F O ij The enumeration type is adopted to clearly define normal output and abnormal output;
(4) Establishing a fault propagation model of each module represented in a fault tree form, and describing a logical combination relation of a system function failure state and an output port failure state thereof in a fault tree graphical form aiming at a system module; aiming at the subsystems, the LRU, the SRU module and the functional circuit module, describing the logical combination relationship of the output port failure state of the component module, the input port failure state of the module and the failure state of the module in a fault tree graphical mode; regarding the lowest layer module, considering the worst condition, taking a functional failure mode of a functional circuit as a top event, taking a hardware failure mode of each component, which causes the functional failure mode of the functional circuit, as a bottom event, and connecting the bottom events by an OR gate to form a failure propagation model represented by a failure tree form; for system module N C 、N ij A variable sigma is added in the mathematical model and used for describing the influence relationship of the current module state variable and the input value on an output port, and the influence relationship is expressed as follows:
where o denotes an and logic, which may be replaced with #/u depending on the specific logical relationship,
is a system module N C The output port of (a) is connected to the output port,
is a module N ij P th input port, state C (state C ∈dom(S C ) Is N) C State space of (2) ij (state ij ∈dom(S ij ) Is N) ij A state space of (a);
the representing module N C The ports are represented by a function in logical combination with or,
representing a module N ij State of the function whose input port is represented by being logically combined with ij The representing module N ij A function whose state is represented by an and or logical combination;
(5) Traversing all module fault propagation models, replacing the input failure state received by each module by the output port failure state fault tree corresponding to other modules, and synthesizing a full-system fault propagation graphical model taking the self function failure state of the system as a top event and the self failure state of the module as a bottom event; aiming at each module mathematical model, if the modules are connected with the same level, the mathematical model meets the requirements
Then there is
If the connection is a connection of cross-layer modules, the connection is satisfied
Then there is
Final σ (state) C ) Expressed as: σ (state) C )＝◇state ij ；
Step three: identification of critical hardware failure modes based on system failure propagation model
(1) And based on the fault propagation graphical model, tracing the functional failure state of the topmost module, namely the fault mode influence, caused by the failure state of the bottommost module along the logic gate from bottom to top. In the tracing process, only the fault influence of the OR gate is 'influenced' in the way, and the corresponding hardware fault mode is a key hardware fault mode; as long as the fault influence of the approach AND gate is 'no influence', the corresponding hardware fault mode can be ignored;
(2) Based on the mathematical model sigma (state) C ) The boolean function relationship in (1) analyzes the influence of the state of the bottommost module on the state of system functional failure, with only the mathematical model σ (state) being u-gate in all (u) C ) If an n gate exists, the fault influence is 'no influence', and the corresponding hardware fault mode can be ignored;
(3) And (3) comparing the key hardware fault modes obtained in the steps (1) and (2), if the key hardware fault modes are the same, indicating that the key hardware fault mode is correctly identified, and if the key hardware fault modes are different, indicating that the system fault propagation model is incorrect, returning to the step one, and modeling the system fault propagation model again.
Preferably, step (4) in step two further comprises:
in the process of establishing the fault propagation model of each module, the fault logic relationship between the components and the system is kept consistent, according to the cross-hierarchy port connection relationship of the system, the system-level input port is simultaneously connected with the output of the system-level preamble module and the input port of the corresponding component unit in the system, and the system-level output port is simultaneously connected with the input port of the system-level subsequent module and the output port of the corresponding component unit in the system, so that the consistency of the state and the fault logic definition among the three modules is kept in the modeling process.
Preferably, the system malfunction state definition in step (1) in step two includes a malfunction or an abnormality.
Preferably, S in step (2) in the second step 6j The fault state is defined as: the resistor is open circuit or parameter drift, the capacitor is open circuit, short circuit or parameter drift, and the integrated chip has electrical property failure, electrical output error or no output.
The invention provides a system fault propagation model modeling method through the steps, and the problems that the system fault modes are multiple, the fault influence relationship is complex, the functional FMEA and hardware FMEA analysis is disjointed and the like can be effectively solved. The advantages are that:
(1) The problems that a traditional reliability modeling method is inaccurate and incomplete are solved;
(2) Clearly and visually displaying the fault propagation relation between different levels of the system in a graphical mode, and accurately expressing the fault logic relation between different levels of the system in a mathematical model mode;
(3) And accurately positioning a hardware fault mode causing the failure of the key functions of the system, and guiding the design improvement.
Drawings
FIG. 1 is a block diagram of the overall architecture of the method of the present invention;
FIG. 2a is an exemplary diagram of the architectural model building of the system modules in the present invention;
FIG. 2b is an exemplary diagram of the architectural modeling of the subsystem in the present invention;
FIG. 2c is an exemplary diagram of the architectural modeling of functional circuit modules in the present invention;
FIG. 3a is an exemplary diagram of the system module architecture model state extension definition in the present invention;
FIG. 3b is an exemplary diagram of the architectural model state extension definition of the functional circuit module in the present invention;
FIG. 4a is an exemplary diagram of a fault propagation model for subsystem A;
FIG. 4b is an exemplary diagram of a fault propagation model for subsystem C;
FIG. 5 is an exemplary diagram of top module functionality and output port fault propagation models in the present invention;
FIG. 6 is an exemplary diagram of a lowest module fault propagation model in the present invention;
FIG. 7 is an exemplary graph of the failure propagation model merging results in the present invention; and
FIG. 8 is an exemplary diagram of a system-wide fault propagation model in the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
The invention provides a system fault propagation model modeling method. First, define and divide the system contractDetermining the level and defining a modeling object; then, the product structure composition of different levels of the system is used as input, a structure graphical model is constructed on the basis of the module, the state and the signal transmission relation elements among the modules, and the module N, the state S and the input port F are used I Output port F O Constructing a hierarchical mathematical model for the mathematical expression of the variables; then, a fault propagation model is constructed through the graphical data variable expansion definition module state, the input/output port state and the local fault logic relation; and finally, forming a full-system fault propagation graphical and mathematical model based on the internal interactive relation and the mathematical expression of different levels of the system, and identifying a key hardware fault mode causing the top-level function failure.
The invention has the innovation points that the fault propagation relations of different levels of the system are visually and clearly displayed in a graphical mode, and the fault logic relations of different levels of the system are accurately expressed in a mathematical model mode, so that the problem that the fault mode of the whole system affects the analysis work is solved, and the key fault mode of the system is accurately positioned.
The method comprises the following steps: architecture model construction
(1) Defining and dividing convention layers, wherein the convention layers comprise a system, a subsystem, an external field Replaceable Unit (LRU), an internal field Replaceable Unit (SRU), a functional circuit and components, the system is a layer 1, the subsystem is a layer 2, and so on, the external field Replaceable Unit is a layer 3, the internal field Replaceable Unit is a layer 4, the functional circuit is a layer 5, and the components are a layer 6;
(2) And (3) system model construction, namely constructing a graph and a mathematical model on the basis of module elements, wherein the construction content comprises a system module, system output port information and a system function state. System setting module N C By { F I c ，F O c ，S c And dom } is represented by I c Presentation System Module N C Input port of (2), F O c Presentation System Module N C Output port of, S c Presentation System Module N C Functional space, F I c 、F O c And S c Collectively referred to as system model variantsQuantity, dom is the full set function of dom (x), meaning that all possible values are taken when the variable is x, where x can be taken as the system model variable S c 、F I c 、F O c E.g. dom (S) c ) = F1: normal, F2: normal };
(3) Constructing an internal architecture model, namely constructing a graph and a mathematical model on the basis of module elements aiming at a system, a subsystem, an LRU (least recently used) module and an SRU (remote unit) module, wherein the constructed content comprises each level of composition units, component input/output port information and component state information; for a functional circuit module, components included in the functional circuit are constructed on the basis of module elements, but port information is not constructed. Let the ith product node N ij With { F I ij ，F O ij ，S ij Dom } is represented by, wherein F I ij Denotes the input port of the jth internal module of the ith layer, F O ij Output port of jth inner module of ith layer, S ij The module is expressed in a normal function state, and the last layer of component module only needs to define the state S 6j 。F I ij 、F O ij And S ij Collectively referred to as internal module model variables, where dom is also the full set of functions of dom (x), but those skilled in the art will recognize that x is an internal module model variable and dom represents all possible values taken for the internal module model variable;
(4) Constructing an interactive relation of internal modules, namely constructing graphs aiming at the subsystems, the LRU, the SRU and the functional circuit modules according to the signal transmission relation among the modules and reflecting the interactive relation of input and output ports of each module; for each module mathematical model, assumptions can be given
Wherein p is i Is a module N ij Number of input ports of q j Is a module N ij The number of output ports of (a),
the representing module N ij The p-th input port of (a),
the representing module N ij The qth output port of (1). If the module N ij Q th output port of (2)
And module N ik P th input port of (2)
When connected, the connection relationship of the ports is defined as
(5) Constructing a connection relation between a component port and a system port, and graphically constructing a connection relation between a subsystem port and a system port on the basis of a signal transmission relation between modules aiming at a system and subsystem modules; for the module mathematical model, if the system module N is divided 2j Is connected to the input port
And system module N C Is connected to the input port
Are connected, the mathematical relationship between the two is defined as
If subsystem module N 2j Of the output port
And system module N c Of the output port
Are connected, the mathematical relationship between the two is defined as
That is to say, the input port of the subsystem module is nowThe output port of the subsystem module is the output port of the system module.
In this embodiment, a system architecture model is constructed:
firstly, a system module named as 'XX system' is constructed, and system output port information and functions thereof are constructed; shown in FIG. 2a as { F } I c ，F O c ，S c And dom represents N C Module of which dom (F) O c ) = signal 1, signal 2, dom (S) c ) = function 1: normal, function 2: normal }.
And then, taking the system architecture composition as input, constructing a system architecture model, defining each subsystem module, input/output port information, function definition and interaction relation thereof, and keeping port definition between cross-layer levels consistent. Shown in FIG. 2b, with { F } I 21 ，F O 21 ，S 21 Dom represents subsystem A with { F } I 22 ，F O 22 ，S 22 Dom represents subsystem B with { F } I 23 ，F O 23 ，S 23 And dom represents subsystem C. Wherein dom (F) O 21 ) = signal 3, signal 4, dom (S) 21 ) = function 3: normal, function 4: normal }; dom (F) O 22 ) = signal 5, signal 6, dom (S) 22 ) = function 5: normal, function 6: normal }; dom (F) I 23 ) = { signal 3, signal 4, signal 5, type 6}, dom (F) O 23 ) = signal 7, signal 8, dom (S) 23 ) = function 7: normal, function 8: normal }.
And then, constructing architecture models of the subsystems, the LRU and the SRU levels in the same modeling mode, and representing the architecture composition and unit interaction relationship of the subsystems, the LRU and the SRU.
Finally, for the functional circuit module, the architecture model is constructed according to the hardware composition, and the diagram is shown in fig. 2 c. With { S 61 Dom represents the resistance 1, { S } 62 Dom represents the resistance 2, { S } 63 Dom represents the capacitance 1, { S } 63 And dom represents an integrated chip, wherein dom (S) 61 ) = function 9: normal }, dom (S) 62 ) = function 10: normal }, dom (S) 63 ) = function 11: normal }, dom (S) 64 ) = function 12: normal }.
Step two: fault propagation model construction
(1) The system function failure state is defined aiming at the system module N C S in (1) C The state element is defined in an extension way, and the constructed content is the fault state of each function of the system, such as dom (S) c ) = F1: normal, F1: loss of function, F2: normal, F2: functional abnormality };
(2) Component failure mode definition, composing modules N for each hierarchy ij S in (1) ij And carrying out extension definition on the state elements, and constructing the content as the failure mode of each component. The failure mode may be a functional failure mode or a hardware failure mode, such as dom (S) depending on the development stage or product level 6j ) = F3: normal, F3: open circuit, F3: parameter drift, F4: normal, F4: open circuit, F4: short circuit, F4: parameter drift };
(3) The module port expansion definition of each layer is specific to the system module, subsystem, LRU, SRU and functional circuit module port variable F I ij 、F O ij Using enumerated types to define normal and abnormal outputs explicitly, e.g.
(4) And establishing a fault propagation model of each module represented in a fault tree form, namely adopting the fault tree form for the fault propagation model of each module. Aiming at a system module, describing a logical combination relation of a system function failure state and an output port failure state thereof in a fault tree graphical mode; aiming at the subsystems, the LRU, the SRU module and the functional circuit module, the logic combination relationship (such as AND gate and OR gate) between the failure state of the output port of the component module, the failure state of the input port of the module and the failure state of the module is described in a fault tree graphical mode; to is directed atAnd the lowest layer module takes the function fault mode of the functional circuit as a top event in consideration of the worst condition, the hardware fault mode of each component, which causes the function fault mode, is taken as a bottom event, and all the bottom events are connected by an OR gate to form a fault propagation model represented by a fault tree form. For system module N C 、N ij A variable sigma is added in the mathematical model and used for describing the influence relationship of the current module state variable and the input value on an output port, and the influence relationship is expressed as follows:
where o denotes an and logic, which may be replaced with #/u depending on the specific logical relationship,
is a system module N C The output port of (a) is connected to the output port,
is a module N ij P th input port, state C (state C ∈dom(S C ) Is N) C State space of (2) ij (state ij ∈dom(S ij ) Is N) ij A state space of (a);
the representing module N C A port is represented by a function in logical combination with or,
the representing module N ij State of the function whose input port is represented by being logically combined with ij The representing module N ij A function whose state is represented by an and or logical combination. In the process of establishing the fault propagation model of each module, the fault logic relationship between the components and the system is kept consistent, and according to the cross-hierarchy port connection relationship of the system, the system level input port and the system level preamble module output and the system are simultaneously connectedThe input ports of the corresponding component units in the system are connected, and the system-level output ports are simultaneously connected with the input ports of the subsequent modules in the system and the output ports of the corresponding component units in the system, so that the consistency of the state and the fault logic definition among the three modules is kept in the modeling process.
(5) Traversing all module fault propagation models, replacing the input failure state received by each module by the output port failure state fault tree corresponding to other modules, and synthesizing a full-system fault propagation graphical model taking the self function failure state of the system as a top event and the self failure state of the module as a bottom event; aiming at each module mathematical model, if the modules are connected with the same level, the mathematical model meets the requirements
Then there is
If the connection of the cross-layer module is satisfied
Then there is
Final σ (state) C ) Expressed as: σ (state) C )＝◇state ij ；
In this embodiment, a fault propagation model of a certain system is constructed:
firstly, aiming at each module function, the function failure mode is defined by state expansion. For each module output port, the failure state of the output information is defined by port type expansion, such as no signal output, signal over-limit, large signal deviation, etc., as shown in fig. 3a, dom (S) c ) = F1: normal, F1: loss, F1: non-instruction execution, F2: normal, F2: loss, F2: non-instruction execution },
then, aiming at the component module, the hardware failure mode is defined by state expansion,the illustration is as shown in fig. 3 b. dom (S) 61 ) = function 9: normal, function 9: parameter drift, function 9: open }, dom (S) 62 ) = function 10: normal, function 10: parameter drift, function 10: open }, dom (S) 63 ) = function 11: normal, function 11: parameter drift, function 11: open circuit, function 11: short }, dom (S) 64 ) = function 12: normal, function 12: electrical failure, function 12: output error, function 12: no output }.
Then, states of output ports and input ports of the modules and a self functional fault mode are described through a fault tree form, as shown in fig. 4a, a fault propagation model of the subsystem a is shown, and as shown in fig. 4b, a fault propagation model of the subsystem C is shown. It also defines the logical relationship between the system functional failure mode and its output port failure status, and the model is shown in fig. 5. Sigma c (function 1: non-instruction execution) = signal 1: instruction error, σ 21 (signal 3: no instruction error) = function 3: non-instruction execution, σ 23 (signal 7: instruction error) = (signal 3: instruction error) — u ((signal 5: instruction error) — n (function 7: non-instruction execution)).
And then constructing a fault propagation model represented in a fault tree form mode aiming at the component module. The effect on the functional circuit of the previous stage is analyzed according to the hardware failure mode defined in fig. 3 (b), as shown in table 1. According to the analysis result, the hardware fault mode causing the functional circuit A, the signal processing function and the error comprises the parameter drift of the resistor 1, the parameter drift of the resistor 2, the parameter drift of the capacitor 1 and the output error of the integrated chip, and the equivalent fault propagation model is represented as shown in figure 6, wherein sigma is 51 (signal processing function: error) = (resistance 1: parametric drift) < u (resistance 2: parametric drift) < u (capacitance 1: parametric drift) < u (integrated chip: electrical output error).
TABLE 1 analysis of hardware failure mode impact
Finally, integrating fault trees of all modules to form system faultsA propagation model. As shown in the fault tree of FIG. 4b, the "subsystem A, SIGNAL 3, INSTRUCTION ERROR" bottom event can be replaced by the subtree of FIG. 4a with "subsystem A, SIGNAL 3, INSTRUCTION ERROR" as the top event, and the subsystem C SIGNAL 7 port is connected to the system SIGNAL 1 port, then "SYSTEM SIGNAL 1, INSTRUCTION ERROR" can replace "subsystem C SIGNAL 7, INSTRUCTION ERROR". FIG. 5 shows a fault tree that "system 1 Signal 1 instruction error" may result in "system 1 function 1 non-instruction execution" and the system, subsystem level fault propagation model merge results are shown in FIG. 7. So on, integration to the component level can be replaced, and the result is shown in fig. 8; then, based on the connection relation of each hierarchy module, the method can know
Then there is
Namely satisfy
Then there is
Then sigma c (function 1: non-instruction execution) = (resistance 1: parameter drift) < u (resistance 2: parameter drift) < u (capacitance 1: parameter drift) < u (integrated chip: electrical output error) < u ((signal 5: instruction error) < u (function 7: non-instruction execution)).
Step three: identification of critical hardware failure modes based on system failure propagation model
(1) And based on the fault propagation graphical model, tracing the functional failure state of the topmost module, namely the fault mode influence, caused by the failure state of the bottommost module along the logic gate from bottom to top. In the tracing process, only the fault influence of the OR gate is 'influenced' in the way, and the corresponding hardware fault mode is a key hardware fault mode; the fault influence of the AND gate is 'no influence', and the corresponding hardware fault mode can be ignored;
(2) Based on the mathematical model sigma (state) C ) Boolean function relationship of (1), analysisThe influence of the lowest module state on the system failure state, only if all are U-gates, the mathematical model σ (state) C ) The hardware failure mode in (b) is the key hardware failure mode, and if there is a gate in (n), the failure effect is "no effect", and the corresponding hardware failure mode can be ignored.
(3) And (3) comparing the key hardware fault modes obtained in the steps (1) and (2), if the key hardware fault modes are the same, indicating that the key hardware fault mode is correctly identified, and if the key hardware fault modes are different, indicating that the system fault propagation model is incorrect, returning to the step one, and modeling the system fault propagation model again.
In this embodiment, a process of identifying a critical failure mode of a system:
based on a full-system fault propagation graphical model, the influence of the fault mode of each level module on the functional failure state of the system is analyzed, and then a key fault mode is identified. Because the AND gate represents that when all input events occur, the output event at a higher level occurs, and the output event cannot be influenced when a single event occurs, the fault influence is 'no influence' as long as the AND gate is accessed in the tracing process. The results of the failure mode impact analysis performed based on the system-wide failure propagation model shown in fig. 8 are shown in table 2, and the hardware failure mode (indicated by a dotted line) that causes the non-instruction execution of the system function 1 is located.
TABLE 2 failure mode impact analysis results
Based on sigma c (function 1: non-instruction execution) mathematical analysis formula, the resistance 1: parameter drift, resistance 2: parameter drift, capacitance 1: parameter drift, integrated chip: a single occurrence of an electrical output error results in non-instruction execution of function 1, which is then located as a critical hardware failure mode.
Finally, a graphical model based on fault propagation and a graphical model based on sigma c The key hardware failure modes obtained by the mathematical analytic expression (function 1: non-instruction execution) are all' resistance 1: parameter drift "," resistance 2: parameter drift "," capacitance 1: parameter drift "and" integrated chip: the electrical output error is a critical hardware failure mode, and therefore, the four hardware failure modes are the critical hardware failure modes of the present embodiment.
Finally, it should be noted that: the above-mentioned embodiments are only used for illustrating the technical solution of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (4)
1. A system fault propagation model modeling method is characterized in that: which comprises the following steps:
the method comprises the following steps: architecture model construction
(1) Defining and dividing convention layers, wherein the convention layers comprise a system, a subsystem, an external field replaceable unit, an internal field replaceable unit, a functional circuit and components, and the convention layers are sequentially from a 1 st layer to a 6 th layer;
(2) Constructing a system model, constructing a graph and a mathematical model on the basis of module elements, wherein the constructed content comprises a system module, system output port information and a system function state, and establishing a system module N C By { F I c ，F O c ，S c And dom } is represented by I c Presentation System Module N C Input port of (1), F O c Presentation System Module N C Output port of S c Presentation System Module N C Functional space, F I c 、F O c And S c Collectively called system model variables, dom is the full set function of dom (x), all of which are taken when the variable is represented as xPossible values, where x is the system model variable S c 、F I c 、F O c ；
(3) Constructing an internal architecture model, namely constructing a graph and a mathematical model on the basis of module elements aiming at a system, a subsystem, an LRU (least recently used) module and an SRU (short message Unit) module, wherein the constructed content comprises each level of composition units, component input/output port information and component state information; aiming at a functional circuit module, components contained in the functional circuit are constructed on the basis of module elements, but port information is not constructed, and the ith product node N of the ith layer is set ij By { F I ij ，F O ij ，S ij And dom } is represented by I ij Denotes the input port of the jth internal module of the ith layer, F O ij Represents the output port of the ith inner module, S ij The module is expressed in a normal function state, and the last layer of component module only needs to define the state S 6j ，F I ij 、F o ij And S ij Collectively referred to as internal module model variables, where dom is also a full set function of dom (x), x is an internal module model variable, and dom represents all possible values taken for the internal module model variable;
(4) Constructing an interactive relation of internal modules, namely constructing graphs aiming at the subsystems, the LRU, the SRU and the functional circuit modules according to the signal transmission relation among the modules and reflecting the interactive relation of input and output ports of each module; for each module mathematical model, set
Wherein p is i Is a module N ij Number of input ports of q j Is a module N ij The number of output ports of (a) is,
the representing module N ij The p-th input port of (2),
the representing module N ij The q thAn output port; if the module N ij Q th output port of (2)
And module N ik P th input port of (2)
When connected, the connection relationship about the port is defined as
(5) Constructing a connection relation between a component port and a system port, and graphically constructing a connection relation between a subsystem port and a system port on the basis of a signal transmission relation between modules aiming at a system and subsystem modules; for the module mathematical model, if the system module N is divided 2j Is connected to the input port
And system module N C Is connected to the input port
When they are connected, the mathematical relationship between them is defined as
If subsystem module N 2j Of the output port
And system module N c Of the output port
Are connected, the mathematical relationship between the two is defined as
Step two: fault propagation model construction
(1) Definition of system function failure state aiming at system module N C S in (1) C Carrying out extension definition on the state elements, and constructing the content as each function fault state of the system;
(2) Component failure mode definition, building blocks N for each hierarchy ij S in (1) ij Carrying out extension definition on the state elements, and constructing the content as a fault mode of each component;
(3) The module port expansion definition of each layer is specific to the system module, subsystem, LRU, SRU and functional circuit module port variable F I ij 、F O ij The enumeration type is adopted to clearly define normal output and abnormal output;
(4) Establishing a fault propagation model of each module represented in a fault tree form, and describing a logical combination relation of a system function failure state and an output port failure state thereof in a fault tree graphical form aiming at a system module; aiming at the subsystems, the LRU, the SRU module and the functional circuit module, describing the logical combination relationship of the output port failure state of the component module, the input port failure state of the module and the failure state of the module in a fault tree graphical mode; regarding the lowest layer module, considering the worst condition, taking a functional failure mode of a functional circuit as a top event, taking a hardware failure mode of each component, which causes the functional failure mode of the functional circuit, as a bottom event, and connecting the bottom events by an OR gate to form a failure propagation model represented by a failure tree form; for system module N C 、N ij A variable sigma is added in the mathematical model for describing the influence relationship of the current module state variable and the input value on the output port, and the expression is as follows:
where o denotes and or logic, where n/u replacement may be chosen according to a specific logical relationship,
to be aSystem module N C The output port of (a) is connected to the output port,
is a module N ij P-th input port, state of C (state C ∈dom(S C ) Is N) C State of ij (state ij ∈dom(S ij ) Is N) ij A state space of (a);
representing a module N C The ports are represented by a function in logical combination with or,
the representing module N ij State is a function where the input port is represented by an AND or logical combination ij Representing a module N ij A function whose state is represented by an and or logical combination;
(5) Traversing all module fault propagation models, replacing the input failure state received by each module by the output port failure state fault tree corresponding to other modules, and synthesizing a full-system fault propagation graphical model taking the self function failure state of the system as a top event and the self failure state of the module as a bottom event; aiming at each module mathematical model, if the modules are connected with the same level, the mathematical model meets the requirements
Then there is
If the connection is a connection of cross-layer modules, the connection is satisfied
Then there is
Final σ (state) C ) Expressed as: σ (state) C )＝◇state ij ；
Step three: identification of critical hardware failure modes based on system failure propagation model
(1) Based on the fault propagation graphical model, tracing the functional failure state of the topmost module, which can be caused by the failure state of the bottommost module, from bottom to top along the logic gate, namely the fault mode influence; in the tracing process, only the failure influence of the OR gate is 'influenced' in the way, and the corresponding hardware failure mode is a key hardware failure mode; as long as the fault influence of the approach AND gate is 'no influence', the corresponding hardware fault mode can be ignored;
(2) Based on the mathematical model sigma (state) C ) The boolean function relationship in (1) analyzes the influence of the state of the bottommost module on the state of system functional failure, with only the mathematical model σ (state) being u-gate in all (u) C ) If an n gate exists, the fault influence is 'no influence', and the corresponding hardware fault mode can be ignored;
(3) And (3) comparing the key hardware fault modes obtained in the steps (1) and (2), if the key hardware fault modes are the same, indicating that the key hardware fault mode is correctly identified, and if the key hardware fault modes are different, indicating that the system fault propagation model is incorrect, returning to the step one, and modeling the system fault propagation model again.
2. A method of modeling a system fault propagation model according to claim 1, characterized by: the step (4) in the second step further comprises:
in the process of establishing the fault propagation model of each module, the fault logic relationship between the components and the system is kept consistent, according to the cross-hierarchy port connection relationship of the system, the system-level input port is simultaneously connected with the output of the system-level preamble module and the input port of the corresponding component unit in the system, and the system-level output port is simultaneously connected with the input port of the system-level subsequent module and the output port of the corresponding component unit in the system, so that the consistency of the state and the fault logic definition among the three modules is kept in the modeling process.
3. A method of modeling a system fault propagation model according to claim 1, characterized by: the system function failure state definition in the step (1) in the second step comprises function loss or function abnormity.
4. A method of modeling a system fault propagation model according to claim 1, characterized by: s in step (2) in the second step 6j The fault state is defined as: the resistor is open circuit or parameter drift, the capacitor is open circuit, short circuit or parameter drift, and the integrated chip has electrical property failure, electrical output error or no output.
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