CN111615688A - Assertion verification code binding method and device - Google Patents
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Abstract
A binding method and a device for assertion verification codes are provided, the method comprises the following steps: determining module identifications, position information and interface information corresponding to a plurality of modules of the chip, when receiving a search instruction aiming at a target module, searching the position information and the interface information corresponding to the target module according to the module identification of the target module, and binding the target module and a corresponding assertion verification code according to the position information and the interface information of the target module. When a search instruction for a target module needing to bind the assertion verification code is received, the position information and the interface information corresponding to the target module are automatically searched, so that the position added by the subsequent assertion verification code is not easy to make mistakes, and the target module and the corresponding assertion verification code are bound according to the position information and the interface information of the target module, so that the workload of artificially binding the assertion verification code and the target module is reduced, and the binding efficiency is improved.
Description
Technical Field
The invention relates to the technical field of computers, in particular to an assertion verification code binding method and device.
Background
With the improvement of the chip design flow, the verification link gradually becomes an important link in the chip design flow, and after the chip design is completed, in order to check abnormal conditions and check whether some scenes are covered or not in the simulation process, assertion verification codes are often required to be added into modules inside the chip, and the assertion verification codes are bound with target modules.
Assertion verification is a programming term, expressed as a number of boolean expressions, that a programmer believes at a certain point in a program that the expression value is true, and assertion verification may be enabled and disabled at any time, so assertion verification may be enabled at test time and disabled at deployment time. Likewise, after the program is put into operation, the end user may re-enable assertion verification when a problem is encountered.
In the prior art, position information and interface information of each module to which an assertion verification code needs to be bound are obtained by a manual searching method, then the assertion verification code is manually written at a corresponding position of the module according to the position information, and the binding between the assertion verification code and a target module is realized based on the interface information.
However, the same module in the chip design may be instantiated for many times, the instantiated module is a module with the same function and is arranged at different positions in the chip, and the position of the instantiated module is difficult to find, so that when the assertion verification code is added, the position where the assertion verification code is added is prone to error, different target modules are bound with different assertion verification codes manually, the workload is large, and the working efficiency is low.
Disclosure of Invention
In order to solve technical problems in the prior art, embodiments of the present invention provide a method and an apparatus for binding an assertion verification code, so as to solve problems in the prior art that an error is easily caused in a position where the assertion verification code is added, and a workload for binding the assertion verification code is large.
In a first aspect, an embodiment of the present invention provides a method for binding assertion verification codes, including:
determining module identifications, position information and interface information corresponding to a plurality of modules of a chip;
when a search instruction for a target module is received, searching position information and interface information corresponding to the target module according to a module identifier of the target module;
and binding the target module with the corresponding assertion verification code according to the position information and the interface information of the target module.
In a second aspect, an embodiment of the present invention provides an assertion verification code binding apparatus, including:
the module information determining module is used for determining module identifications, position information and interface information corresponding to a plurality of modules of the chip;
the module information searching module is used for searching the position information and the interface information corresponding to the target module according to the module identification of the target module when receiving a searching instruction aiming at the target module;
and the assertion binding module is used for binding the target module and the corresponding assertion verification code according to the position information and the interface information of the target module.
In a third aspect, an embodiment of the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the assertion verification code binding method when executing the computer program
In a fourth aspect, the present invention provides a computer-readable storage medium, where program instructions are stored, and when the program instructions are executed by a processor, the program instructions are used to execute the assertion verification code binding method.
In the embodiment of the invention, by determining the module identifiers, the position information and the interface information corresponding to a plurality of modules of the chip, when a search instruction for a target module is received, the position information and the interface information corresponding to the target module are searched according to the module identifier of the target module, and the target module and the corresponding assertion verification code are bound according to the position information and the interface information of the target module. When a search instruction for a target module needing to bind the assertion verification code is received, the position information and the interface information corresponding to the target module are automatically searched, so that the position added by the subsequent assertion verification code is not easy to make mistakes, and the target module and the corresponding assertion verification code are bound according to the position information and the interface information of the target module, so that the workload of artificially binding the assertion verification code and the target module is reduced, and the binding efficiency is improved.
Drawings
FIG. 1 is a flow chart illustrating a method for assertion verification code binding according to a first embodiment of the present invention;
FIG. 2 is a flow chart illustrating a method for assertion verification code binding according to a second embodiment of the present invention;
FIG. 3 is a block diagram showing a configuration of an assertion verification code binding apparatus according to a third embodiment of the present invention;
fig. 4 is a block diagram showing another assertion verification code binding apparatus according to a third embodiment of the present invention.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, a flowchart of a method for binding assertion verification code according to a first embodiment of the present invention is shown, which specifically includes the following steps:
step S101, determining module identifications, position information and interface information corresponding to a plurality of modules of a chip.
A plurality of modules, such as a FIFO (First Input First Output) module, a RAM (Random Access Memory) module, an ARBITER module, a calculator module, and the like, are usually integrated inside the chip.
In chip design, a developer stores codes involved in the whole chip design in a chip file list, where the chip file list includes not only codes of each module integrated inside a chip, but also other related codes, such as interaction codes between modules, specifically, the codes of each module include a module identifier and interface information of the module, the interface information of the module includes an interface name of the module, configuration parameters of the interface, and other related parameters, and the module identifier may be represented by the module name.
In a chip design, a certain hierarchical structure exists between modules, and generally, a top-level module includes a plurality of sub-modules, and each sub-module can nest a plurality of sub-modules, so that the position information of a module is generally represented by a path of the module.
For example, the top module is module a, the top module includes a plurality of sub-modules B1, B2 and B3, sub-module B1 nests sub-module C1, and therefore, the position information of sub-module C1 is represented by a path "module a-sub-module B1-sub-module C1".
And determining module identifications, position information and interface information corresponding to a plurality of modules of the chip in the chip file list.
Step S102, when a search instruction for a target module is received, according to the module identification of the target module, the position information and the interface information corresponding to the target module are searched.
In practical applications, not all modules of the chip need to bind the assertion verification code, and therefore, a plurality of modules in the chip can be divided into two types, one type is a target module, and the other type is a non-target module.
It should be noted that the division standards of the target module and the non-target module are set according to the design requirements of the chips by developers, and the division standards of the chips may be the same or different; the target module refers to a module that needs to bind the assertion verification code, and the non-target module refers to a module that does not need to bind the assertion verification code.
And when a searching instruction aiming at the target module is received, searching the position information and the interface information corresponding to the target module according to the module identification of the target module.
The position information and the interface information corresponding to the target module are automatically searched, errors are not prone to occurring, even if the target module is instantiated for multiple times, the position of the instantiated target module can be searched, and therefore errors are not prone to occurring in the position where the assertion verification code is added when the assertion verification code is added subsequently.
Wherein the target module comprises: at least one of FIFO module, RAM module, ARBITER module, and counter module.
And step S103, binding the target module and the corresponding assertion verification code according to the position information and the interface information of the target module.
According to different modules, developers can write assertion verification codes corresponding to the modules, the assertion verification codes comprise assertion codes and assertion coverage rate codes, the assertion codes are used for verifying whether a corresponding target module is abnormal or not during chip simulation, when the abnormality occurs, the assertion codes can give an alarm, and the assertion coverage rate codes are used for detecting whether a scene needing to be verified in the target module is covered or not after the chip simulation is finished.
For example, the target module is a counter in a chip, the count value of the counter is 1 to 100, during simulation, when the assertion code detects the count value 101, it is determined that the counter is abnormal, after the simulation is finished, the assertion coverage rate code counts the count value of the actually detected counter, it is determined that the assertion coverage rate of the counter is determined, if the detected count values of the counter are 1, 10 and 100, it means that the assertion coverage rate is 3%, and it is determined whether a scene needing to be verified is covered according to the assertion coverage rate.
Acquiring an assertion verification code corresponding to the target module, determining the position where the assertion verification code needs to be inserted according to the position information of the target module, and connecting the assertion verification code with the interface of the target module according to the interface information of the target module, thereby realizing the binding of the assertion verification code and the target module.
By automatically acquiring the assertion verification code corresponding to the target module and binding the assertion verification code with the target module, the workload of artificially binding the assertion verification code with the target module is reduced, and the binding efficiency is improved.
When the module in the chip is simulated, the target module can be verified by using the assertion verification code bound with the target module.
As can be seen from the above, the assertion verification code binding method provided in the embodiment of the present invention has at least the following technical effects:
in the embodiment of the invention, by determining the module identifiers, the position information and the interface information corresponding to a plurality of modules of the chip, when a search instruction for a target module is received, the position information and the interface information corresponding to the target module are searched according to the module identifier of the target module, and the target module and the corresponding assertion verification code are bound according to the position information and the interface information of the target module. When a search instruction for a target module needing to bind the assertion verification code is received, the position information and the interface information corresponding to the target module are automatically searched, so that the position added by the subsequent assertion verification code is not easy to make mistakes, and the target module and the corresponding assertion verification code are bound according to the position information and the interface information of the target module, so that the workload of artificially binding the assertion verification code and the target module is reduced, and the binding efficiency is improved.
Referring to fig. 2, a flowchart of a method for binding assertion verification code according to a second embodiment of the present invention is shown, which specifically includes the following steps:
step S201, providing an assertion code library, in which assertion verification codes respectively corresponding to the plurality of modules and assertion identifications corresponding to each assertion verification code are stored.
For different modules, developers can write assertion verification codes corresponding to the modules and store the assertion verification codes in an assertion code library, wherein the assertion verification codes respectively corresponding to a plurality of modules are stored in the assertion code library; of course, when writing the assertion verification codes, a unique assertion identifier may be set for each assertion verification code, that is, the assertion identifier corresponding to each assertion verification code is stored in the assertion code library in addition to the assertion verification codes respectively corresponding to the plurality of modules.
After storing the written assertion verification code and the corresponding assertion identification in the assertion code library, the written assertion code library may be obtained.
It should be noted that the assertion identifier corresponds to the module identifier of the target module, and is used for facilitating the subsequent call of the assertion verification code; of course, it will be appreciated that the assertion identification may also be represented by the module name of the target module.
Step S202, according to module identifications of a plurality of modules of the chip, a VERDI tool is adopted to search the position information and the interface information of the plurality of modules from a chip file list.
Generally, the module identifier of each module in the chip has uniqueness, and because the VERDI tool can analyze the chip file list, therefore, the module identifiers of the modules of the chip can be sequentially input into the VERDI tool, the chip file list is analyzed by the VERDI tool, and the position information and the interface information of the module corresponding to the module identifier are searched from the chip file list, so that the position information and the interface information of a plurality of modules are obtained.
Step S203, storing the module identifiers, the location information, and the interface information of the plurality of modules in a target file.
And storing the searched position information and interface information of the plurality of modules in a target file, and correspondingly, storing the module identifications corresponding to the modules in the target file. The target file may include a module identifier, location information of the module, and interface information of the module, and the format of the target file may be txt format.
Step S204, when a search instruction for the target module is received, reading corresponding position information and interface information from the target file according to the module identification of the target module.
And when a search instruction for the target module is received, reading the position information and the interface information corresponding to the target module from the target file according to the module identification of the target module.
Wherein the target module comprises: at least one of FIFO module, RAM module, ARBITER module, and counter module.
Step S205, matching the module identifier of the target module with the assertion identifier in the assertion code library.
And matching the module identifier of the target module with each assertion identifier in the assertion code library, and determining assertion verification codes corresponding to the assertion identifiers which are successfully matched, namely determining the assertion verification codes which need to be bound by the target module.
For example, the target module is a FIFO (First Input First Output) module, a module identifier of the target module is FIFO, the assertion code library includes assertion verification code 1, assertion verification code 2 and assertion verification code 3, the assertion verification code 1 is used to verify the FIFO module, the assertion verification code 2 is used to verify the RAM module, the assertion verification code 3 is used to verify the ARBITER module, the assertion identifier of the assertion verification code 1 is 0001, the assertion identifier of the assertion verification code 2 is 0002, the assertion identifier of the assertion verification code 3 is 0003, the module identifier FIFO of the target module is matched with each assertion identifier in the assertion code library, and if the matched assertion identifier is 0001, it is determined that the assertion verification code to be bound is assertion verification code 1 from the assertion code library.
Step S206, the assertion verification code corresponding to the assertion identification successfully matched is called from the assertion code library.
And after determining the assertion verification codes needing to be bound by the target module, calling the assertion verification codes corresponding to the successfully matched assertion identifications from the assertion code library.
Step S207, connecting the assertion verification code with the interface of the target module according to the location information and the interface information of the target module.
Determining the position of the assertion verification code to be inserted according to the position information of the target module, and connecting the assertion verification code with the interface of the target module according to the interface information of the target module, so as to realize the binding of the assertion verification code and the target module; in particular, the assertion verification code may be interfaced with the target module using a bind command.
Although the assertion verification codes in the assertion code library are also manually written, in subsequent applications, when the assertion verification codes are found to be wrongly written, the assertion verification codes can be manually corrected, after multiple verification and use by multiple users, the assertion verification codes in the assertion code library are more accurate, when the assertion verification codes in the assertion code library are called and are connected with an interface of a target module, the assertion verification codes are accurate, so that the problem that errors are easy to occur when the assertion verification codes are manually added to the target module is solved, when the same target module is instantiated, the assertion verification codes in the assertion code library are directly called without copying the assertion verification codes, and errors in the copying process are avoided.
In the embodiment of the invention, an assertion code library is provided, position information and interface information of a plurality of modules are searched from a chip file list by adopting a VERDI tool according to module identifiers of the modules of a chip, the module identifiers, the position information and the interface information of the modules are stored in a target file, when a search instruction aiming at the target module is received, the corresponding position information and the corresponding interface information are read from the target file according to the module identifier of the target module, the module identifier of the target module is matched with the assertion identifiers in the assertion code library, assertion verification codes corresponding to the assertion identifiers which are successfully matched are called from the assertion code library, and the assertion verification codes are connected with an interface of the target module according to the position information and the interface information of the target module. The VERDI tool is adopted to search the position information and the interface information of the modules from the chip file list and store the position information and the interface information into the target file, so that the problem that the positions of the modules are easy to make mistakes when being manually searched is avoided, the assertion verification codes are automatically called from the assertion code library through the module identification of the target module, and the assertion verification codes are connected with the interfaces of the target module according to the position information and the interface information, so that the workload of manually binding the assertion verification codes and the target module is reduced, and the binding efficiency is improved; and when the same target module is instantiated, the assertion verification code does not need to be copied, and the assertion verification code in the assertion code library is directly called, so that errors in the copying process are avoided.
Referring to fig. 3, which shows a block diagram of a assertion verification code binding apparatus according to a third embodiment of the present invention, the assertion verification code binding apparatus 300 may include:
a module information determining module 301, configured to determine module identifiers, location information, and interface information corresponding to multiple modules of a chip;
a module information search module 302, configured to search, when a search instruction for a target module is received, location information and interface information corresponding to the target module according to a module identifier of the target module;
and the assertion binding module 303 is configured to bind the target module and the corresponding assertion verification code according to the location information and the interface information of the target module.
Referring to fig. 4, there is shown a block diagram of another assertion verifying code binding apparatus according to a third embodiment of the present invention.
On the basis of fig. 3, optionally, the assertion verification code binding apparatus 300 further includes:
an assertion code library providing module 304, configured to provide an assertion code library, in which assertion verification codes respectively corresponding to the plurality of modules and assertion identifications corresponding to each of the assertion verification codes are stored.
Optionally, the assertion binding module 303 includes:
an identity matching submodule 3031, configured to match a module identity of the target module with an assertion identity in the assertion code library;
the assertion calling submodule 3032 is configured to call, from the assertion code library, an assertion verification code corresponding to the assertion identifier that is successfully matched;
and the assertion binding submodule 3033 is configured to connect the assertion verification code with the interface of the target module according to the location information and the interface information of the target module.
Optionally, the module information determining module 301 includes:
the module information searching submodule 3011 is configured to search, according to module identifiers of multiple modules of a chip, location information and interface information of the multiple modules from a chip file list by using a VERDI tool;
and a module information storing sub-module 3012, configured to store the module identifiers, the location information, and the interface information of the modules in a target file.
Optionally, the module information searching module 302 includes:
the module information reading sub-module 3021 is configured to, when a search instruction for a target module is received, read corresponding location information and interface information from the target file according to a module identifier of the target module.
Optionally, the target module includes: at least one of FIFO module, RAM module, ARBITER module, and counter module.
In the embodiment of the invention, by determining the module identifiers, the position information and the interface information corresponding to a plurality of modules of the chip, when a search instruction for a target module is received, the position information and the interface information corresponding to the target module are searched according to the module identifier of the target module, and the target module and the corresponding assertion verification code are bound according to the position information and the interface information of the target module. When a search instruction for a target module needing to bind the assertion verification code is received, the position information and the interface information corresponding to the target module are automatically searched, so that the position added by the subsequent assertion verification code is not easy to make mistakes, and the target module and the corresponding assertion verification code are bound according to the position information and the interface information of the target module, so that the workload of artificially binding the assertion verification code and the target module is reduced, and the binding efficiency is improved.
Accordingly, an embodiment of the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the assertion verification code binding method when executing the computer program.
Embodiments of the present invention further provide a computer-readable storage medium, in which program instructions are stored, and when the program instructions are executed by a processor, the program instructions are configured to perform the assertion verification code binding method.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The assertion verification code binding method and device provided by the invention are introduced in detail, and a specific example is applied in the text to explain the principle and the implementation manner of the invention, and the description of the embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (14)
1. A method of assertion verification code binding, comprising:
determining module identifications, position information and interface information corresponding to a plurality of modules of a chip;
when a search instruction for a target module is received, searching position information and interface information corresponding to the target module according to a module identifier of the target module;
and binding the target module with the corresponding assertion verification code according to the position information and the interface information of the target module.
2. The method of claim 1, further comprising, prior to the step of binding the target module with a corresponding assertion verification code based on the location information and the interface information of the target module:
providing an assertion code library, wherein assertion verification codes respectively corresponding to the modules and assertion identifications corresponding to each assertion verification code are stored in the assertion code library.
3. The method of claim 2, wherein the step of binding the target module with a corresponding assertion verification code based on the location information and the interface information of the target module comprises:
matching the module identification of the target module with the assertion identification in the assertion code library;
calling an assertion verification code corresponding to the successfully matched assertion identification from an assertion code library;
and connecting the assertion verification code with the interface of the target module according to the position information and the interface information of the target module.
4. The method of claim 1, wherein the step of determining module identifications, location information, and interface information corresponding to the plurality of modules of the chip comprises:
according to module identifications of a plurality of modules of the chip, searching position information and interface information of the modules from a chip file list by using a VERDI tool;
storing the module identification, the location information, and the interface information of the plurality of modules in a target file.
5. The method according to claim 4, wherein the step of finding the location information and the interface information corresponding to the target module according to the module identifier of the target module when receiving the finding instruction for the target module comprises:
and when a searching instruction aiming at the target module is received, reading corresponding position information and interface information from the target file according to the module identification of the target module.
6. The method of any one of claims 1 to 5, wherein the target module comprises: at least one of FIFO module, RAM module, ARBITER module, and counter module.
7. An assertion authentication code binding apparatus comprising:
the module information determining module is used for determining module identifications, position information and interface information corresponding to a plurality of modules of the chip;
the module information searching module is used for searching the position information and the interface information corresponding to the target module according to the module identification of the target module when receiving a searching instruction aiming at the target module;
and the assertion binding module is used for binding the target module and the corresponding assertion verification code according to the position information and the interface information of the target module.
8. The apparatus of claim 7, further comprising:
and the assertion code library providing module is used for providing an assertion code library, and assertion verification codes respectively corresponding to the modules and assertion identifications corresponding to each assertion verification code are stored in the assertion code library.
9. The apparatus of claim 8, wherein the predicate binding module comprises:
the identification matching submodule is used for matching the module identification of the target module with the assertion identification in the assertion code library;
the assertion calling submodule is used for calling assertion verification codes corresponding to the successfully matched assertion identifications from the assertion code library;
and the assertion binding submodule is used for connecting the assertion verification code with the interface of the target module according to the position information and the interface information of the target module.
10. The apparatus of claim 7, wherein the module information determining module comprises:
the module information searching submodule is used for searching the position information and the interface information of a plurality of modules from a chip file list by adopting a VERDI tool according to the module identifications of the modules of the chips;
and the module information storage submodule is used for storing the module identifications, the position information and the interface information of the modules in a target file.
11. The apparatus of claim 10, wherein the module information lookup module comprises:
and the module information reading sub-module is used for reading corresponding position information and interface information from the target file according to the module identification of the target module when receiving a search instruction aiming at the target module.
12. The apparatus of any of claims 7 to 11, wherein the target module comprises: at least one of FIFO module, RAM module, ARBITER module, and counter module.
13. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the assertion verification code binding method of any one of claims 1 to 6 when executing the computer program.
14. A computer-readable storage medium having stored therein program instructions for execution by a processor to perform the assertion verification code binding method as claimed in any one of claims 1 to 6.
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| PCT/CN2019/088850 WO2020237508A1 (en) | 2019-05-28 | 2019-05-28 | Assertion validation code binding method and apparatus |
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| CN (1) | CN111615688A (en) |
| WO (1) | WO2020237508A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112364581A (en) * | 2020-11-13 | 2021-02-12 | 上海兆芯集成电路有限公司 | Method and device for automatically inserting specific code into register transmission level design file |
| CN112364580A (en) * | 2020-11-13 | 2021-02-12 | 上海兆芯集成电路有限公司 | Method and device for automatically inserting specific code into register transmission level design file |
| CN115114135A (en) * | 2021-03-17 | 2022-09-27 | 中国联合网络通信集团有限公司 | Software data testing method, device, equipment, medium and product |
| CN116627846A (en) * | 2023-07-20 | 2023-08-22 | 北京云枢创新软件技术有限公司 | Method, electronic device and medium for determining position information of target call identifier |
| CN117472670A (en) * | 2023-11-09 | 2024-01-30 | 紫光同芯微电子有限公司 | Method, device, system and medium for assertion verification management in chip verification |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060271890A1 (en) * | 2005-05-24 | 2006-11-30 | Amir Hekmatpour | Systems, methods, and media for block-based assertion generation, qualification and analysis |
| CN101055523A (en) * | 2006-06-01 | 2007-10-17 | 威盛电子股份有限公司 | Method for exchanging software program code to hardware described language program code |
| CN103020396A (en) * | 2012-12-31 | 2013-04-03 | 青岛中星微电子有限公司 | Method and device for automatic generating assertion |
| US9501598B1 (en) * | 2014-09-22 | 2016-11-22 | Cadence Design Systems, Inc. | System and method for assertion publication and re-use |
| CN107016189A (en) * | 2017-04-05 | 2017-08-04 | 广东浪潮大数据研究有限公司 | It is a kind of that the method asserted and be automatically inserted into RTL is realized based on perl |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7711536B2 (en) * | 2005-12-30 | 2010-05-04 | Cadence Design Systems, Inc. | System and method for verification aware synthesis |
| CN103019745B (en) * | 2012-12-31 | 2015-10-21 | 青岛中星微电子有限公司 | A kind of method that automatic generation is asserted and device |
-
2019
- 2019-05-28 WO PCT/CN2019/088850 patent/WO2020237508A1/en active Application Filing
- 2019-05-28 CN CN201980008861.5A patent/CN111615688A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060271890A1 (en) * | 2005-05-24 | 2006-11-30 | Amir Hekmatpour | Systems, methods, and media for block-based assertion generation, qualification and analysis |
| CN101055523A (en) * | 2006-06-01 | 2007-10-17 | 威盛电子股份有限公司 | Method for exchanging software program code to hardware described language program code |
| CN103020396A (en) * | 2012-12-31 | 2013-04-03 | 青岛中星微电子有限公司 | Method and device for automatic generating assertion |
| US9501598B1 (en) * | 2014-09-22 | 2016-11-22 | Cadence Design Systems, Inc. | System and method for assertion publication and re-use |
| CN107016189A (en) * | 2017-04-05 | 2017-08-04 | 广东浪潮大数据研究有限公司 | It is a kind of that the method asserted and be automatically inserted into RTL is realized based on perl |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112364581A (en) * | 2020-11-13 | 2021-02-12 | 上海兆芯集成电路有限公司 | Method and device for automatically inserting specific code into register transmission level design file |
| CN112364580A (en) * | 2020-11-13 | 2021-02-12 | 上海兆芯集成电路有限公司 | Method and device for automatically inserting specific code into register transmission level design file |
| CN115114135A (en) * | 2021-03-17 | 2022-09-27 | 中国联合网络通信集团有限公司 | Software data testing method, device, equipment, medium and product |
| CN115114135B (en) * | 2021-03-17 | 2024-05-17 | 中国联合网络通信集团有限公司 | Software data testing method, device, equipment, medium and product |
| CN116627846A (en) * | 2023-07-20 | 2023-08-22 | 北京云枢创新软件技术有限公司 | Method, electronic device and medium for determining position information of target call identifier |
| CN116627846B (en) * | 2023-07-20 | 2023-09-22 | 北京云枢创新软件技术有限公司 | Method, electronic device and medium for determining position information of target call identifier |
| CN117472670A (en) * | 2023-11-09 | 2024-01-30 | 紫光同芯微电子有限公司 | Method, device, system and medium for assertion verification management in chip verification |
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| WO2020237508A1 (en) | 2020-12-03 |
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