CN111600606B - Multi-phase clock generation circuit for time interleaved sampling ADC - Google Patents
Multi-phase clock generation circuit for time interleaved sampling ADC Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase
Abstract
The invention relates to a multiphase clock generation circuit for a time interleaving sampling ADC, which belongs to the technical field of clock generation and realizes low clock jitter, low time deviation and low power consumption on the premise of ensuring high speed. The circuit comprises a ring voltage-controlled oscillator, a phase tracking loop circuit and a calibration pulse generating circuit; the annular voltage-controlled oscillator and the phase tracking loop circuit form a PLL loop; the annular voltage-controlled oscillator outputs clock signals of a plurality of phases under the control of a first control voltage output by the phase tracking loop circuit; the calibration pulse generating circuit is connected with the annular voltage-controlled oscillator and is used for outputting a clock calibration signal to the annular voltage-controlled oscillator, adjusting the internal clock of the annular voltage-controlled oscillator and eliminating the influence of clock jitter on an output clock signal. The invention generates the multiphase clock with low jitter, low clock deviation and high precision, and has low power consumption and low hardware cost.
Description
Technical Field
The invention relates to the technical field of clock generation, in particular to a multiphase clock generation circuit for a time interleaving sampling ADC.
Background
Analog-to-Digital Converter (ADC) converts continuous-time and amplitude signals into discrete-time and quantized amplitude signals in a digital processing system. ADC is widely applied to electronic systems such as voice image processor, sonar radar processing system, sensing network, finite infinite communication system, biomedical system, test measuring instrument, etc. Along with the development of technology, miniaturization, mobility and wearing of electronic products become mainstream, low power consumption becomes an important index of electronic products, in addition, the continuous development of a wireless communication system and the explosive growth of information brought by the rapid development of the internet of things bring great challenges to the processing speed and the communication capability of the system. In summary, high-speed, high-precision, low-power ADCs are often the bottleneck for overall system performance.
In recent years, as the research emphasis of high-speed high-precision low-power consumption, the multi-channel time-interleaved ADC is used for synthesizing one channel of high-speed ADC through interleaving of the multi-channel low-speed ADC in a time domain, and the limitation of the speed of a single channel ADC under the same process is broken through. The precision and the power consumption of the multipath time interleaving ADC are also important indexes for measuring the whole ADC. The precision is mainly limited by the performance of a single-channel ADC, offset errors, gain errors, time deviation and the like generated by time interleaving; the power consumption is mainly limited by a single-channel ADC, a driving circuit of reference voltage, a high-speed high-precision multiphase clock generation circuit and the like. At present, the single-channel ADC can ensure good performance under low power consumption, offset errors, gain errors and time deviations generated by time interleaving can be solved by a foreground or background calibration technology, the power consumption of a driving circuit of a reference voltage can be reduced by incompletely establishing errors of a calibration DAC, and a high-speed high-precision low-power consumption multiphase clock generating circuit has no better solution at present. The solution known at present is as follows:
firstly, as shown in fig. 1, a multi-phase clock is generated by frequency division of an external input high-frequency clock through a CML circuit, then the clock level is converted into a CMOS level through a CML-to-CMOS circuit, and the multi-phase sampling clock is finally obtained after the subsequent time deviation adjustment circuit is calibrated. A significant disadvantage of this scheme is that the high-speed clock through external inputs is relatively poor in performance, and when the sampling clock frequency is high, the CML circuit requires a large current to achieve high-speed frequency division, causing the clock circuit power consumption to rise exponentially.
And secondly, as shown in fig. 2, a path of basic clock is generated through a PLL, then a plurality of delay circuits are used for delaying a multi-phase clock, the clock level is converted into the CMOS level through a CML-to-CMOS circuit, and finally the multi-phase sampling clock is obtained after the calibration of a subsequent time deviation adjusting circuit. A significant disadvantage of this approach is that the high speed clock through each delay circuit deteriorates the jitter of the clock, thereby limiting the accuracy of the ADC.
Disclosure of Invention
In view of the above analysis, the present invention aims to provide a multiphase clock generation circuit for a time-interleaved sampling ADC, which achieves low clock jitter, low time bias and low power consumption while ensuring high speed.
The invention discloses a multiphase clock generation circuit for a time interleaving sampling ADC, which comprises a ring voltage-controlled oscillator, a phase tracking loop circuit and a calibration pulse generation circuit;
the annular voltage-controlled oscillator and the phase tracking loop circuit form a PLL loop; the annular voltage-controlled oscillator outputs clock signals of a plurality of phases under the control of a first control voltage output by the phase tracking loop circuit; feeding back a clock signal of one phase to the phase tracking loop circuit to perform phase discrimination with an input reference clock signal, and adjusting the amplitude of the first control voltage to enable the frequencies of the clock signals of a plurality of phases output by the annular voltage-controlled oscillator to be equal to the frequency of the reference clock;
the calibration pulse generating circuit is connected with the annular voltage-controlled oscillator and is used for outputting a clock calibration signal to the annular voltage-controlled oscillator, adjusting the internal clock of the annular voltage-controlled oscillator and eliminating the influence of clock jitter on an output clock signal.
Further, the ring voltage controlled oscillator adjusts a phase difference between clock signals of a plurality of phases according to the input second control voltage.
Further, the ring voltage controlled oscillator comprises a first delay unit, a second delay unit, a third delay unit and a fourth delay unit which are connected into a ring and have the same structure, wherein the output ends OP and ON of the fourth delay unit are respectively connected with the input ends IP and IN of the first delay unit; the output ends OP and ON of the previous delay unit IN the rest delay units connected IN sequence are respectively connected with the input ends IN and IP of the next delay unit;
the phase difference of the signals of the input ends IP and IN of each delay unit is 180 degrees, and the phase difference of the signals of the output ends ON and OP is 180 degrees; the phase difference between the signal of the output terminal OP and the signal of the input terminal IN is 45 °, and the phase difference between the signal of the output terminal ON and the signal of the input terminal IP is 45 °.
Further, the delay unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first normally-on transmission gate, a second normally-on transmission gate, a first variable capacitor group, and a second variable capacitor group;
the output end of the first inverter is connected with the input end of the second inverter; the output end of the third inverter is connected with the input end of the fourth inverter; a first normally-on transmission gate is connected between the input end of the first inverter and the output end of the third inverter in a bridging way; a second normally-on transmission gate is connected between the input end of the third inverter and the output end of the first inverter in a bridging way; the output end of the first inverter and the output end of the third inverter are connected in parallel in a bridging manner through a first variable capacitor group and a second variable capacitor group;
the input end of the first inverter is the input end IN of the delay unit, and the input end of the third inverter is the input end IP of the delay unit; the output end of the second inverter is the output end OP of the delay unit, and the output end of the fourth inverter is the output end ON of the delay unit;
the first variable capacitor group is a voltage-controlled capacitor group, the control end VC of the first variable capacitor group is connected with control voltage, and the frequency of the clock signal output by the delay unit is controlled by controlling the capacitance of the first variable capacitor group;
the second variable capacitor group is a voltage-controlled capacitor group, the control end VT of the second variable capacitor group is connected with control voltage, and the phase of the clock signal output by the delay unit is controlled by controlling the capacitance of the second variable capacitor group.
Further, the control end VC of each delay unit is connected to the first control voltage output by the phase tracking loop circuit, so that the output clock signal frequency of each delay unit is the same as the reference clock signal frequency;
the control terminals VT of the first, second, third and fourth delay units are respectively connected to the second control voltages VTs1, VTs2, VTs3 and VTs4, and respectively adjust the phases of the clock signals output by the delay units.
Further, the ring voltage-controlled oscillator further comprises an NMOS tube, the source electrode and the drain electrode of the NMOS tube are connected between the input ends IN and IP of any delay unit IN a bridging mode, and the grid electrode of the NMOS tube is connected with the output end of the calibration pulse generating circuit.
Further, the ring voltage-controlled oscillator further comprises four NMOS tubes, the four NMOS tubes correspond to the four delay units respectively, and the source electrode and the drain electrode of each NMOS tube are connected between the input ends IN and IP of the corresponding delay units IN a bridging manner; the grid electrode of any one NMOS tube is connected with the output end of the calibration pulse generating circuit, and the grid electrodes of the other three NMOS tubes are grounded.
Further, the calibration pulse generating circuit is connected with a reference clock signal, and outputs a clock calibration signal aligned with the rising edge of the reference clock signal to the grid electrode of the NMOS tube under the enabling of the jitter removal enabling signal;
when the ring voltage-controlled oscillator generates clock jitter, the output potentials of the output ends OP and ON of the delay units bridged by the NMOS tube are unequal, the clock calibration pulse signal enables the NMOS tube to be conducted, and then current flows through the NMOS tube, so that the voltage difference between the output ends OP and ON is reduced to zero, and the zero crossing point of the output clock signal of the ring voltage-controlled oscillator is retimed at the arrival time of the injected clock calibration pulse signal.
Further, the calibration pulse generation circuit comprises a three-input AND gate and a delay inverting module;
the input end of the delay inverting module is connected with a reference clock signal, and the output end of the delay inverting module outputs the reference clock signal which is delayed for set time and inverted;
the first input end of the three-input AND gate is connected with a jitter removal enabling signal; the second input end is connected with a reference clock signal, and the third input end is connected with a reference clock signal which is delayed for a set time and is inverted;
when the debounce enable signal is high, the calibration pulse generation circuit outputs a clock calibration signal having a rising edge aligned with the rising edge of the reference clock signal and a pulse width set to a delay time.
Further, the delay inverting module comprises three inverters which are sequentially connected; the input signal is a reference clock signal, and the output signal is a clock signal with the delay time being the sum of the delay times of three inverters and the phase opposite to the reference clock signal.
The beneficial effects of the invention are as follows:
the frequency of the external input clock signal adopted by the invention is the same as that of the multiphase sampling clock, and a CML frequency dividing circuit is not needed, so that the power consumption of the circuit is large. Meanwhile, the multi-phase clock with low jitter and low clock deviation can be directly generated in the PLL (phase locked loop), an additional delay circuit is not needed, the hardware cost is reduced, the low clock jitter is realized, and the accuracy of the ADC is ensured.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, like reference numerals being used to refer to like parts throughout the several views.
FIG. 1 is a schematic diagram of the connection of the components of a PLL-based clock generation circuit;
FIG. 2 is a schematic diagram showing the connection of conventional clock generation circuits;
FIG. 3 is a schematic diagram showing the connection of the multi-phase clock generating circuit in the embodiment of the invention;
FIG. 4 is a schematic diagram of the connection of the ring voltage controlled oscillators in the embodiment of the invention;
FIG. 5 is a schematic diagram showing the connection of delay units in an embodiment of the invention;
FIG. 6 is a schematic diagram showing the connection of calibration pulse generating circuits according to an embodiment of the invention.
Detailed Description
Preferred embodiments of the present invention are described in detail below with reference to the attached drawing figures, which form a part of the present application and, together with the embodiments of the present invention, serve to explain the principles of the invention.
The present embodiment discloses a multiphase clock generation circuit for a time interleaved sampling ADC, as shown in fig. 3, including a ring voltage controlled oscillator 301 (RVCO), a phase tracking loop circuit 302, and a calibration pulse generation circuit 303;
the annular voltage-controlled oscillator 301 and the phase tracking loop circuit 302 form a PLL loop; the ring voltage-controlled oscillator 301 outputs clock signals of a plurality of phases under the control of the first control voltage VCTRL output from the phase tracking loop circuit 302; the clock signal of any phase is fed back to the phase tracking loop circuit 302 to be compared with the input reference clock signal, and the amplitude of the first control voltage VCTRL is adjusted so that the clock signal frequencies of the phases output by the ring voltage-controlled oscillator 301 are equal to the reference clock frequency.
The ring voltage controlled oscillator 301 also adjusts the phase difference between the clock signals of the plurality of phases according to the second control voltage VTS inputted from the outside.
The calibration pulse generating circuit 303 is connected to the ring voltage controlled oscillator 301, and is configured to output a clock calibration signal to the ring voltage controlled oscillator 301, adjust an internal clock of the ring voltage controlled oscillator 301, and eliminate an influence of clock jitter on an output clock signal.
As shown in fig. 4, the ring voltage controlled oscillator 301 includes 4 delay units and 4 NMOS transistors with the same structure, which are a first delay unit 401, a second delay unit 402, a third delay unit 403, and a fourth delay unit 404, and a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, respectively.
Each delay unit comprises an input terminal IN, an IP, an output terminal OP, ON, a control terminal VC, VT.
Wherein the output terminals OP, ON of the first delay unit 401 are connected to the input terminals IN, IP of the second delay unit 402, respectively; the output terminals OP, ON of the second delay unit 402 are connected to the input terminals IN, IP of the third delay unit 403, respectively; the output terminals OP, ON of the third delay unit 403 are connected to the input terminals IN, IP of the fourth delay unit 404, respectively; the outputs OP, ON of the fourth delay unit 404 are connected to the inputs IP, IN of the first delay unit 401, respectively.
The input ends IN and IP of the first delay unit 401 are connected across the first NMOS transistor; the input ends IN, IP of the second delay unit 402 are connected across the second NMOS transistor; the input ends IN, IP of the third delay unit 403 are connected across the third NMOS transistor; the input terminals IN, IP of the fourth delay unit 404 are connected across the fourth NMOS transistor.
And injecting a clock calibration signal into one gate end of the four NMOS tubes, and grounding the gate ends of the other three NMOS tubes. For example, the gate terminal of the third NMOS transistor is injected with the clock calibration signal INJ. The jitter removal effect of the clock calibration signal INJ injected at the gate terminal of any one NMOS transistor in the ring voltage controlled oscillator 301 is the same,
of course, an NMOS tube is bridged between the input ends IN and IP of any delay unit, and the grid electrode of the NMOS tube is connected with the output end of the calibration pulse generating circuit; and other three NMOS tubes are replaced by other substitute components or circuits to realize parasitic effect matching, and corresponding side jitter removal effect can be realized.
The control terminal VC of each delay unit is connected to the first control voltage VCTRL output from the phase tracking loop circuit 302, and outputs a clock signal having the same frequency as the reference clock signal under the control of the first control voltage VCTRL. And the phase difference of the signals of the input terminals IN, IP is controlled to 180 °, the phase difference of the signal of the input terminal IN and the signal of the output terminal OP is controlled to 45 °, the phase difference of the signal of the input terminal IP and the signal of the output terminal ON is controlled to 45 °, and the phase difference of the signals of the output terminals OP, ON is controlled to 180 °. Thus, the ring voltage controlled oscillator 301 can finally obtain 8 high performance clock signals with phases of 45 ° respectively. Since the 8-phase high-performance clock signal is generated by one phase-locked loop, the time deviation between the multiphase clocks is low.
The control terminals VT of the first, second, third, and fourth delay units 404 are respectively connected to the second control voltages VTs1, VTs2, VTs3, and VTs4, and respectively adjust the phases of the clock signals output by the delay units.
For example, in the case of performing the multi-channel time interleaving ADC, the phase difference of the clock signals required to be connected to each ADC module is strictly required to be 45 °, the phase difference reaching each ADC module may be deviated due to the path delay or other reasons, and the phase difference reaching each ADC module may be 45 ° by adjusting the second control voltages VTS1, VTS2, VTS3, VTS4, respectively, to change the phase of the clock signals outputted from each delay unit.
Specifically, as shown in fig. 5, the schematic circuit diagram of each delay unit includes a first inverter 501, a second inverter 502, a third inverter 503, a fourth inverter 504, a first normally-on transmission gate 505, a second normally-on transmission gate 506, a first variable capacitor group 507, and a second variable capacitor group 508.
The output end of the first inverter 501 is connected with the input end of the second inverter 502; the output end of the third inverter 503 is connected to the input end of the fourth inverter 504; a first normally-on transmission gate 505 is connected between the input end of the first inverter 501 and the output end of the third inverter 503; a second normally-on transmission gate 506 is connected between the input end of the third inverter 503 and the output end of the first inverter 501; a first variable capacitor group 507 and a second variable capacitor group 508 connected in parallel are connected across the output terminal of the first inverter 501 and the output terminal of the third inverter 503;
the input of the first inverter 501 is the input IN of the delay unit, and the input of the third inverter 503 is the input IP of the delay unit; the output end of the second inverter 502 is the output end OP of the delay unit, and the output end of the fourth inverter 504 is the output end ON of the delay unit;
the control terminal VC of the first variable capacitor group 507 is connected to the first control voltage VCTRL, and under the control of the first control voltage VCTRL, the capacitance value of the first variable capacitor group 507 is changed, so that the output clock signal frequency of the ring voltage-controlled oscillator 301 is equal to the input reference clock frequency.
The control terminal VT of the second variable capacitor group 508 of each delay unit is connected to a corresponding second control voltage VTs, and under the control of the second control voltage VTs, the capacitance value of the second variable capacitor group 508 is changed, so as to finely control the phase of each delay unit, and realize the phase deviation adjustment of each phase clock in the ring voltage-controlled oscillator 301.
The calibration pulse generating circuit 303 is connected to the reference clock signal, and outputs a clock calibration signal aligned with the rising edge of the reference clock signal when the jitter removal enable signal is enabled, and the output voltages of the output terminals OP and ON of the second delay unit 402 are not equal due to the high frequency of the input reference clock. When the clock calibration pulse signal arrives, the third NMOS tube is turned ON, if the output voltages of the output terminals OP and ON of the second delay unit 402 are not equal, a current flows through the third NMOS tube, so that the voltage difference between the output terminals OP and ON is reduced to zero, that is, the zero crossing point of the output signal of the ring voltage controlled oscillator 301 is re-timed at the arrival time of the injected clock calibration pulse signal, and the effect of reducing the signal jitter is achieved.
As shown in fig. 6, the calibration pulse generation circuit 303 includes a three-input and gate 601 and a delay inversion module 602;
the input end of the delay inverting module 602 is connected with a reference clock signal, and the output end of the delay inverting module outputs the reference clock signal which is delayed for a set time and inverted;
a first input terminal of the three-input and gate 601 is connected to a jitter removal enabling signal; the second input end is connected with a reference clock signal, and the third input end is connected with a reference clock signal which is delayed for a set time and is inverted;
when the debounce enable signal is high, the calibration pulse generation circuit 303 outputs a clock calibration signal having a rising edge aligned with the rising edge of the reference clock signal and a pulse width that sets the delay time.
Specifically, the delayed inversion module 602 includes three inverters connected in sequence; the input signal is a reference clock signal, and the output signal is a clock signal with the delay time being the sum of the delay times of three inverters and the phase opposite to the reference clock signal.
The input end of the calibration pulse generating circuit 303 is connected to a reference clock signal, monitors the clock jitter of the reference clock signal, outputs a clock calibration signal to the ring voltage-controlled oscillator 301 under the enabling of the jitter removal enabling signal, adjusts the internal clock of the ring voltage-controlled oscillator 301, and eliminates the influence of the reference clock jitter on the output clock signal.
In summary, the frequency of the external input reference clock signal adopted in the embodiment is the same as that of the multiphase sampling clock, and the CML frequency dividing circuit is not required, so that the power consumption of the circuit is large. Meanwhile, the multi-phase clock with low jitter and low clock deviation can be directly generated in the phase-locked loop, an additional delay circuit is not needed, the hardware cost is reduced, the low clock jitter is realized, and the accuracy of the ADC is ensured.
The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention.
Claims (6)
1. A multiphase clock generation circuit for a time interleaved sampling ADC comprising a ring voltage controlled oscillator, a phase tracking loop circuit and a calibration pulse generation circuit;
the annular voltage-controlled oscillator and the phase tracking loop circuit form a PLL loop; the annular voltage-controlled oscillator outputs clock signals of a plurality of phases under the control of a first control voltage output by the phase tracking loop circuit; feeding back a clock signal of one phase to the phase tracking loop circuit to perform phase discrimination with an input reference clock signal, and adjusting the amplitude of the first control voltage to enable the frequencies of the clock signals of a plurality of phases output by the annular voltage-controlled oscillator to be equal to the frequency of the reference clock;
the calibration pulse generating circuit is connected with the annular voltage-controlled oscillator and is used for outputting a clock calibration signal to the annular voltage-controlled oscillator, adjusting the internal clock of the annular voltage-controlled oscillator and eliminating the influence of clock jitter on an output clock signal;
the ring voltage-controlled oscillator adjusts the phase difference between clock signals of a plurality of phases according to the input second control voltage;
the annular voltage-controlled oscillator comprises a first delay unit, a second delay unit, a third delay unit and a fourth delay unit which are connected into an annular shape and have the same structure, wherein the output ends OP and ON of the fourth delay unit are respectively connected with the input ends IP and IN of the first delay unit; the output ends OP and ON of the previous delay unit IN the rest delay units connected IN sequence are respectively connected with the input ends IN and IP of the next delay unit;
the phase difference of the signals of the input ends IP and IN of each delay unit is 180 degrees, and the phase difference of the signals of the output ends ON and OP is 180 degrees; the phase difference between the signal of the output terminal OP and the signal of the input terminal IN is 45 degrees, and the phase difference between the signal of the output terminal ON and the signal of the input terminal IP is 45 degrees; the ring voltage-controlled oscillator finally obtains 8 clock signals with phase differences of 45 degrees;
the delay unit comprises a first inverter, a second inverter, a third inverter and a fourth inverter, wherein the first normally-on transmission gate, the second normally-on transmission gate, the first variable capacitor group and the second variable capacitor group;
the output end of the first inverter is connected with the input end of the second inverter; the output end of the third inverter is connected with the input end of the fourth inverter; a first normally-on transmission gate is connected between the input end of the first inverter and the output end of the third inverter in a bridging way; a second normally-on transmission gate is connected between the input end of the third inverter and the output end of the first inverter in a bridging way; the output end of the first inverter and the output end of the third inverter are connected in parallel in a bridging manner through a first variable capacitor group and a second variable capacitor group;
the input end of the first inverter is the input end IN of the delay unit, and the input end of the third inverter is the input end IP of the delay unit; the output end of the second inverter is the output end OP of the delay unit, and the output end of the fourth inverter is the output end ON of the delay unit;
the first variable capacitor group is a voltage-controlled capacitor group, the control end VC of the first variable capacitor group is connected with control voltage, and the frequency of the clock signal output by the delay unit is controlled by controlling the capacitance of the first variable capacitor group;
the second variable capacitor group is a voltage-controlled capacitor group, the control end VT of the second variable capacitor group is connected with control voltage, and the phase of the clock signal output by the delay unit is controlled by controlling the capacitance of the second variable capacitor group;
the control end VC of each delay unit is connected with a first control voltage output by the phase tracking loop circuit, so that the frequency of an output clock signal of each delay unit is the same as the frequency of a reference clock signal;
the control terminals VT of the first, second, third and fourth delay units are respectively connected with second control voltages VTS1, VTS2, VTS3 and VTS4, and respectively adjust the phases of clock signals output by the delay units;
in the case of performing the multi-channel time interleaving ADC, the phase difference of the clock signals required to be connected to each ADC block is strictly required to be 45 °, and the phase difference reaching each ADC block is deviated due to the path delay or other reasons, and the phase of the clock signals outputted from each delay unit is changed by adjusting the second control voltages VTS1, VTS2, VTS3, VTS4, respectively, so that the phase difference reaching each ADC block is 45 °.
2. The multiphase clock generation circuit of claim 1 wherein the ring voltage controlled oscillator further comprises an NMOS transistor having a source and drain connected across the input IN, IP of either delay cell, and a gate connected to the output of the calibration pulse generation circuit.
3. The multiphase clock generation circuit of claim 1 wherein the ring voltage controlled oscillator further comprises four NMOS transistors corresponding to the four delay cells, respectively, the source and drain of each NMOS transistor being connected across the input IN, IP of its corresponding delay cell; the grid electrode of any one NMOS tube is connected with the output end of the calibration pulse generating circuit, and the grid electrodes of the other three NMOS tubes are grounded.
4. A multi-phase clock generating circuit according to claim 2 or 3, wherein,
the calibration pulse generating circuit is connected with a reference clock signal, and outputs a clock calibration signal aligned with the rising edge of the reference clock signal to the grid electrode of the NMOS tube under the enabling of the jitter removal enabling signal;
when the ring voltage-controlled oscillator generates clock jitter, the output potentials of the output ends OP and ON of the delay units bridged by the NMOS tube are unequal, the clock calibration pulse signal enables the NMOS tube to be conducted, and then current flows through the NMOS tube, so that the voltage difference between the output ends OP and ON is reduced to zero, and the zero crossing point of the output clock signal of the ring voltage-controlled oscillator is retimed at the arrival time of the injected clock calibration pulse signal.
5. The multiphase clock generation circuit of claim 4 wherein the calibration pulse generation circuit comprises a three-input and gate and a delayed inversion module;
the input end of the delay inverting module is connected with a reference clock signal, and the output end of the delay inverting module outputs the reference clock signal which is delayed for set time and inverted;
the first input end of the three-input AND gate is connected with a jitter removal enabling signal; the second input end is connected with a reference clock signal, and the third input end is connected with a reference clock signal which is delayed for a set time and is inverted;
when the debounce enable signal is high, the calibration pulse generation circuit outputs a clock calibration signal having a rising edge aligned with the rising edge of the reference clock signal and a pulse width set to a delay time.
6. The multiphase clock generation circuit of claim 5 wherein the delayed inversion module comprises three inverters connected in series; the input signal is a reference clock signal, and the output signal is a clock signal with the delay time being the sum of the delay times of three inverters and the phase opposite to the reference clock signal.
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| CN116137531A (en) * | 2021-11-16 | 2023-05-19 | 深圳市中兴微电子技术有限公司 | Sampling circuit, method for using sampling circuit, storage medium, and electronic device |
| CN114650058A (en) * | 2022-04-08 | 2022-06-21 | 福州大学 | BBPD module-based time-interleaved FLASH ADC circuit for realizing self-calibration |
| CN115334264B (en) * | 2022-08-17 | 2024-04-09 | 中国电子科技集团公司第四十四研究所 | CMOS image sensor on-chip clock generation circuit, module and method |
| CN117478130B (en) * | 2023-12-28 | 2024-04-02 | 南京美辰微电子有限公司 | Multiphase sampling clock generation circuit of time interleaving ADC |
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| CN106849942A (en) * | 2016-12-29 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of ultrahigh speed low jitter multiphase clock circuit |
| CN207083071U (en) * | 2017-07-20 | 2018-03-09 | 深圳市汇春科技股份有限公司 | A kind of clock phase-locked loop loop circuit for microcontroller |
| CN110855288A (en) * | 2019-11-27 | 2020-02-28 | 西安紫光国芯半导体有限公司 | Clock circuit and clock signal generation method |
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| US7339439B2 (en) * | 2005-07-18 | 2008-03-04 | Atmel Corporation | Voltage-controlled oscillator with multi-phase realignment of asymmetric stages |
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| JPH09326692A (en) * | 1996-06-04 | 1997-12-16 | Texas Instr Japan Ltd | Phase locked loop circuit |
| CN106849942A (en) * | 2016-12-29 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of ultrahigh speed low jitter multiphase clock circuit |
| CN207083071U (en) * | 2017-07-20 | 2018-03-09 | 深圳市汇春科技股份有限公司 | A kind of clock phase-locked loop loop circuit for microcontroller |
| CN110855288A (en) * | 2019-11-27 | 2020-02-28 | 西安紫光国芯半导体有限公司 | Clock circuit and clock signal generation method |
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| CN111600606A (en) | 2020-08-28 |
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