CN111600576B - Synchronous trigger pulse generating circuit - Google Patents
Synchronous trigger pulse generating circuit Download PDFInfo
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- CN111600576B CN111600576B CN202010341374.5A CN202010341374A CN111600576B CN 111600576 B CN111600576 B CN 111600576B CN 202010341374 A CN202010341374 A CN 202010341374A CN 111600576 B CN111600576 B CN 111600576B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a synchronous trigger pulse generating circuit, which comprises a first voltage comparator, a second voltage comparator and a third voltage comparator, wherein the non-inverting input end of the first voltage comparator is connected with a sine wave signal, the inverting input end of the first voltage comparator is connected with zero voltage, and the output end of the first voltage comparator outputs a first square wave signal VOUT_1 through a first RC filter; the non-inverting input end of the second voltage comparator is connected with the first square wave signal VOUT_1, and the inverting input end thereof is connected with the low level reference voltage V ref The output end of the second voltage comparator outputs a second square wave signal VOUT_2 through a second RC filter; the non-inverting input end of the first voltage comparator is connected with the second square wave signal VOUT_2, the inverting input end of the first voltage comparator is connected with the first square wave signal VOUT_1, and the output end of the third voltage comparator outputs a synchronous pulse signal. The invention has the advantages of small volume, simple structure, strong stability and the like, and the output synchronous pulse signal is synchronous with the phase of the input variable frequency sine wave signal, thereby being convenient for the detection of a post-stage sensor circuit.
Description
Technical Field
The invention belongs to the field of signal conversion, and particularly relates to a synchronous trigger pulse generating circuit.
Background
In the application of signal and information processing technology, it is often necessary to convert the variable-frequency amplitude sine wave signal input from the front end into a high-precision synchronous pulse signal as trigger excitation, and send the synchronous pulse signal to the rear end acquisition card to trigger the acquisition card to work. The sine wave is converted into a pulse output signal by adopting a traditional analog circuit or a Schmitt trigger, the requirement on the amplitude and the frequency of an input waveform is higher, the generated pulse signal has obvious hysteresis, the acquisition at the rear end is affected, and the requirements on synchronous and high-precision signal acquisition at the current stage cannot be met; on the other hand, if the FPGA (Field-Programmable GateArray, field programmable gate array) is used to generate the synchronous pulse control signal, a large number of peripheral devices and high-precision digital processing chips are required, including a signal receiving unit, a parameter processing unit, a phase-locked loop unit (PLL unit), a pulse generating unit, a pulse output unit, etc., which are capable of generating a pulse signal conforming to the acquisition requirements, but are expensive in cost, large in size, and cannot be widely installed in the sensing signal acquisition device.
In view of the above circumstances, it is desired to design a synchronous pulse signal generating circuit that meets the requirement of high-precision acquisition while changing the conventional technical drawbacks and reducing the production cost.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention provides a synchronous trigger pulse generating circuit which utilizes a comparator to generate a synchronous pulse signal, thereby overcoming the defects of poor stability and high delay of the pulse signal generated by the traditional gate circuit simulation technology and reducing the circuit cost.
In order to solve the technical problems in the prior art, the technical scheme of the invention is as follows:
a synchronous trigger pulse generating circuit at least comprises a power supply conversion circuit and a waveform output circuit, wherein,
the power supply conversion circuit is used for providing a power supply voltage and a comparison reference voltage for the waveform output circuit;
the waveform output circuit comprises a first voltage comparator, a second voltage comparator and a third voltage comparator, wherein the non-inverting input end of the first voltage comparator is connected with a sine wave signal, the inverting input end of the first voltage comparator is connected with zero voltage, and the output end of the first voltage comparator outputs a first square wave signal VOUT_1 through a first RC filter; the non-inverting input end of the second voltage comparator is connected with the first square wave signal VOUT_1, and the inverting input end thereof is connected with the low level reference voltage V ref The output end of the second voltage comparator outputs a second square wave signal VOUT_2 through a second RC filter; the non-inverting input end of the third voltage comparator is connected with the second square wave signal VOUT_2, the inverting input end of the third voltage comparator is connected with the first square wave signal VOUT_1, and the output end of the third voltage comparator outputs a synchronous pulse signal;
the positive power input end of the first voltage comparator inputs +2.5V, the negative power input end inputs-1.2V, the high level of the first square wave signal VOUT_1 is +2.5V, and the low level thereof is-1.2V;
the positive power input end of the second voltage comparator inputs +3.3V, the negative power input end inputs 0V, the high level of the second square wave signal VOUT_2 is +3.3V, and the low level is 0V;
in the third voltage comparator, positive power input end of the comparator inputs +3.3V, negative power input end inputs 0V, high level of the synchronous pulse signal is +3.3V, and low level of the synchronous pulse signal is 0V.
As a further improvement scheme, the first RC filter and the second RC filter form an RC low-pass filter for series resistors and parallel capacitors, and the RC low-pass filter is used for filtering high-frequency noise and periodic fluctuation signals to obtain square wave signals with slowly-rising edges.
As a further development, the non-inverting input of the second voltage comparator and the inverting input of the third comparator are provided with current limiting resistors.
As a further improvement, the pulse width of the synchronous pulse signal is between a few ns and a few tens ns.
As a further improvement, the power supply conversion circuit at least comprises three independent DC-DC conversion circuits for respectively supplying power to the comparators in the waveform output circuit.
As a further improvement, the power conversion circuit further comprises a resistor voltage division circuit which outputs a low-level reference voltage V within the range of 0-2.5V by utilizing series voltage division ref 。
As a further improvement, the device further comprises a buffer circuit, wherein the buffer circuit is used for outputting the input variable-frequency amplitude sine wave signal into a low-impedance sine wave signal without bias voltage.
In the above technical scheme, after the input variable frequency sine wave signal passes through the voltage follower, a low impedance sine wave without bias signal is generated, then the input variable frequency sine wave signal is input to the homodromous input end of the first voltage comparator, the output signal of the first voltage comparator passes through the RC filter to generate a square wave signal VOUT_1 with high level +2.5V and low level-1.2V, then the square wave signal VOUT_1 is input to the homodromous input end of the second voltage comparator, the square wave signal VOUT_1 is compared with the low level voltage signal Vref input to the reverse input end of the second voltage comparator, the output signal of the second voltage comparator passes through the RC filter to output a square wave signal VOUT_2 with high level +3.3V and low level 0V, and as a constant phase difference exists between the square wave signals VOUT_1 and VOUT_2, the square wave signal VOUT_1 output by the first voltage comparator is input to the reverse input end of the third voltage comparator, the third voltage comparator generates a synchronous pulse signal, and the synchronous pulse signal is conveniently provided by the power supply system in the whole power supply circuit of the conversion circuit after the detection stage.
Compared with the prior art, the technical scheme of the invention is adopted, the input variable frequency sine wave signal is subjected to voltage follower to generate a non-offset low-impedance sine wave, the input variable frequency sine wave signal is subjected to comparator input by two different power supplies to generate square wave signals VOUT_1 and VOUT_2 with corresponding levels, and the difference value of the two rising edges can be output through the comparator to be the output synchronous pulse signal due to the fixed phase difference between the two signals. The invention has the advantages of small volume, simple structure and strong stability, and the output synchronous pulse signal is synchronous with the phase of the input variable frequency sine wave signal, thereby being convenient for the detection of a post-stage sensor circuit.
Drawings
FIG. 1 is a schematic diagram of a system circuit of the present invention;
FIG. 2 is a schematic diagram of the power conversion circuit in FIG. 1;
FIG. 3 is a schematic diagram of the resistor divider circuit of FIG. 1;
FIG. 4 is a schematic diagram of the buffer circuit of FIG. 1;
FIG. 5 is a schematic diagram of the waveform output circuit of FIG. 1;
Detailed Description
The invention will be further described with reference to the accompanying drawings.
Referring to fig. 1, the invention provides a circuit for converting sine wave into synchronous control pulse output, which mainly comprises a power supply conversion circuit, a resistor voltage dividing circuit, an isolation input circuit, a waveform output circuit and the like. The power supply conversion circuit is used for providing a power supply voltage and a comparison reference voltage for the waveform output circuit;
the waveform output circuit comprises a first voltage comparator, a second voltage comparator and a third voltage comparator, wherein the non-inverting input end of the first voltage comparator is connected with a sine wave signal, the inverting input end of the first voltage comparator is connected with zero voltage, and the output end of the first voltage comparator outputs a first square wave signal VOUT_1 through a first RC filter; the non-inverting input end of the second voltage comparator is connected with the first square wave signal VOUT_1, and the inverting input end thereof is connected with the low level reference voltage V ref The output end of the second voltage comparator outputs a second square wave signal VOUT_2 through a second RC filter; the non-inverting input end of the third voltage comparator is connected with the second square wave signal VOUT_2, the inverting input end of the third voltage comparator is connected with the first square wave signal VOUT_1, and the output end of the third voltage comparator outputs a synchronous pulse signal;
the power supply conversion circuit at least comprises three independent DC-DC conversion circuits which are used for respectively supplying power to comparators in the waveform output circuit. The power supply conversion circuit outputs high-precision low-noise voltage +3.3V, +2.5V and-1.2V respectively, and the voltages are respectively supplied by a positive power input end, a negative power input end and a low-voltage level signal of a comparator in the waveform output circuit;
the positive power input end of the comparator in the first voltage comparator inputs +2.5V, the negative power input end inputs-1.2V, the output end connects the series resistor and connects the capacitor in parallel to form RC low-pass filter to filter high-frequency noise and periodic fluctuation signal, get the square wave signal VOUT_1 that the rising edge is slowed down, the high level of this signal is +2.5V, the low level is-1.2V;
the positive power input end of the comparator in the second voltage comparator inputs +3.3V, the negative power input end inputs 0V, because the voltage sources of the second voltage comparator and the first voltage comparator are different, a current limiting resistor is needed to be added at the non-inverting input end of the comparator to prevent the comparator from being burnt, the output end of the comparator is connected with a series resistor and a parallel capacitor to form an RC filter to filter high-frequency noise and periodic fluctuation signals, and a square wave signal VOUT_2 with a slowly rising edge is obtained, wherein the high level of the signal is +3.3V, and the low level of the signal is 0V;
in the third voltage comparator, the positive power input end of the comparator inputs +3.3V, the negative power input end inputs 0V, because the voltage sources of the third voltage comparator and the first voltage comparator are different, a current-limiting resistor is required to be added at the non-inverting input end of the comparator to prevent the comparator from being burnt, and the output end outputs a synchronous pulse signal with the peak value of 3.3V.
The first RC filter and the second RC filter are RC low-pass filters formed by series resistors and parallel capacitors and are used for filtering high-frequency noise and periodic fluctuation signals so as to obtain square wave signals with slowly-released rising edges.
Because the voltage sources of the second voltage comparator and the first voltage comparator are different, a current limiting resistor is added at the non-inverting input end of the comparator to prevent the comparator from being burnt; because the voltage source of the third voltage comparator is different from that of the first voltage comparator, a current limiting resistor is added at the non-inverting input end of the comparator to prevent the comparator from being burnt. As a further development, the non-inverting input of the second voltage comparator and the inverting input of the third comparator are provided with current limiting resistors.
As a further improvement, the pulse width of the synchronous pulse signal is between a few ns and a few tens ns.
As a further improvement, the power conversion circuit further comprises a resistor voltage division circuit which outputs a low-level reference voltage V within the range of 0-2.5V by utilizing series voltage division ref 。
As a further improvement, the device further comprises a buffer circuit, wherein the buffer circuit is used for outputting the input variable-frequency amplitude sine wave signal into a low-impedance sine wave signal without bias voltage.
Referring to fig. 2, a schematic diagram of a power conversion circuit of the present invention is shown, where +3.3v, +2.5v, -1.2v levels are respectively output for providing power to a voltage comparator, the power conversion circuit further includes a voltage input terminal JP1, a precision adjustable potentiometer RP2, a precision adjustable potentiometer RP3, a first linear voltage stabilizing chip U1, a second linear voltage stabilizing chip U2, a third linear voltage stabilizing chip U3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first patch capacitor C1, a second patch capacitor C2, a third patch capacitor C3, a first patch capacitor C4, a first patch capacitor C5, a first patch capacitor C6, a first patch capacitor C7, a first patch capacitor C8, a first capacitor C9, a first patch capacitor C10, a first patch capacitor C11, a first linear capacitor C12, a first patch capacitor C13, a first patch capacitor C14, a first linear capacitor C35, a first patch capacitor C16, a first linear voltage stabilizing chip V, a first wire capacitor C16, a first patch capacitor V1, a first linear voltage stabilizing capacitor V, a first wire V, a first patch capacitor V12, a first patch capacitor V14, a first patch capacitor V21, a first voltage C20, a first voltage stabilizing capacitor V, a first tsp 1, a voltage stabilizing capacitor V, a first wire V, a voltage, and a voltage, wherein the first patch capacitor V is set 2, and first voltage is used as input terminal, respectively.
The voltage input terminal JP1 in the power conversion circuit is connected with external input voltage, a first pin of JP1 is connected with external input-5V, a third pin is connected with external input +5V, a second pin is connected with one end of a first resistor R1, and the other end of the first resistor R1 is grounded; one end of the first patch capacitor C1 and one end of the second patch capacitor C2 are connected with +5V, and the other ends of the first patch capacitor C1 and the second patch capacitor C2 are connected with a ground wire; one ends of the third patch capacitor C3 and the fourth patch capacitor C4 are connected with-5V, and the other ends of the third patch capacitor C3 and the fourth patch capacitor C4 are connected with a ground wire; the power supply input of the chips is +5V by the 15 pins and the 16 pins of the first linear voltage stabilizing chip U1, one end of the fifth chip capacitor C5 and one end of the sixth chip capacitor C6 are connected, the other ends of the fifth chip capacitor C5 and the sixth chip capacitor C6 are connected with the ground wire, the 1 pins and 20 pins of the linear voltage stabilizing chip U1 are connected with the power supply output +3.3V, one end of the seventh chip capacitor C7, the eighth chip capacitor C8, the ninth chip capacitor C9 and one end of the second resistor R2 are connected, the other ends of the seventh chip capacitor C7 and the eighth chip capacitor C8 are connected with the ground wire, the other ends of the ninth chip capacitor C9 are connected with the 3 pins of the linear voltage stabilizing chip U1, the other ends of the second resistor R2 are connected with the first pin of the precision adjustable potentiometer RP1, the other ends of the third pin of the first linear voltage stabilizing chip U1 are connected with the second pin and the third pin of the potentiometer RP1, one end of the other ends of the third resistor R3 are connected with the ground wire, the other ends of the linear resistor C3 and the other ends of the fourth chip C8 and the fourth chip C9 are connected with the ground wire, and the other ends of the linear voltage stabilizing chip C1 and the other ends of the pins of the chip C1 and the ground wire and the other ends of the chip 7 and the other ends are connected with the ground wire and the chip 7 and the ground wire and the chip and the end of the chip and is connected with the ground wire and 18 and the end and the chip and is well and 18 and is connected and 18 and suspended and 18; the 15 pin and the 16 pin of the second linear voltage stabilizing chip U2 are connected with the chip power input +5V, one end of the eleventh patch capacitor C11 and one end of the twelfth patch capacitor C12 are connected, the other end of the eleventh patch capacitor C11 and the other end of the twelfth patch capacitor C12 are connected with the power output +2.5V, the 1 pin and the 20 pin of the linear voltage stabilizing chip U2 are connected with one end of the thirteenth patch capacitor C13, the fourteenth patch capacitor C14, the fifteenth patch capacitor C15 and one end of the fourth resistor R4, the other end of the thirteenth patch capacitor C13 and the fourteenth patch capacitor C14 are connected with the ground wire, the other end of the fifteenth patch capacitor C15 is connected with the 3 pin of the linear voltage stabilizing chip U2, the other end of the fourth resistor R4 is connected with the first pin of the precision adjustable potentiometer RP2, the 3 pin of the second linear voltage stabilizing chip U2 is connected with the second pin and the third pin of the potentiometer RP2, one end of the fifth resistor R5 is connected with the other end of the thirteenth chip capacitor C13, the other end of the sixteenth chip C14 is connected with the sixteen end of the other end of the linear voltage stabilizing chip C2, the sixteen end of the sixteenth chip C2 is connected with the ground wire, and the other end of the sixteen end of the chip C2 is connected with the sixteen end of the chip C2 and the sixteen end of the chip 17 is connected with the ground wire and the other end of the chip 7 is connected with the chip 7; the power supply input of the chips is +5V by the 15 pins and the 16 pins of the third linear voltage stabilizing chip U3, one end of the seventeenth chip capacitor C17 and one end of the eighteenth chip capacitor C18 are connected, the other end of the seventeenth chip capacitor C17 and the other end of the eighteenth chip capacitor C18 are grounded by the power supply output of-1.2V, one end of the nineteenth chip capacitor C19, one end of the twenty-first chip capacitor C20, one end of the twenty-first chip capacitor C21 and one end of the sixth resistor R6 are connected, the other end of the nineteenth chip capacitor C19 and the other end of the twenty-first chip capacitor C20 are grounded by the ground wire, the other end of the twenty-first chip capacitor C21 is connected with the first pin of the linear voltage stabilizing chip U3, the other end of the sixth resistor R6 is connected with the first pin of the precision adjustable potentiometer RP3, the other end of the seventh chip U7 is connected with the second pin and the third pin of the potentiometer RP3, one end of the seventh resistor R7 is connected with one end of the seventh chip C20, the other end of the twenty-first chip capacitor C7 is connected with the other end of the twenty-first pin of the linear voltage stabilizing chip C7, the other end of the twenty-first chip C21 is connected with the ground wire, and the other end of the twenty-first chip 7 is connected with the ground wire, and the other end of the twenty-second chip is suspended, and the end of the line stable chip is connected with the ground wire is suspended;
referring to fig. 3, a schematic diagram of a resistor voltage dividing circuit according to the present invention is shown, in which a resistor is used to divide the +2.5v voltage output from the power conversion circuit to obtain a low level voltage Vref, the resistor voltage dividing circuit further includes an eleventh resistor R11, a twelfth resistor R12, a twenty-ninth chip capacitor C29, and a thirty-ninth chip capacitor C30;
one end of an eleventh resistor R11 in the resistor divider circuit is connected with +2.5V output by the linear voltage stabilizing chip U2 in the power supply conversion circuit, and the other end of the eleventh resistor R11 is connected with a low-level signal output Vref; one end of the twenty-ninth patch capacitor C29 is connected with +2.5V output by the linear voltage stabilizing chip U2 of the power conversion circuit, and the other end of the twenty-ninth patch capacitor C29 is connected with a ground wire; one end of the twelfth resistor R12 and one end of the thirty-second patch capacitor C30 are connected with the low-level signal output Vref, and the other end of the twelfth resistor R12 and the thirty-second patch capacitor C30 are connected with the ground wire;
because the sine wave signal output by the sensor system in the general sense is continuously changed in peak-to-peak value, the bandwidth of the signal is between 1MHz and 10MHz, and the signal to be processed with burrs and noise needs to be processed by reducing the output impedance through a filter capacitor and a voltage follower and then is output to a comparator. Referring to fig. 4, a schematic diagram of a buffer circuit of the present invention is shown, the buffer circuit connects an input sine wave signal to a forward input end of an operational amplifier after RC high-pass filtering, and outputs a signal OPAOUT; the voltage follower formed by the operational amplifier has the characteristics of high input impedance and low output impedance, and is used for isolating the front-stage and the rear-stage circuits, eliminating the mutual influence between the front-stage and the rear-stage circuits, effectively reducing the consumption of signals and reducing the interference to the rear-stage comparator.
The buffer circuit further comprises a first signal input terminal SIN_1, a fourth operational amplifier chip U4, an eighth chip resistor R8, a ninth chip resistor R9, a tenth chip resistor R10, a twenty-third chip capacitor C23, a twenty-fourth chip capacitor C24, a twenty-fifth chip capacitor C25, a twenty-sixth chip capacitor C26, a twenty-seventh chip capacitor C27 and a twenty-eighth chip capacitor C28, wherein the fourth operational amplifier chip is an OPA690, and the first signal input terminal SIN_1 is an SMA_KE master.
The second pin of the signal input terminal SIN_1 of the isolation input module is connected with analog ground, the first pin is connected with one end of a twenty-third patch capacitor C23, the other end of the twenty-third patch capacitor C23 is connected with 3 pins of a fourth operational amplifier chip U4 and one end of a ninth resistor R9, the other end of the ninth resistor R9 is connected with analog ground, 7 pins and 8 pins of the fourth operational amplifier chip U4 are connected with positive power input +5V of the chip, 4 pins are connected with negative power input-5V of the chip, 2 pins are connected with an eighth resistor R8, and the other end of the eighth resistor R8 is connected with 6 pins of the operational amplifier chip U4, namely an output sine wave signal OPAOUT after isolation; one end of the tenth resistor R10 is connected with analog ground, and the other end is connected with a ground wire; one end of the twenty-fourth patch capacitor C24 and one end of the twenty-fifth patch capacitor C25 are connected with the power input +5V, and the other end is connected with the analog ground; one end of the twenty-sixth patch capacitor C26 and one end of the twenty-seventh patch capacitor C27 are connected with power input-5V, and the other end is connected with analog ground; one end of the twenty-eighth patch capacitor C28 is connected with the power input +5V, and the other end is connected with the power input-5V.
The waveform output circuit outputs a square wave signal VOUT_1 from the low-impedance OPAOUT sine wave signal through a first voltage comparator and an RC filter to form the first voltage comparator; the output square wave signal VOUT_1 is input into the non-inverting input end of the second voltage comparator after passing through the current limiting resistor, and the low level voltage signal V ref The square wave signal VOUT_2 is output through the second voltage comparator and the RC filter to form the second voltage comparator; the square wave signal VOUT_1 is input into the non-inverting input end of the third voltage comparator after passing through the current limiting resistor, the square wave signal VOUT_2 is input into the inverting input end of the second voltage comparator, and the synchronous pulse signal is output through the second voltage comparator to form the third voltageAnd a comparator.
Referring to fig. 5, a schematic diagram of a waveform output circuit of the present invention is shown, in which an obtained isolated input sine wave is transformed and shaped to generate a synchronous pulse signal and output, the comparator circuit further includes a fifth voltage comparator chip U5, a sixth voltage comparator chip U6, a seventh voltage comparator chip U7, a second signal output terminal out_1, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, a thirty-first patch capacitor C31, a thirty-second patch capacitor C32, a thirty-third patch capacitor C33, a thirty-fourth patch capacitor C34, a thirty-fifth patch capacitor C35, a thirty-sixth patch capacitor C36, a thirty-seventh patch capacitor C37, a thirty-eighth patch capacitor C38, a thirty-ninth patch capacitor C39, and a fortieth patch capacitor C40; the fifth voltage comparator chip U5, the sixth voltage comparator chip U6, and the seventh voltage comparator chip U7 are TLV3501, and the second signal output terminal out_1 is an sma_ke socket.
In the comparator circuit, pin 3 of the fifth voltage comparator chip U5 is connected with the sine wave signal OPAOUT which is output in an isolated mode, pin 4 and pin 8 of the voltage comparator chip U5 are connected with-1.2V which is output by the power conversion circuit, pin 7 is connected with the grounding wire of pin +2.5V which is output by the power conversion circuit, pin 1 and pin 5 are suspended, pin 6 of the voltage comparator chip U5 is connected with one end of a thirteenth resistor R13, the other end of the thirteenth resistor R13 outputs a square wave signal VOUT_1 and is simultaneously connected with one end of a thirty-third patch capacitor C33, and the other end of the thirty-third patch capacitor C33 is connected with the grounding wire; one end of the thirty-first patch capacitor C31 and one end of the thirty-second patch capacitor C32 are connected with +2.5V output by the power conversion circuit, and the other end is connected with a ground wire; one end of the thirty-fourth patch capacitor C34 and one end of the thirty-fifth patch capacitor C35 are connected with-1.2V output by the power conversion circuit, and the other end of the thirty-fifth patch capacitor C35 is connected with a ground wire; the 3 pin of the sixth voltage comparator chip U6 is connected with one end of a fourteenth resistor R14, the other end of the fourteenth resistor R14 is connected with a square wave signal VOUT_1 output by the fifth voltage comparator chip U5, the 2 pin of the voltage comparator chip U6 is connected with a low level signal Vref output by the voltage dividing circuit, the 7 pin is connected with +3.3V,4 and 8 pins ground wires output by the power conversion circuit, the 1 and 5 pins are suspended, the 6 pin of the voltage comparator chip U6 is connected with one end of a fifteenth resistor R15, the other end of the fifteenth resistor R15 outputs a square wave signal VOUT_2 and is simultaneously connected with one end of a thirty-eighth patch capacitor C38, and the other end of the thirty-eighth patch capacitor C38 is connected with the ground wire; one end of the thirty-sixth patch capacitor C36 and the thirty-seventh patch capacitor C37 are connected with +3.3V output by the power conversion circuit, and the other end is connected with a ground wire; the 3 pin of the seventh voltage comparator chip U7 is connected with one end of a sixteenth resistor R16, the other end of the sixteenth resistor R16 is connected with a square wave signal VOUT_1 output by the fifth voltage comparator chip U5, the 2 pin of the voltage comparator chip U7 is connected with a square wave signal VOUT_2 output by the sixth voltage comparator chip U6, the 7 pin is connected with +3.3V,4 and 8 pin grounding wires output by a power conversion circuit, the 1 and 5 pins are suspended, the 6 pin of the voltage comparator chip U7 is connected with one end of a seventeenth resistor R17, the other end of the seventeenth resistor R17 is connected with a first pin of a second signal output terminal OUT_1, and the second pin of the second signal output terminal OUT_1 is grounded; one end of the thirty-ninth patch capacitor C39 and one end of the forty patch capacitor C40 are connected with +3.3V output by the power conversion circuit, and the other end is connected with a ground wire;
the specific working process is as follows: the external circuit provides +5V, -5V direct current power for the whole pulse circuit generating system, the power is provided for the power conversion circuit of figure 2 after capacitive decoupling and filtering, and voltages of +3.3V, +2.5V and-1.2V are respectively output by setting the resistance values of the voltage regulating pin output ends of the linear voltage stabilizing chips U1, U2 and U3; the +5V and-5V power supply after filtering is supplied to the buffer circuit of figure 4, the resistor R9 and the capacitor C23 in the buffer circuit of figure 4 form an RC filter to reduce the ripple and burr of the input variable frequency sine wave signal, then the output sine wave signal OPAOUT is reduced in impedance through the operational amplification chip U4, the consumption of the signal is reduced, the load capacity is improved, the signal OPAOUT is input to the in-phase input end of the comparator chip U5 in the waveform output circuit of figure 5, the power supply voltage of U5 is +2.5V and-1.2V respectively, the output signal passes through the RC filter formed by the resistor R13 and the capacitor C33 in figure 5 to generate the square wave signal VOUT_1 of +2.5V and-1.2V, the square wave signal vout_1 is input to the in-phase input end and the anti-phase input end of the comparator chip U6 in fig. 5 respectively through the current limiting resistor R14 in fig. 5 and the low voltage signal Vref generated in the resistor divider circuit in fig. 3, the power supply voltage of the comparator chip U6 is 3.3V and 0V respectively, the output signal is output to the RC filter formed by the resistor R15 and the capacitor C18 in fig. 5 to generate the square wave signal vout_2, the square wave signal vout_1 is input to the in-phase input end and the anti-phase input end of the comparator chip U7 in fig. 5 respectively through the current limiting resistor R16 in fig. 5 and the square wave signal vout_2, the power supply voltage of the comparator chip U7 is 3.3V and 0V respectively, and the output signal is the output synchronous pulse signal after passing through the protection resistor R17 in fig. 5.
The above description of the embodiments is only for aiding in the understanding of the method of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A synchronous trigger pulse generating circuit is characterized by at least comprising a power supply conversion circuit and a waveform output circuit, wherein,
the power supply conversion circuit is used for providing a power supply voltage and a comparison reference voltage for the waveform output circuit;
the waveform output circuit comprises a first voltage comparator, a second voltage ratioThe input end of the first voltage comparator is connected with a sine wave signal, the reverse input end of the first voltage comparator is connected with zero voltage, and the output end of the first voltage comparator outputs a first square wave signal VOUT_1 through a first RC filter; the non-inverting input end of the second voltage comparator is connected with the first square wave signal VOUT_1, and the inverting input end thereof is connected with the low level reference voltage V ref The output end of the second voltage comparator outputs a second square wave signal VOUT_2 through a second RC filter; the non-inverting input end of the third voltage comparator is connected with the second square wave signal VOUT_2, the inverting input end of the third voltage comparator is connected with the first square wave signal VOUT_1, and the output end of the third voltage comparator outputs a synchronous pulse signal;
the positive power input end of the first voltage comparator inputs +2.5V, the negative power input end inputs-1.2V, the high level of the first square wave signal VOUT_1 is +2.5V, and the low level thereof is-1.2V;
the positive power input end of the second voltage comparator inputs +3.3V, the negative power input end inputs 0V, the high level of the second square wave signal VOUT_2 is +3.3V, and the low level is 0V;
in the third voltage comparator, positive power input end of the comparator inputs +3.3V, negative power input end inputs 0V, high level of the synchronous pulse signal is +3.3V, and low level of the synchronous pulse signal is 0V.
2. The synchronous trigger pulse generating circuit of claim 1, wherein the first RC filter and the second RC filter are series resistors and parallel capacitors to form an RC low pass filter for filtering high frequency noise and periodic fluctuating signals to obtain square wave signals with a slowed rising edge.
3. The synchronous trigger generating circuit of claim 1, wherein the non-inverting input of the second voltage comparator and the inverting input of the third comparator are provided with current limiting resistors.
4. The synchronous trigger generating circuit of claim 1, wherein the pulse width of the synchronous pulse signal is between several ns and several tens ns.
5. The synchronous trigger generating circuit of claim 1, wherein the power conversion circuit comprises at least three independent DC-DC conversion circuits for supplying power to the comparators in the waveform output circuit, respectively.
6. The synchronous trigger pulse generating circuit of claim 5, wherein the power conversion circuit further comprises a resistor divider circuit for outputting a low level reference voltage V in the range of 0-2.5V by series division ref 。
7. The synchronous trigger pulse generating circuit of claim 1, further comprising a buffer circuit for outputting the input variable frequency amplitude sine wave signal as a low impedance sine wave signal without bias voltage.
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