CN111599749B - High-depth-width-ratio through type TSV structure, preparation method thereof and silicon adapter plate - Google Patents

High-depth-width-ratio through type TSV structure, preparation method thereof and silicon adapter plate Download PDF

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CN111599749B
CN111599749B CN202010484257.4A CN202010484257A CN111599749B CN 111599749 B CN111599749 B CN 111599749B CN 202010484257 A CN202010484257 A CN 202010484257A CN 111599749 B CN111599749 B CN 111599749B
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filling
groove
filling groove
insulating layer
etching
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CN111599749A (en
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朱克宝
唐昭焕
吴罚
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United Microelectronics Center Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

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Abstract

The application provides a through TSV structure with a high depth-to-width ratio, a preparation method thereof and a silicon adapter plate, wherein the preparation method comprises the following steps: providing a silicon substrate, wherein the silicon substrate comprises a first surface and a second surface which are opposite; defining a first filling groove area on the first surface, and carrying out etching treatment around the first filling groove area to form a first etching groove; thinning the second surface; etching the corresponding area of the first filling groove area on the second surface to form a second filling groove, growing a second insulating layer in the second filling groove, and filling a conductive material in the second filling groove; etching the first filling groove region to form a first filling groove, wherein the first filling groove is communicated with the second filling groove to form a through hole penetrating through the thinned silicon substrate; and filling the conductive material in the first filling groove.

Description

High-depth-to-width-ratio through type TSV structure, preparation method thereof and silicon adapter plate
Technical Field
The application relates to the technical field of integrated circuit advanced packaging interconnection, in particular to a through type TSV structure with a high depth-width ratio, a preparation method of the through type TSV structure and a silicon adapter plate.
Background
With the rapid development of integrated circuits, the latter molar times are approaching gradually, and the integration level cannot be increased by simply reducing the line width. The application of integrated circuits is diversified, and the integrated circuit chip also has higher requirements in emerging fields such as smart phones, internet of things, automobile electronics, high-performance computing, 5G, artificial intelligence and the like. The three-dimensional packaging (3D-TSV) silicon adapter plate technology of the silicon through holes can provide homogeneous and heterogeneous integration, and the high-speed interconnection of electric signals among chips and multiple layers of chips at high ends is achieved. The silicon adapter plate technology provides a solution for realizing more functions, smaller size and higher speed for silicon-based 2.5D/3D system-in-package.
The current 2.5D silicon adapter plate has just emerged, and in order to match the conventional wafer transmission mode and clamping tool, the technology of the TSV silicon adapter plate with the high depth-to-width ratio and the small depth-to-diameter ratio is urgently needed to be solved. The traditional method is adopted to manufacture a thick silicon adapter plate, the TSV aperture needs to be increased, and the requirement of high-density integrated wiring cannot be met; the TSV aperture is small, the high aspect ratio process is difficult to realize, the TSV aperture is realized through a menu program of an etching machine or the modification and optimization of the structure of the machine, and the TSV aperture has the defects of long test period, high cost, unobvious effect and the like. In the process of manufacturing a filling groove on the other side after forming a filling groove on one side in the conventional opposite-type TSV process, in order to ensure that an insulating layer or a barrier layer at the bottom of the filling groove is etched completely, the insulating layer or the barrier layer on the side wall of the filling groove is etched to cause side effects, so that the quality problem is easily caused; meanwhile, complete alignment cannot be ensured in the front and back surface etching process, alignment deviation easily causes contact between the conductive material deposited in the filling groove and the substrate, and quality problems easily occur.
Disclosure of Invention
The method solves all or part of technical problems that the aspect ratio of the TSV structure in the prior art is too low to effectively adapt to the three-dimensional packaging interconnection structure.
In order to solve all or part of the technical problems, the application discloses a method for preparing a through type TSV structure with a high depth-to-width ratio, which is characterized in that when a first or second filling groove area is defined on any surface, a first or second etching groove is formed by surrounding the first or second filling groove area in an etching mode, and an insulating material is filled in the first or second etching groove to form a first or second insulating layer. The width of the insulating layer prepared by the method can be far larger than that of the insulating layer deposited in the filling groove in the prior art, so that the insulating layer or the barrier layer at the bottom of the filling groove can be effectively ensured to be etched completely when the other surface is etched, the possibility that the first or second insulating layer is etched to penetrate so that the conductive material is in contact with the related material of the substrate is greatly reduced, and the quality is improved; meanwhile, the alignment process window required by the front and back surfaces is greatly improved, and the quality problem caused by the alignment problem is also improved.
The first class of embodiments of the application discloses a specific process of the preparation method of the through type TSV structure with the high aspect ratio, and the specific process comprises the following steps: providing a silicon substrate, wherein the silicon substrate comprises a first surface and a second surface which are opposite; defining a first filling groove area on the first surface, and carrying out etching treatment around the first filling groove area to form a first etching groove; filling an insulating material in the first etching groove to form a first insulating layer; thinning the second surface to obtain a thinned silicon substrate, wherein the step can be omitted if the thickness of the silicon substrate is proper; etching the corresponding area of the first filling groove area on the second surface to form a second filling groove, growing a second insulating layer in the second filling groove, depositing a second barrier layer, a second seed layer and the like after the process of growing the second insulating layer according to actual process requirements, filling a conductive material in the second filling groove, wherein the thickness of the first insulating layer is greater than that of the second insulating layer; etching the first filling groove region to form a first filling groove, wherein the first filling groove is communicated with the second filling groove to form a through hole, and the through hole penetrates through the silicon substrate; and filling a conductive material in the first filling groove and ensuring the conduction with the conductive material in the second filling groove.
Further, before the step of defining the first filling groove region on the first surface, the method further includes: a first mask layer is grown on the first surface.
Before the step of forming the second filling groove by etching the corresponding region of the first filling groove region on the second surface, the method further comprises the following steps: a second mask layer is grown on the second surface.
In the invention, in order to prevent the process of one surface from being influenced when the process is carried out on the other surface; for example, after performing any process step described in the present invention or not related to the present invention on the first surface, before performing any process step described in the present invention on the second surface, specifically, before performing a step of performing a thinning process on the second surface to obtain a thinned silicon substrate, the method further includes: a first slide is acquired and the first surface is bonded to the first slide. So as to protect the first surface in the subsequent process and prevent the subsequent process from being influenced. When the first surface is not required to be protected after the second surface processing step is completed, the method further comprises the following steps: the first surface is debonded from the first carrier.
Also, after performing any process step described in the present invention or not related to the present invention on the second surface, before performing any process step described in the present invention on the first surface, specifically, for example, before the step of forming the first filling groove in the first filling groove region, the method further includes: a second carrier sheet is acquired and the second surface is bonded to the second carrier sheet.
After the step of processing the first surface is completed, the method further comprises: debonding the second surface from the second slide.
Further, the first insulating layer and the second insulating layer may be materials known in the semiconductor field and used for insulation, and the common materials include: silicon dioxide or silicon nitride; the conductive material includes: at least one or any combination of Cu, W, Sn, Ti, Pt, Pd, Ni or Au.
Further, the etching process includes Bosch etching or laser etching.
Further, the thinning process includes a chemical mechanical polishing process.
It should be noted that, the above process steps, except for the step with strict chronological order on any surface, can not be adjusted, and the other steps can be adjusted in chronological order according to the actual process requirements. For example, a first etching groove, a first insulating layer and a first filling groove are formed on the first surface in a strict sequence; on the second surface, a second filling groove, a second insulating layer and the like are formed in strict sequence, and cannot be adjusted. The process between the first surface and the second surface can be adjusted according to actual needs. For example, after the first insulating layer is formed after the first etched trench is formed on the first surface, the second filled trench may not be formed on the second surface first, but the first filled trench may be formed on the first surface. It should be further noted that, when the process adjustment is performed according to the actual situation, the bonding and debonding between the first surface and the first carrier, and between the second surface and the second carrier may be selected according to the actual situation. In addition, "growing, depositing, and filling" in the present invention are equivalent solutions unless one of ordinary skill in the art would understand that there are obvious differences and that they belong to different solutions.
The second embodiment of the present invention is mainly different from the first embodiment in that the second filling groove of the second surface also adopts the same process as the first filling groove of the first surface, that is, the area on the second surface corresponding to the first filling groove area is defined as a second filling groove area, a second etching groove is formed by etching around the second filling groove area, and the second etching groove is filled with an insulating material to form a second insulating layer. The size (CD) of the second insulating layer that plays an insulating role in this embodiment is much larger than that in the first embodiment. In this embodiment, the width dimension (CD) of the second etched trench may or may not be the same as the width dimension of the first etched trench.
The third embodiment of the application discloses a first aspect of a high aspect ratio through type TSV structure, which comprises a silicon substrate, wherein a first filling groove and a second filling groove are formed in the silicon substrate; the first filling groove is communicated with the second filling groove to form a through hole, and the through hole penetrates through the silicon substrate; the first filling groove and the second filling groove are filled with conductive materials; a first insulating layer and a second insulating layer are respectively arranged between the conductive materials in the first filling groove and the second filling groove and the silicon substrate, a first etching groove is formed in the periphery of the first filling groove, the first insulating layer is located in the first etching groove, and the second insulating layer is located in the second filling groove. The thickness of the first insulating layer is larger than that of the second insulating layer, and a shoulder-shaped or step-shaped insulating layer is formed.
The second aspect of the third class of embodiments of the present application discloses another high aspect ratio through type TSV structure, which includes a silicon substrate, wherein a first filling groove and a second filling groove are formed on the silicon substrate; the first filling groove is communicated with the second filling groove to form a through hole, and the through hole penetrates through the silicon substrate; the first filling groove and the second filling groove are filled with conductive materials; and a first insulating layer and a second insulating layer are respectively arranged between the conductive materials in the first filling groove and the second filling groove and the silicon substrate, and the silicon substrate etching device is characterized in that the first insulating layer and/or the second insulating layer are formed by filling insulating materials in an etching groove after the etching groove is formed by etching the surface of the silicon substrate around the first filling groove and/or the second filling groove.
Further, the first insulating layer and the second insulating layer may be materials known in the semiconductor field and used for insulation, and common materials include: silicon dioxide or silicon nitride; the conductive materials each include: at least one or any combination of Cu, W, Sn, Ti, Pt, Pd, Ni or Au.
The application also provides a silicon adapter plate which comprises a through TSV structure with a high depth-width ratio.
By adopting the technical scheme, the application has the following beneficial effects: the preparation method of the through TSV structure with the height-depth-width ratio provided by the embodiment of the application adopts a mode of manufacturing the filling grooves on the front side and the back side of the silicon substrate in a segmented mode to form the through TSV structure with the height-depth-width ratio, wherein the scheme that the insulating layer is prepared around the filling grooves before the filling grooves are etched is adopted, the problem that the side walls and the bottoms of the filling grooves at the two ends are easily penetrated in the etching process can be avoided while the through TSV structure with the height-depth-width ratio is obtained, and the alignment window is improved. Due to the advantages, the TSV aperture can be small, the high aspect ratio process is easy to realize, the workload of menu program parameter adjustment or machine structure modification through an etching machine can be greatly reduced, the test period can be shortened, the cost is reduced, and the preparation effect is very obvious. When the height-depth-width ratio through type TSV structure is applied to a silicon adapter plate, three-dimensional packaging of chips with multiple sizes and 2.5D/3D micro-system integration can be achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a high aspect ratio through TSV structure according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a process for manufacturing a TSV structure with a high aspect ratio.
Fig. 3 is a schematic diagram illustrating a process for manufacturing a TSV structure with a high aspect ratio.
Fig. 4 is a schematic diagram of a process for preparing a three-height-depth-width-ratio pass-through TSV structure according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a process for manufacturing a four-height-depth-width-ratio pass-through TSV structure according to an embodiment of the present application.
Fig. 6 is a schematic diagram illustrating a technical problem of a high aspect ratio pass-through TSV structure in the prior art.
Fig. 7 is a schematic diagram of a five-type TSV structure with high aspect ratio.
Fig. 8 is a schematic diagram of a five-type TSV structure with high aspect ratio.
The following is a supplementary description of the drawings:
1-a silicon substrate; 2-a first mask layer; 3-first filled trench region; 4-first etching the groove; 5-a first insulating layer; 6-first slide; 7-a second mask layer; 8-a second filled trench; 9-a second slide; 10-second etching groove; 11-a first filled trench; 12-circular shoulder.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the protection scope of the present application.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the present application. In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "top", "bottom", and the like refer to orientations or positional relationships based on orientations or positional relationships shown in the drawings, which are used for convenience in describing the present application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be taken as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.
Implement one
With reference to fig. 1 and fig. 2, fig. 1 is a schematic flow chart of a method for manufacturing a high aspect ratio through TSV structure according to an embodiment of the present application, where the method includes the following steps:
s1, a silicon substrate 1 is provided, and the silicon substrate 1 comprises a first surface and a second surface which are opposite.
S2, defining a first filling groove area 3 on the first surface, and etching around the first filling groove area 3 to form a first etching groove 4.
S3, filling the first etching groove 4 with an insulating material to form a first insulating layer 5.
S4, thinning the second surface to obtain a thinned silicon substrate 1; the thinning step may also be omitted if the thickness of the silicon substrate is appropriate.
S5, etching the corresponding area of the first groove filling area 3 defined by the second surface and the first surface to form a second groove filling 8, sequentially growing a second insulating layer in the second groove filling 8 and filling the second groove filling 8 with the conductive material 82; it is also possible to fill, for example, the second barrier layer, the second seed layer, etc. after depositing the second insulating layer and before filling the conductive material 82 according to actual process requirements.
And S6, etching the first filling groove 11 region 3 to form a first filling groove 11, wherein the first filling groove 11 is communicated with the second filling groove 8 to form a through hole which penetrates through the thinned silicon substrate 1.
S7, the conductive material 82 is filled in the first filling groove 11. The conductive material 82 is filled with some materials, such as the first seed layer, according to the actual process requirements.
The preparation method of the through TSV structure with the height-depth-width ratio provided by the embodiment of the application adopts a mode of manufacturing the filling grooves on the front side and the back side of the silicon substrate in a segmented mode to form the through TSV structure with the height-depth-width ratio, wherein the scheme that the insulating layer is prepared around the filling grooves before the filling grooves are etched is adopted, the problem that the side walls and the bottoms of the filling grooves at the two ends are easily penetrated in the etching process can be avoided while the through TSV structure with the height-depth-width ratio is obtained, and the alignment window is improved. Due to the advantages, the TSV aperture can be small, the high aspect ratio process is easy to realize, the workload of menu program parameter adjustment or machine structure modification through an etching machine can be greatly reduced, the test period can be shortened, the cost is reduced, and the preparation effect is very obvious. The through type TSV structure with the high depth-width ratio can be applied to a silicon adapter plate to realize three-dimensional packaging of chips with multiple sizes and integration of 2.5D/3D microsystems.
Fig. 2 is a detailed schematic diagram of a process for manufacturing a high aspect ratio through TSV structure according to an embodiment of the present disclosure; the preparation process comprises the following steps:
as shown in fig. 2 (a): a silicon substrate 1 is provided, the silicon substrate 1 comprising opposing first and second surfaces.
As shown in fig. 2 (b): growing a first mask layer 2 on the first surface to serve as a buffer layer and a barrier layer; in the embodiment of the present application, the first mask layer 2 may be formed by oxide preparation.
As shown in fig. 2 (c): defining a first groove filling area 3 on the first surface, and carrying out etching treatment around the first groove filling area 3 to form a first etching groove 4; specifically, the process may include: the peripheral area of the defined first trench-filling region 3 is opened after the yellow mask process and the etching process, resulting in a first etched trench 4.
As shown in fig. 2 (d): the first etched groove 4 is filled with an insulating material to form a first insulating layer 5.
As shown in fig. 2 (e): a first carrier sheet 6 is acquired and the first surface is bonded to the first carrier sheet 6.
As shown in fig. 2 (f): thinning the second surface to obtain a thinned silicon substrate 1; wherein the area above the dotted line is the silicon substrate to be thinned, in the embodiment of the present application, the thinning process includes a chemical mechanical polishing process. Specifically, the process comprises the following steps: and thinning the second surface to enable the thickness of the silicon substrate 1 to be equal to the depth of the finally required through-type TSV. Of course, if the silicon substrate is of an appropriate thickness, this step of thinning may be omitted.
As shown in fig. 2 (g): growing a second mask layer 7 on the second surface; in the embodiment of the present application, the second mask layer 7 may be formed by oxide preparation.
And etching the corresponding area of the first groove filling area 3 defined by the second surface and the first surface to form a second groove filling 8.
As shown in fig. 2 (h): growing a second insulating layer in the second filling groove 8, and filling the conductive material 82; a second barrier layer and/or a second seed layer, etc. may be deposited before filling with the conductive material 82, as desired.
As shown in fig. 2 (i): a second carrier 9 is acquired, the second surface is bonded to the second carrier 9, and the first surface is debonded from the first carrier 6.
And etching the first filling groove 11 region 3 to form a first filling groove 11, wherein the first filling groove 11 is communicated with the second filling groove 8 to form a through hole, and the through hole penetrates through the thinned silicon substrate 1.
As shown in fig. 2 (j): filling the first filling groove 11 with a conductive material 82 according to a related filling processing technique for TSVs; of course, additional thin insulating layers, first seed layers, etc. may be deposited prior to depositing the conductive material 82, as desired.
As shown in fig. 2 (k): and debonding the second surface and the second carrier sheet 9 to form a through TSV structure. As an implementable scheme in the embodiment of the present application, if a through TSV structure with an aspect ratio of 35:1 is prepared according to actual requirements, the aspect ratio of the first filling groove 11 can be selected from 15:1, the aspect ratio of the second filling groove can be selected from 20:1, and the preparation method is adopted to prepare the through TSV structure.
In the first embodiment of the present application, the materials of the first insulating layer 5, the second insulating layer and the third insulating layer include, but are not limited to, silicon dioxide or silicon nitride.
In the first embodiment of the present application, the conductive material 82 includes, but is not limited to, at least one or more of Cu, W, Sn, Ti, Pt, Pd, Ni, or Au.
Example two
The difference between the second embodiment and the first embodiment is: the embodiment is that after a first etching groove is formed on a first surface and an insulating layer is deposited, a second filling groove is formed on a second surface, a second insulating layer is grown in the second filling groove and filled with a conductive material 82, and then a first filling groove 11 is formed on the first surface and filled with the conductive material 82; in the second embodiment, the first etching groove is formed on the first surface and the insulating layer is deposited, the first filling groove 11 is directly formed, the conductive material 82 is deposited in the filling groove, and then the second surface is removed, the second filling groove is formed, the second insulating layer is grown, and the conductive material 82 is filled.
Fig. 3 is a schematic diagram illustrating a process of manufacturing a high-depth-to-width-ratio through TSV structure according to a second embodiment of the present application; the preparation process can be as follows:
as shown in fig. 3 (a): a silicon substrate 1 is provided, the silicon substrate 1 comprising opposing first and second surfaces.
As shown in fig. 3 (b): growing a first mask layer 2 on the first surface to serve as a buffer layer and a barrier layer; in the embodiment of the present application, the first mask layer 2 may be formed by oxide preparation.
As shown in fig. 3 (c): defining a first filling groove 11 area 3 on the first surface, and carrying out etching treatment around the first filling groove 11 area 3 to form a first etching groove 4; specifically, the process may include: the first etched trench 4 is obtained by opening the peripheral area of the defined first filled trench 11 region 3 after the photolithography mask process and the etching process.
As shown in fig. 3 (d): the first etched groove 4 is filled with an insulating material to form a first insulating layer 5.
As shown in fig. 3 (e): and etching the first filling groove 11 region 3 to form the first filling groove 11.
As shown in fig. 3 (f): filling the first filling groove 11 with a conductive material 82; of course, additional thin insulating layers, first seed layers, etc. may be deposited prior to depositing the conductive material 82, as desired.
As shown in fig. 3 (g): a first carrier sheet 6 is acquired and the first surface is bonded to the first carrier sheet 6.
As shown in fig. 3 (h): thinning the second surface to obtain a thinned silicon substrate 1; in the embodiment of the present application, the thinning process includes a chemical mechanical polishing process. Specifically, the process comprises the following steps: and thinning the second surface to enable the thickness of the silicon substrate 1 to be equal to the depth of the finally required through-type TSV. Of course, if the silicon substrate is of an appropriate thickness, this step of thinning may be omitted.
As shown in fig. 3 (i): growing a second mask layer 7 on the second surface; in the embodiment of the present application, the second mask layer 7 may be formed by oxide preparation.
Etching the corresponding area of the first filling groove 11 area 3 defined by the second surface and the first surface to form a second filling groove 8; the first filling groove 11 is communicated with the second filling groove 8 to form a through hole, and the through hole penetrates through the thinned silicon substrate 1.
As shown in fig. 3 (j): growing a second insulating layer in the second filling groove 8, and filling the conductive material 82; where a second barrier layer and/or a second seed layer, etc. may be deposited before filling with conductive material 82, as desired.
As shown in fig. 3 (k): the first surface is debonded from the first carrier 6 to form a through TSV structure.
EXAMPLE III
The third embodiment is different from the first embodiment in that the second filling groove of the second surface also adopts the same process as the first filling groove 11 of the first surface, that is, the area corresponding to the first filling groove 11 area on the second surface is defined as a second filling groove area, a second etching groove is formed by etching around the second filling groove area, and the second etching groove is filled with an insulating material to form a second insulating layer. The size (CD) of the second insulating layer that plays an insulating role in this embodiment is much larger than that in the first embodiment. In this embodiment, the width dimension (CD) of the second etched trench may or may not be the same as the width dimension of the first etched trench.
Fig. 4 is a schematic diagram illustrating a process of manufacturing a TSV structure with a high aspect ratio; the preparation process can be as follows:
as shown in fig. 4 (a): a silicon substrate 1 is provided, the silicon substrate 1 comprising opposing first and second surfaces.
As shown in fig. 4 (b): growing a first mask layer 2 on the first surface to serve as a buffer layer and a barrier layer; in the embodiment of the present application, the first mask layer 2 may be formed by oxide preparation.
As shown in fig. 4 (c): defining a first filling groove 11 area 3 on the first surface, and carrying out etching treatment around the first filling groove 11 area 3 to form a first etching groove 4; specifically, the process may include: the first etched trench 4 is obtained by opening the peripheral area of the defined first filled trench 11 region 3 after the photolithography mask process and the etching process.
As shown in fig. 4 (d): the first etched groove 4 is filled with an insulating material to form a first insulating layer 5.
As shown in fig. 4 (e): a first carrier sheet 6 is acquired and the first surface is bonded to the first carrier sheet 6.
As shown in fig. 4 (f): thinning the second surface to obtain a thinned silicon substrate 1; in an embodiment of the present application, the thinning process includes a chemical mechanical polishing process. Specifically, the process comprises the following steps: and thinning the second surface to enable the thickness of the silicon substrate 1 to be equal to the depth of the finally required through-type TSV. Of course, if the silicon substrate is of an appropriate thickness, this step of thinning may be omitted.
As shown in fig. 4 (g): growing a second mask layer 7 on the second surface; in the embodiment of the present application, the second mask layer 7 may be formed by oxide preparation.
Defining a corresponding area of the first filling groove 11 area 3 as a second filling groove area on the second surface, and carrying out etching treatment around the second filling groove area to form a second etching groove 10; and filling an insulating material in the second etching groove 10 to form a second insulating layer.
And etching the second filled groove region to form a second filled groove 8.
As shown in fig. 4 (h): growing a second insulating layer in the second filling groove 8, and filling the conductive material 82; a second barrier layer and/or a second seed layer, etc. may also be deposited before filling with conductive material 82, as desired.
As shown in fig. 4 (i): a second carrier 9 is acquired, the second surface is bonded to the second carrier 9, and the first surface is debonded from the first carrier 6.
And etching the first filling groove 11 region 3 to form a first filling groove 11, wherein the first filling groove 11 is communicated with the second filling groove 8 to form a through hole, and the through hole penetrates through the thinned silicon substrate 1.
As shown in fig. 4 (j): filling the first filling groove 11 with a conductive material 82 according to a related filling processing technique for TSVs; of course, additional thin insulating layers, first seed layers, etc. may be deposited prior to depositing the conductive material 82, as desired.
As shown in fig. 4 (k): and debonding the second surface from the second carrier sheet 9 to form the through-type TSV structure 10. As an implementable solution of the third embodiment of the present application, if a through-type TSV structure with an aspect ratio of 35:1 is prepared according to actual requirements, the aspect ratio of the first filling groove 11 can be selected to be 15:1, the aspect ratio of the second filling groove is selected to be 20:1, and the preparation method is adopted to prepare the through-type TSV structure.
Example four
The fourth embodiment is different from the second embodiment in that the second filling groove of the second surface also adopts the same process as the first filling groove 11 of the first surface, that is, the area on the second surface corresponding to the area of the first filling groove 11 is defined as the second filling groove area, a second etching groove is formed by etching around the second filling groove area, and the second etching groove is filled with an insulating material to form a second insulating layer. The size (CD) of the second insulating layer which plays a role of insulation in this embodiment is much larger than that in the first embodiment. In this embodiment, the width dimension (CD) of the second etched trench may or may not be the same as the width dimension of the first etched trench.
Fig. 5 is a schematic diagram illustrating a process of manufacturing a TSV structure with a high aspect ratio; the preparation process can be as follows:
as shown in fig. 5 (a): a silicon substrate 1 is provided, the silicon substrate 1 comprising opposing first and second surfaces.
As shown in fig. 5 (b): growing a first mask layer 2 on the first surface to serve as a buffer layer and a barrier layer; in the embodiment of the present application, the first mask layer 2 may be formed by oxide preparation.
As shown in fig. 5 (c): defining a first filling groove 11 area 3 on the first surface, and carrying out etching treatment around the first filling groove 11 area 3 to form a first etching groove 4; specifically, the process may include: the first etched trench 4 is obtained by opening the peripheral area of the defined first filled trench 11 region 3 after the photolithography mask process and the etching process.
As shown in fig. 5 (d): the first etched groove 4 is filled with an insulating material to form a first insulating layer 5.
As shown in fig. 5 (e): and etching the first filling groove 11 region 3 to form the first filling groove 11.
As shown in fig. 5 (f): filling the first filling groove 11 with a conductive material 82; of course, additional thin insulating layers, first seed layers, etc. may also be deposited as desired prior to depositing conductive material 82.
As shown in fig. 5 (g): a first carrier sheet 6 is acquired and the first surface is bonded to the first carrier sheet 6.
As shown in fig. 5 (h): thinning the second surface to obtain a thinned silicon substrate 1; in an embodiment of the present application, the thinning process includes a chemical mechanical polishing process. Specifically, the process comprises the following steps: and thinning the second surface to enable the thickness of the silicon substrate 1 to be equal to the depth of the finally required through-type TSV. Of course, if the silicon substrate is of an appropriate thickness, this step of thinning may be omitted.
As shown in fig. 5 (i): growing a second mask layer 7 on the second surface; in the embodiment of the present application, the second mask layer 7 may be formed by oxide preparation.
Defining a corresponding area of the first filling groove 11 area 3 as a second filling groove area on the second surface, and carrying out etching treatment around the second filling groove area to form a second etching groove; and filling an insulating material in the second etching groove to form a second insulating layer.
And etching the second filled groove region to form a second filled groove 8.
The first filling groove 11 is communicated with the second filling groove 8 to form a through hole, and the through hole penetrates through the thinned silicon substrate 1.
As shown in fig. 5 (j): a second insulating layer is grown in the second filled trench 8 and filled with a conductive material 82.
As shown in fig. 5 (k): the first surface is debonded from the first carrier 6 to form a through TSV structure.
The first to fourth embodiments of the present application disclose several methods for preparing a TSV structure with a high aspect ratio and a low aspect ratio, which are characterized in that when a first or second filling groove region is defined on any side, a first or second etching groove is formed by etching around the first or second filling groove region, and an insulating material is filled in the first or second etching groove to form a first or second insulating layer. Some solutions in the prior art adopt a scheme of growing thin insulating layers in the first and second filling grooves, and when the barrier layer at the bottom of the filling groove is etched on the other side, the etching rate of the sidewall insulating layer matches the etching rate of the bottom, which easily causes the sidewall insulating layer to be etched through, so that the conductive material in the filling groove is electrically connected with the silicon substrate (as shown in fig. 6 (a); in the prior art, the first filling groove and the second filling groove are not aligned due to alignment errors of the device, and the filling grooves are misaligned and butted during etching, so that the conductive material in the filling grooves is electrically connected with the silicon substrate (as shown in fig. 6 (b)). The width of the insulating layer prepared by the preparation method provided by the embodiment of the application can be far larger than that of the insulating layer deposited in the filling groove in the prior art, so that the insulating layer or the barrier layer at the bottom of the filling groove can be effectively ensured to be etched completely when the other surface is etched, the possibility that the first or second insulating layer is etched to be penetrated so that the conductive material is contacted with the related material of the substrate is greatly reduced, and the quality is improved; meanwhile, the alignment process window required by the front and back surfaces is greatly improved, and the quality problem caused by the alignment problem is also improved.
EXAMPLE five
The fifth embodiment of the application provides a through type TSV structure with a high depth-to-width ratio, which can be prepared by the above method, and as shown in fig. 7, the structure includes a silicon substrate 1, and a first filling groove 11 and a second filling groove 8 are formed in the silicon substrate.
The first filling groove 11 is communicated with the second filling groove 8 to form a through hole, and the through hole penetrates through the silicon substrate.
The first filling groove 11 and the second filling groove 8 are filled with conductive materials.
A first insulating layer and a second insulating layer are respectively arranged between the conductive materials in the first filling groove 11 and the second filling groove 8 and the silicon substrate; the thickness of the first insulating layer is larger than that of the second insulating layer, and a shoulder-shaped or step-shaped insulating layer is formed.
A first etching groove is formed in the periphery of the first filling groove 11, and a first insulating layer is positioned in the first etching groove; wherein the first insulating layer 5 is prepared by filling an insulating material into the first etched groove surrounding the first filled groove 11.
In the fifth embodiment of the present application, the second insulating layer may be disposed in the second filling groove 8 as shown in fig. 7; at this time, an annular shoulder 12 exists between the first insulating layer 5 and the second insulating layer 81 due to a difference in the size (CD) of the first insulating layer 5 and the second insulating layer.
In the fifth embodiment of the present application, the second insulating layer may also have a structure as shown in fig. 8, a second etching groove is disposed around the second filling groove 8, and the second insulating layer 81 is located in the second etching groove. The first insulating layer 5 and the second insulating layer 81 are prepared by etching and filling insulating materials around the first filling groove 11 and the second filling groove 8 respectively. Wherein the dimensions of the first insulating layer 5 and the second insulating layer 81 are preferably the same, in which case the photolithographic mask patterns defining the first etched trench and the second etched trench may be the same or even the same, which may save costs.
In the fifth embodiment of the present invention, the silicon substrate 1 may include a first surface and a second surface, the first surface is connected to the first mask layer 2, and the second surface is connected to the second mask layer 7.
In the fifth embodiment of the present application, the materials of the first insulating layer 5 and the second insulating layer include, but are not limited to, silicon dioxide or silicon nitride.
The conductive material includes, but is not limited to, at least one or a combination of more of Cu, W, Sn, Ti, Pt, Pd, Ni, or Au.
The fifth embodiment of the application further provides a silicon interposer, which comprises any one of the above through type TSV structures with high depth-width ratios.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

Claims (13)

1. A preparation method of a high-aspect-ratio through TSV structure is characterized by comprising the following steps:
providing a silicon substrate comprising opposing first and second surfaces;
defining a first filling groove area on the first surface, and carrying out etching treatment around the first filling groove area to form a first etching groove; filling an insulating material in the first etching groove to form a first insulating layer;
etching the corresponding area of the first filling groove area on the second surface to form a second filling groove, growing a second insulating layer in the second filling groove, and filling a conductive material in the second filling groove, wherein the thickness of the first insulating layer is greater than that of the second insulating layer;
etching the first filling groove region to form a first filling groove;
the first filling groove is communicated with the second filling groove to form a through hole, and the through hole penetrates through the silicon substrate;
and filling a conductive material in the first filling groove.
2. The method for manufacturing a TSV structure with a high aspect ratio according to claim 1, wherein before etching the second surface to form the second filling groove, thinning the second surface to obtain a thinned silicon substrate.
3. The method for manufacturing a high aspect ratio through TSV structure according to claim 1 or 2, wherein a second barrier layer and/or a second seed layer is filled in the second filling trench after the step of growing a second insulating layer in the second filling trench and before the step of filling a conductive material in the second filling trench.
4. The method for preparing a high aspect ratio through-type TSV structure according to claim 1 or 2, wherein said step of defining a first filled trench region on said first surface further comprises: a first mask layer is grown on the first surface.
5. The method for preparing a high aspect ratio through-type TSV structure according to claim 1 or 2, wherein before the step of performing an etching process on the second surface to form a second filling trench corresponding to the first filling trench region, the method further comprises: and growing a second mask layer on the second surface.
6. The method for preparing a high aspect ratio through-type TSV structure according to claim 1 or 2, wherein the step of performing an etching process on the second surface to form a second filled trench corresponding to the first filled trench region, and growing a second insulating layer in the second filled trench is replaced by: defining a region corresponding to the first groove filling region on the second surface as a second groove filling region, performing etching treatment around the second groove filling region to form a second etching groove, filling an insulating material in the second etching groove to form a second insulating layer, and performing etching treatment in the second groove filling region to form a second filling groove.
7. The method of claim 2, further comprising, after any processing steps are performed on the first surface and before any processing steps are performed on the second surface: acquiring a first slide, and bonding the first surface with the first slide;
after the step of processing the second surface is completed, the method further comprises the following steps: debonding the first surface from the first slide.
8. The method of claim 2, further comprising, after any processing steps are performed on the second surface and before any processing steps are performed on the first surface: acquiring a second slide, and bonding the second surface with the second slide;
after the step of processing the first surface is completed, the method further comprises the following steps: debonding the second surface from the second slide.
9. The method for preparing a high aspect ratio through-type TSV structure according to any one of claims 1, 2, 7 and 8, wherein the materials of the first insulating layer and the second insulating layer each include: silicon dioxide or silicon nitride; the conductive material includes: at least one of Cu, W, Sn, Ti, Pt, Pd, Ni, or Au.
10. A high-aspect-ratio through type TSV structure comprises a silicon substrate, wherein a first filling groove and a second filling groove are formed in the silicon substrate; the first filling groove is communicated with the second filling groove to form a through hole, and the through hole penetrates through the silicon substrate; the first filling groove and the second filling groove are filled with conductive materials; a first insulating layer and a second insulating layer are respectively arranged between the conductive materials in the first filling groove and the second filling groove and the silicon substrate, and the silicon substrate etching device is characterized in that a first etching groove is formed in the periphery of the first filling groove, the first insulating layer is positioned in the first etching groove, and the second insulating layer is positioned in the second filling groove; the thickness of the first insulating layer is larger than that of the second insulating layer, and a shoulder-shaped or step-shaped insulating layer is formed.
11. A high-aspect-ratio through type TSV structure comprises a silicon substrate, wherein a first filling groove and a second filling groove are formed in the silicon substrate; the first filling groove is communicated with the second filling groove to form a through hole, and the through hole penetrates through the silicon substrate; the first filling groove and the second filling groove are filled with conductive materials; and a first insulating layer and a second insulating layer are respectively arranged between the conductive materials in the first filling groove and the second filling groove and the silicon substrate, and the silicon substrate etching device is characterized in that the first insulating layer and/or the second insulating layer are formed by filling insulating materials in an etching groove after the etching groove is formed by etching the surface of the silicon substrate around the first filling groove and/or the second filling groove.
12. The high aspect ratio through-TSV structure of claim 10 or 11, wherein the first and second insulating layers each comprise: silicon dioxide or silicon nitride;
the conductive material includes: at least one of Cu, W, Sn, Ti, Pt, Pd, Ni, or Au.
13. A silicon interposer comprising a high-depth-to-width-ratio pass-through TSV structure as claimed in claim 10 or claim 11.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376689A (en) * 2011-09-09 2012-03-14 华中科技大学 Through silicon hole structure with step and manufacture process of through silicon hole
WO2013056519A1 (en) * 2011-10-21 2013-04-25 中国科学院上海微系统与信息技术研究所 Wafer-level through-silicon via transmission structure applicable to microwave band and manufacturing method thereof
CN103258788A (en) * 2013-04-17 2013-08-21 华中科技大学 Through hole interconnection structure manufacturing method based on bidirectional filling and through hole interconnection structure product
US9401323B1 (en) * 2015-04-03 2016-07-26 International Business Machines Corporation Protected through semiconductor via (TSV)
CN106057757A (en) * 2016-07-08 2016-10-26 桂林电子科技大学 Silicon through hole structure and manufacturing method thereeof
JP2017022223A (en) * 2015-07-09 2017-01-26 大日本印刷株式会社 Through electrode substrate, method of manufacturing the same, and interposer and semiconductor device using the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6806579B2 (en) * 2003-02-11 2004-10-19 Infineon Technologies Ag Robust via structure and method
KR20100112669A (en) * 2009-04-10 2010-10-20 삼성전자주식회사 Semiconductor device and method of manufacturing the same
US9018094B2 (en) * 2011-03-07 2015-04-28 Invensas Corporation Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376689A (en) * 2011-09-09 2012-03-14 华中科技大学 Through silicon hole structure with step and manufacture process of through silicon hole
WO2013056519A1 (en) * 2011-10-21 2013-04-25 中国科学院上海微系统与信息技术研究所 Wafer-level through-silicon via transmission structure applicable to microwave band and manufacturing method thereof
CN103258788A (en) * 2013-04-17 2013-08-21 华中科技大学 Through hole interconnection structure manufacturing method based on bidirectional filling and through hole interconnection structure product
US9401323B1 (en) * 2015-04-03 2016-07-26 International Business Machines Corporation Protected through semiconductor via (TSV)
JP2017022223A (en) * 2015-07-09 2017-01-26 大日本印刷株式会社 Through electrode substrate, method of manufacturing the same, and interposer and semiconductor device using the same
CN106057757A (en) * 2016-07-08 2016-10-26 桂林电子科技大学 Silicon through hole structure and manufacturing method thereeof

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