CN111585683A - High-reliability clock synchronization system and method for time-sensitive network - Google Patents
High-reliability clock synchronization system and method for time-sensitive network Download PDFInfo
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Abstract
The invention discloses a high-reliability clock synchronization system and method for a time-sensitive network, and relates to the technical field of communication. The network is divided into two levels according to the clock synchronization function, the top network adopts a master-slave synchronization method to realize time and frequency offset correction and compares the time and frequency offset correction with the clock reference of the bottom network, so that the network reliability is ensured; the bottom layer network adopts a distributed structure to realize the calculation release and the frequency release of the time reference. The invention reduces the dependence of network clock reference on GM, and improves the fault tolerance and reliability; the roles of all the devices in the network are dynamically distributed, so that the clustering phenomenon is avoided, and the clock synchronization of all the network devices is realized; meanwhile, time and frequency offset correction are considered, synchronization of a network system clock and UTC in time and frequency is achieved, the problems that time offset correction precision is not high and frequency offset correction is slow in a traditional clock synchronization method are effectively solved, synchronization precision is improved, and synchronization speed is improved.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a high-reliability clock synchronization system and method for a time-sensitive network.
Background
A Time Sensitive Network (TSN) is an emerging network that can provide deterministic services for modern industries, and is an extension of traditional ethernet. The TSN establishes a universal time sensitive mechanism for the traditional Ethernet protocol, and ensures the time certainty of network data transmission.
The key link for constructing the TSN is to design a TSN gateway, and an important basis of the TSN is precise clock synchronization, so the TSN gateway needs to realize the precise clock synchronization. Clock synchronization provides uniform and accurate time for all devices of the TSN, which is the basis for the normal operation of the TSN. If there is no precise clock synchronization, the TSN cannot accurately control the switching of the gates in the gated list during traffic scheduling, and the TSN will generate a large delay. Thus, TSNs place great demands on the accuracy and reliability of clock synchronization between devices. Due to the complexity of the network structure and the great dependence of clock synchronization on hardware, how to realize the high-precision and high-reliability clock synchronization of the TSN is a very challenging problem.
Clock synchronization schemes commonly employed today include IEEE 802.1AS and AS 6802. The clock synchronization mode of IEEE 802.1AS is Master-slave synchronization, an optimal Master clock (GM) must be selected, the optimal Master clock is synchronized with Coordinated Universal Time (UTC) by means of GPS Time service and the like, and is used AS a global clock reference, the GM is used AS a Master clock, the lower layer devices of the GM are used AS slave clocks, and are synchronized with the lower layer devices by Master-slave synchronization, and the lower layer devices are used AS Master clocks of the lower layer devices and are also synchronized in a Master-slave manner. The AS6802 is a distributed synchronization method, has no concept of a Master clock, and defines a synchronization Master controller (SM), a Compression Master Controller (CM), and a synchronization Slave Controller (SC). The SM sends a Protocol Control Frame (PCF) to the CM, the CM calculates a compression correction value after performing operations such as curing and compression, the CM sends the correction value to the SM and the SC, and the SM and the SC adjust a local clock according to the correction value.
After retrieval, the publication number is CN 109818702A, the name is 'a system and a method for realizing IEEE 802.1AS clock synchronization function', and the IEEE 802.1AS method is adopted to realize clock synchronization. The master-slave clocks adopt a one-step synchronization method on a platform with software and hardware collaborative design, two steps of delay measurement and time synchronization are combined into one, the complexity of a time synchronization system is simplified, in each synchronous interaction process, the master-slave clocks respectively collect two timestamps, the slave clocks calculate master-slave clock offset values according to four timestamp information collected by the master-slave clocks, and the slave clocks are calibrated according to the master-slave clock offset values to complete the clock synchronization of network equipment in a communication network system. The publication number is CN110299957A entitled "crystal frequency digital compensation-based time-triggered ethernet clock synchronization method", which solves the problem of frequency offset calibration in the clock synchronization process. The method is based on an AS6802 protocol to set up a time-triggered Ethernet model, and a clock synchronization process is simulated through network calculation. And designing a crystal oscillator frequency-temperature characteristic curve lookup table and an improved local clock module containing a crystal oscillator frequency digital compensation module by using a Verilog HDL tool, and applying the lookup table and the improved local clock module to a network node hardware model.
IEEE 802.1AS adopts a master-slave synchronization mode, and simultaneously assumes that the downlink delay from a master clock to a slave clock is equal to the uplink delay from the slave clock to the master clock, but the uplink delay and the downlink delay are often unequal in an actual network, so that a certain error is generated during master-slave synchronization, especially in a TSN (time sensitive network), because the TSN aims to realize the combination of time sensitive mechanisms of various types of networks, the time delay asymmetry brought by heterogeneous networks is more serious. Meanwhile, the error is accumulated in the multi-stage network, and finally the overall error is large. Although the IEEE 802.1AS adopts a hardware-assisted time stamping method to reduce errors caused by unequal uplink and downlink delays, the errors are still not eliminated, and the dependence degree of synchronization precision on hardware is large.
The global clock reference in IEEE 802.1AS is greatly dependent on GM, if the GM clock has a large offset, the clock of the entire network will generate a large error, although the GM can be adjusted by using the optimal master clock algorithm, since the information such AS super master clock hierarchy, identification, clock stability, etc. of all network devices need to be compared, when the network scale is large, the switching speed will be slow, and if the difference between the selected GM clock frequency and UTC is large, the error will be increased accumulatively.
The AS6802 lacks a function of synchronizing with the UTC, and can only implement clock synchronization in the local area network, and meanwhile, the AS6802 may have a clustering phenomenon, which may result in that global clock synchronization cannot be implemented, and although a clustering detection mechanism is introduced, algorithm complexity is increased.
IEEE 802.1AS and AS6802 both consider only instantaneous time synchronization and do not consider changes in crystal frequency, i.e., the clock synchronization is only time synchronization, and does not achieve clock frequency synchronization, and cannot correct clock frequency offset. When the frequency deviation is large, under the same clock synchronization precision requirement, a shorter synchronization period is needed, the synchronization frequency is higher, a large amount of network bandwidth is occupied, and the network load is increased; if the same synchronization period is used, the synchronization precision is reduced.
Some current methods that consider both clock offset correction and frequency offset correction only consider frequency offset correction of independent devices, such as only considering the effect of temperature on clock frequency on a single device and compensating; some methods adopt master-slave frequency synchronization, and the frequency of a slave clock is only related to the frequency of a master clock at the upper stage, so that frequency offset correction errors can be accumulated in a large network continuously.
The existing method for separately considering frequency offset correction generally needs a long period of time for data acquisition, and then performs offline calculation, so that the synchronization time is prolonged, and the frequency offset cannot be corrected in real time.
Therefore, those skilled in the art are devoted to develop a two-layer highly reliable clock synchronization system and method for the coordinated adjustment of clock offset and frequency offset of time sensitive network. The dependence of a network clock reference on a GM is reduced, and the fault tolerance and reliability of the network are improved; the synchronization of the network system clock and the UTC on time and frequency is realized; the phenomenon of agglomeration is avoided, and the clock synchronization of the whole network equipment is realized; the method solves the problems of low clock offset correction precision and slow frequency offset correction, improves the synchronization precision, reduces the synchronization time period and improves the synchronization speed.
Disclosure of Invention
In view of the above defects in the prior art, the technical problem to be solved by the present invention is to realize synchronization of the network system clock reference with UTC in time and frequency, introduce a fault-tolerant mechanism, reduce the degree of dependence of the network clock reference on GM, and improve the reliability of the network; the problem of restarting a network clock synchronization system caused by clock clustering of partial equipment in a network and synchronization of only partial equipment is avoided; the method realizes the fusion of clock offset correction and online frequency offset correction in the clock synchronization process, improves the synchronization speed and the synchronization precision, and reduces the synchronization period.
In order to achieve the above object, the present invention provides a high-reliability clock synchronization method for a time-sensitive network, comprising the following steps:
step one, selecting a certain device in a network as a GM according to an optimal master clock algorithm;
step two, starting at each integration period, each device transmits local clock information to the GM, and the GM selects roles of each device, including FM, SM, CM and SC;
step three, after confirming the roles of all the devices, the GM writes role distribution information into a PCF frame; after receiving the role distribution information frame, each device determines the roles, completes state conversion of each role and sends a role confirmation information frame to the GM;
after receiving the role confirmation information frame returned by each device, the GM starts time synchronization with the SM and frequency synchronization with the FM;
step five, the SM generates PCF frames after completing time synchronization with the GM, the PCF frames are sent to the CM, the CM calculates a compression correction value according to the received PCF frames, the CM generates new PCF frames after adjusting a local clock according to the compression correction value, and the reference is sent to the GM, the SM, the FM and the SC;
step six, after receiving PCF frames sent by the CM, the SM, the FM and the SC carry out local clock adjustment;
seventhly, in the finishing stage of each cluster cycle, namely the finishing stage of the last integration cycle of each cluster cycle, the GM judges whether the GM is normal or not and feeds information back to each device;
step eight, if the FM receives the GM normal information frame, the FM processes the data transmission delay measured value which is collected in one cluster period and sent to the FM by the GM, calculates clock frequency offset, then adjusts the local clock frequency of the FM, and simultaneously sends the frequency value after the FM adjustment to the SM, the CM and the SC, and the SM, the CM and the SC adjust the local clock frequency according to the received frequency adjustment information; if the FM receives the GM abnormal information frame, the FM directly issues the clock frequency of the FM to lower-layer equipment, and the lower-layer equipment adjusts according to the FM clock;
step nine, starting at the next cluster cycle, each device adjusts a synchronization strategy according to the state information sent by the GM; if the GM normal information frame is received, jumping to the second step, and re-selecting the roles of the devices; and if the GM abnormal information frame is received, jumping to the fifth step.
Further, the local clock information includes a local clock time value, local crystal oscillator frequency information, a local crystal oscillator aging degree, and a hop count from the device to the GM.
Further, when the SM is selected in the second step, the devices are clustered according to a device clustering rule, and an SM cluster is selected according to a principle that devices in the cluster are the most, wherein the devices in the cluster are the SM.
Further, the device clustering rule is to perform clock distribution detection according to the clock information of the devices, and group devices with similar clocks into a cluster.
Further, the device clustering rule is to determine a network hierarchy structure, and take the hop count of the device from the GM as a grading standard, where the hop count from the GM represents the grade number of the device; and each level of network independently performs clock distribution detection according to the clock information of the equipment, and the equipment with similar clocks form a cluster.
Further, in the second step, when the FM is selected, the device with the most stable frequency is selected as the FM according to the information such as the frequency information of the local crystal oscillator and the aging degree of the local crystal oscillator.
Further, when the CM is set in the step two, the total number of hops for each SM to reach the CM is guaranteed to be minimum.
Further, in the seventh step, the rule for the GM to determine whether the GM itself is normal is: the GM compares the global clock reference of the distributed network calculated by the CM with the local clock of the GM, if the time difference between the global clock reference and the local clock of the GM is less than or equal to a preset threshold value, the GM is considered to be in a normal state, and then the GM sends a GM normal mark frame to all equipment; and if the difference value is larger than a preset threshold value, the GM is considered to be in an abnormal state, and then the GM sends a GM abnormal mark frame to all the devices.
Further, the GM, the FM, the SM, the CM, and the SC device include a relay device and a terminal device.
The invention also provides a high-reliability clock synchronization system facing the time sensitive network, which comprises:
a real-time clock module: the precise timing is realized according to the crystal oscillator frequency and the counter, and the clock adjusting function is included, so that the correction can be carried out according to the calculated clock offset and frequency deviation;
an input module: the real-time clock module is responsible for receiving data and recording a clock value of the real-time clock module when receiving the data, namely receiving time;
an output module: the real-time clock module is responsible for sending data, and a timestamp is added to the data according to the clock value of the real-time clock module when the data is sent, namely the sending time;
a state management module: the system comprises a state processing module, a state transfer module, a state management module and a role distribution module, wherein the state processing module and the state transfer module are used for managing different states of equipment, and the state management module can be used for switching different state sets according to received role distribution information and switching different states according to received information;
a configuration management module: providing a uniform interface for parameters used by all modules, and uniformly configuring all parameters of the system, including the maximum transmission delay of a network, a cluster period, an integration period and the size of an observation window;
a calculation module: providing calculation functions for a system, wherein the calculation functions comprise comparison calculation of clock references calculated by a GM clock and a CM, calculation of data transmission delay, clock offset calculation of master-slave synchronization, calculation of clock frequency deviation, a solidification function and a compression function, and the calculation module starts different calculation functions according to different state sets of a state management module;
a data storage module: mainly providing a data storage function, including providing the data storage function for FM, and storing data frame transmission delay from the GM to the FM recorded by the FM in a cluster period; past and current state information is stored for the state management module, so that network information query is facilitated; temporary or permanent data storage is provided for the computing module, so that the computing module can be conveniently inquired and called; and configuring the parameter information configured by the management module.
Compared with the prior art, the invention has the following obvious substantive characteristics and obvious advantages:
1. a distributed clock calculation mechanism is introduced, the dependence of a network clock reference on a GM is reduced, and the fault tolerance and reliability of the network are improved.
2. And meanwhile, the synchronization of the network system clock and the UTC in time and frequency is realized.
3. The roles of all the devices in the network are dynamically distributed, the phenomenon of clustering is avoided, and the clock synchronization of all the network devices is realized.
4. Meanwhile, clock offset correction and frequency offset correction are considered, a global frequency value is obtained through frequency offset estimation of FM and GM, the clock offset correction ensures the rapidity of synchronization, the frequency offset correction ensures the accuracy of synchronization, and the problems that in a traditional clock synchronization method, the clock offset correction is not high in precision and the frequency offset correction is slow are effectively solved, so that the synchronization precision is improved, the synchronization time period is shortened, and the synchronization speed is improved.
The conception, the specific structure and the technical effects of the present invention will be further described with reference to the accompanying drawings to fully understand the objects, the features and the effects of the present invention.
Drawings
FIG. 1 is a diagram of a clock synchronization network in accordance with a preferred embodiment of the present invention;
FIG. 2 is a diagram of the system operating cycle of a preferred embodiment of the present invention;
FIG. 3 is a diagram of various types of node information interactions in accordance with a preferred embodiment of the present invention;
FIG. 4 is a block diagram of a clock synchronization system in accordance with a preferred embodiment of the present invention;
FIG. 5 is a diagram of a GM state machine in accordance with a preferred embodiment of the present invention;
FIG. 6 is a diagram of an FM state machine in accordance with a preferred embodiment of the present invention;
FIG. 7 is a diagram of a SM state machine in accordance with a preferred embodiment of the present invention;
FIG. 8 is a CM state machine diagram of a preferred embodiment of the present invention;
FIG. 9 is a diagram of an SC state machine in accordance with a preferred embodiment of the present invention.
Detailed Description
The technical contents of the preferred embodiments of the present invention will be more clearly and easily understood by referring to the drawings attached to the specification. The present invention may be embodied in many different forms of embodiments and the scope of the invention is not limited to the embodiments set forth herein.
In the drawings, structurally identical elements are represented by like reference numerals, and structurally or functionally similar elements are represented by like reference numerals throughout the several views. The size and thickness of each component shown in the drawings are arbitrarily illustrated, and the present invention is not limited to the size and thickness of each component. The thickness of the components may be exaggerated where appropriate in the figures to improve clarity.
Fig. 1 is a network structure diagram of a clock synchronization network according to a preferred embodiment of the present invention. The network is divided into two levels according to the clock synchronization function, the network comprises two layers of networks, the top layer network comprises GM, SM1, SM2 and FM, and the bottom layer network comprises SM1, SM2, FM, CM and SC. The top network adopts a master-slave synchronization method to realize clock offset correction and frequency offset correction, and compares the clock offset correction and the frequency offset correction with the clock reference of the bottom network to ensure the reliability of the network; the underlying network adopts a distributed structure to realize the calculation release and the frequency release of the clock reference.
The system operation cycle is shown in fig. 2. Defining a cluster cycle as the traffic with the highest requirement for each pair of transmission delays in the network, i.e. the least common multiple of a Time-Critical (TC) flow scheduling cycle, for example, Time-Triggered (TT) flows of a TTE network and a TSN network. The integration period is a clock synchronization period, the integration period is a cluster period/N, and N may be any positive integer. The integration period comprises a 301 stage, a 302 stage and a 303 stage.
The information interaction flow among the nodes of each type is shown in fig. 3, and the structure of each node, i.e., the structure of the clock synchronization system, is shown in fig. 4.
The high-reliability clock synchronization system facing the time sensitive network comprises the following modules:
a real-time clock module: the precise timing is realized according to the crystal oscillator frequency and the counter, and the clock adjusting function is included, so that the correction can be carried out according to the calculated clock offset and frequency deviation;
an input module: the real-time clock module is responsible for receiving data and recording a clock value of the real-time clock module when receiving the data, namely receiving time;
an output module: the real-time clock module is responsible for sending data, and a timestamp is added to the data according to a clock value of the real-time clock module when the data is sent, namely sending time;
a state management module: the method comprises the steps of state processing and state transition, different states of equipment are managed, a state management module can carry out conversion of different state sets according to received role distribution information, and meanwhile, conversion of different states is carried out according to the received information.
A configuration management module: and providing a uniform interface for parameters used by all modules, and uniformly configuring all parameters of the system, including parameters such as the maximum transmission delay of a network, the size of a cluster cycle and an integration cycle, the size of an observation window and the like.
A calculation module: the system is provided with a calculation function which comprises a plurality of calculation functions, wherein the calculation functions comprise comparison calculation of clock references calculated by a GM clock and a CM, calculation of data transmission delay, calculation of clock offset of master-slave synchronization, calculation of clock frequency deviation, a solidification function, a compression function and the like, and the calculation module starts different calculation functions according to different state sets of the state management module.
A data storage module: mainly providing a data storage function, including but not limited to providing the data storage function for the FM, and storing GM-to-FM data frame transmission delay recorded by the FM in a cluster period; past and current state information is stored for the state management module, so that network information query is facilitated; temporary or permanent data storage is provided for the calculation module, and the calculation module is convenient to query and call; the parameter information configured by the configuration management module is also stored in the data storage module.
GM state machine as shown in fig. 5, FM state machine as shown in fig. 6, SM state machine as shown in fig. 7, CM state machine as shown in fig. 8, SC state machine as shown in fig. 9, SM comprising SM1 and SM 2.
The high-reliability clock synchronization method facing the time sensitive network comprises the following steps:
the first step is as follows: selecting a GM by using an optimal master clock algorithm, and enabling the GM to enter an integration state.
The second step is that: at the beginning of each integration period, that is, at the stage 301 shown in fig. 3, all devices except the GM send local clock information of each device to the GM, the GM defines a device with the most stable clock frequency as a frequency master controller (FM), after the FM is excluded, the GM performs clock distribution detection according to the clock information of the remaining devices, the devices with similar time form a cluster, and the cluster with the most devices in the cluster is set as an SM cluster, where the devices are SMs. And simultaneously, a plurality of CMs are set, the total hop count of each SM reaching the CM is ensured to be minimum, and the rest equipment is set to be SC, and the SM, the FM, the CM and the SC enter an integrated state.
Another selection scheme of the SM is to determine a network hierarchy structure, and use the hop count of the device from the GM as a ranking standard, that is, the hop count from the GM represents the number of levels of the device. And ensuring that each level of network has at least one SM, independently determining SM clusters of each level according to the original scheme by each level of network, wherein the devices in the clusters are SMs. The first scheme has at least one SM, and the second scheme has at least N SMs, wherein N is the number of stages of the network. In the implementation difficulty, the first scheme is simple, only the clock distribution of the network needs to be known, the second scheme is complex, the hierarchical structure of the network needs to be known, the clock distribution is determined according to the hierarchical structure, but the influence of the network structure is fully considered in the second scheme, and the selected SM is more representative.
The GM, FM, SM, CM, SC devices include, but are not limited to, relay devices such as routers and switches in the network, and terminal devices, including hosts, mobile terminals, controllers, and the like.
The third step: after determining the role of each device, the GM writes the role allocation information into the PCF data frame and sends the PCF data frame to other devices, after receiving the role allocation frame, each device determines the role, and each role completes state conversion and sends a role confirmation frame to the GM. The SM and FM enter a master-slave synchronization state and the CM and SC enter a distributed synchronization state.
The fourth step: after receiving the role confirmation information returned by each device, the GM enters the phase 302 shown in fig. 3, and starts clock synchronization with the SM1 and the SM2 and frequency synchronization with the FM. The GM transmits a sync frame and a following frame to the SM1 and SM2, the following frame including a transmission time t of the sync frame1The GM simultaneously sends the synchronous frame and the following frame to the FM, the FM records the transmission delay of the two data frames and stores the transmission delay in the data storage module, and the SM1 and SM2 record the sending time t of the synchronous frame1And a reception time t2Then, the SMs 1 and 2 transmit a delay request frame to the GM, and the GM transmits a delay response frame to the SMs 1 and 2, the delay response frame including the reception time t of the delay request frame4Meanwhile, the delayed response frame transmitted by the GM is also transmitted to the FM, SM1 and SM2 to record the transmission time t of the delayed request frame3And a reception time t4. SM1 and SM2 according to t1、t2、t3And t4The clock offset offs from the GM is calculated according to the following formula for four timeset and correction:
fifthly, after clock synchronization between the SM1 and SM2 and the GM is completed, the stage 303 shown in FIG. 3 is entered, a distributed synchronization state is entered, PCF frames are generated, the PCF frames are sent to the CM, the CM starts an observation window after receiving the PCF frames, the collected PCF frames are sent to a calculation module for solidification after a plurality of observation windows are started, the sending sequence of each PCF frame is restored, then compression processing is carried out, a compression correction value is calculated, the CM generates new PCF frames after adjusting a local clock, and the new PCF frames are sent to the GM, the SM1, the SM2, the FM and the SC. The compression correction value calculation method is as follows:
pi＝ppi-pp1
wherein pp isiIs the i-th collected solidification point, piThe time difference between the ith solidification point and the first solidification point.
corr is the calculated compression correction value, k corresponds to the number of collected curing points; f corresponds to the maximum number of SMs allowed to go wrong in the system.
Sixthly, after receiving PCF frames sent by the CM, the SM1, the SM2, the FM and the SC carry out local clock adjustment.
Seventhly, in the ending stage of each cluster period, namely the ending stage of the last integration period of each cluster period, comparing the time information (namely the calculated global clock reference of the distributed network) of the PCF frame sent by the CM with a local clock of the GM, if the time difference value between the two is less than or equal to a preset threshold value, considering that the GM is in a normal state, namely the integration state, and then sending a GM normal mark frame to all equipment by the GM; and if the difference value is larger than the preset threshold value, the GM is considered to be in an abnormal state, and then the GM sends a GM abnormal mark frame to all the devices.
Eighth step: if the FM receives the GM normal mark frame, the FM processes the data transmission delay measured value which is collected in a cluster period and sent to the FM by the GM, calculates a clock frequency ratio, then adjusts the local clock frequency of the FM, the FM enters a distribution synchronization state, the FM sends the adjusted frequency value to the SM1, the SM2, the CM and the SC, the FM 1, the SM2, the CM and the SC adjust the local clock frequency according to the received frequency adjustment information, and the frequency of the non-adjustable frequency is not adjusted. And if the FM receives the GM abnormal mark frame, the FM also enters a distribution synchronization state, the FM directly issues the clock frequency of the FM to the lower-layer equipment, and the lower-layer equipment adjusts according to the FM clock.
The ninth step: and at the beginning of the next trunking period, each device adjusts the synchronization strategy according to the state information sent by the GM. If the GM normal mark frame is received, jumping to the second step, and re-selecting the roles of the devices; and if the GM abnormal mark frame is received, jumping to the fifth step.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.
Claims (10)
1. A high-reliability clock synchronization method facing a time sensitive network is characterized by comprising the following steps:
step one, selecting a certain device in a network as a GM according to an optimal master clock algorithm;
step two, starting at each integration period, each device transmits local clock information to the GM, and the GM selects roles of each device, including FM, SM, CM and SC;
step three, after confirming the roles of all the devices, the GM writes role distribution information into a PCF frame; after receiving the role distribution information frame, each device determines the roles, completes state conversion of each role and sends a role confirmation information frame to the GM;
after receiving the role confirmation information frame returned by each device, the GM starts time synchronization with the SM and frequency synchronization with the FM;
step five, the SM generates PCF frames after completing time synchronization with the GM, the PCF frames are sent to the CM, the CM calculates a compression correction value according to the received PCF frames, the CM generates new PCF frames after adjusting a local clock according to the compression correction value, and the reference is sent to the GM, the SM, the FM and the SC;
step six, after receiving PCF frames sent by the CM, the SM, the FM and the SC carry out local clock adjustment;
seventhly, in the finishing stage of each cluster cycle, namely the finishing stage of the last integrated cycle of each cluster cycle, the GM judges whether the GM is normal or not and feeds information back to each device;
step eight, if the FM receives the GM normal information frame, the FM processes the data transmission delay measured value which is collected in one cluster period and sent to the FM by the GM, calculates clock frequency offset, then adjusts the local clock frequency of the FM, and simultaneously sends the frequency value after the FM adjustment to the SM, the CM and the SC, and the SM, the CM and the SC adjust the local clock frequency according to the received frequency adjustment information; if the FM receives the GM abnormal information frame, the FM directly issues the clock frequency of the FM to lower-layer equipment, and the lower-layer equipment adjusts according to the FM clock;
step nine, starting at the next cluster cycle, each device adjusts a synchronization strategy according to the state information sent by the GM; if the GM normal information frame is received, jumping to the second step, and re-selecting the roles of the devices; and if the GM abnormal information frame is received, jumping to the fifth step.
2. The time-sensitive network-oriented highly reliable clock synchronization method of claim 1, wherein the local clock information comprises a local clock time value, local crystal frequency information, local crystal aging degree, hop count of a device to the GM.
3. The time-sensitive-network-oriented highly reliable clock synchronization method according to claim 1, wherein when selecting the SM in step two, the devices are clustered according to a device clustering rule, and an SM cluster is selected according to a principle that devices in a cluster are the most, and the devices in a cluster are the SMs.
4. The method for highly reliable clock synchronization facing to time-sensitive network as claimed in claim 3, wherein the device clustering rule is to perform clock distribution detection according to the clock information of the devices, and group devices with close clocks into a cluster.
5. The method for highly reliable clock synchronization facing to time-sensitive network as claimed in claim 3, wherein the device clustering rule is to determine a network hierarchy first, and take the hop count of the device from the GM as a ranking criterion, and the hop count from the GM represents the number of levels of the device; and each level of network independently performs clock distribution detection according to the clock information of the equipment, and the equipment with similar clocks form a cluster.
6. The method for highly reliable clock synchronization for time-sensitive networks according to claim 1, wherein the device with the most stable frequency is selected as the FM in the second step according to the local crystal frequency information and the local crystal aging information.
7. The method for highly reliable clock synchronization for time-sensitive networks according to claim 1, wherein the setting of the CM in the second step ensures that the total number of hops for each SM to reach the CM is minimum.
8. The highly reliable clock synchronization method for time-sensitive networks according to claim 1, wherein in step seven, the rule that the GM determines whether it is normal or not is: the GM compares the global clock reference of the distributed network calculated by the CM with the local clock of the GM, if the time difference between the global clock reference and the local clock of the GM is less than or equal to a preset threshold value, the GM is considered to be in a normal state, and then the GM sends a GM normal mark frame to all devices; and if the difference value is larger than a preset threshold value, the GM is considered to be in an abnormal state, and then the GM sends a GM abnormal mark frame to all the devices.
9. The time-sensitive network-oriented high-reliability clock synchronization method according to claim 1, wherein the GM, the FM, the SM, the CM, and the SC device comprise a relay device and a terminal device.
10. A highly reliable clock synchronization system for time-sensitive networks, comprising:
a real-time clock module: the precise timing is realized according to the crystal oscillator frequency and the counter, and the clock adjusting function is included, so that the correction can be carried out according to the calculated clock offset and frequency deviation;
an input module: the real-time clock module is responsible for receiving data and recording a clock value of the real-time clock module when receiving the data, namely receiving time;
an output module: the real-time clock module is responsible for sending data, and a timestamp is added to the data according to the clock value of the real-time clock module when the data is sent, namely the sending time;
a state management module: the system comprises a state processing module, a state transfer module, a state management module and a role distribution module, wherein the state processing module and the state transfer module are used for managing different states of equipment, and the state management module can be used for switching different state sets according to received role distribution information and switching different states according to received information;
a configuration management module: providing a uniform interface for parameters used by all modules, and uniformly configuring all parameters of the system, including the maximum transmission delay of a network, a cluster period, an integration period and the size of an observation window;
a calculation module: providing calculation functions for a system, wherein the calculation functions comprise comparison calculation of clock references calculated by a GM clock and a CM, calculation of data transmission delay, clock offset calculation of master-slave synchronization, calculation of clock frequency deviation, a solidification function and a compression function, and the calculation module starts different calculation functions according to different state sets of the state management module;
a data storage module: mainly providing a data storage function, including providing the data storage function for the FM, and storing the data frame transmission delay from the GM recorded by the FM in the cluster period to the FM; storing past and current state information for the state management module; providing temporary or permanent data storage for the computing module; and configuring the parameter information configured by the management module.
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