CN111585574B - Pipeline analog-to-digital converter - Google Patents
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Abstract
The invention belongs to the technical field of integrated circuits, and particularly relates to a pipeline analog-to-digital converter capable of correcting capacitor mismatch and interstage gain errors. According to the method, PN codes are injected into a digital domain or an analog domain of the pipeline stage sub-analog-digital converter, the average value of output code words of the (i + 1) th pipeline stage sub-analog-digital converter is counted under the condition that the output of the ith pipeline stage sub-analog-digital converter is a specific code word b, the capacitance mismatch error and the actual interstage gain of the ith pipeline stage are estimated according to the relation between the average value and the preceding stage capacitance mismatch error and the actual interstage gain, and the code words output by the (i + 1) th pipeline stage sub-analog-digital converter can be corrected. The invention can also flexibly adjust the working interval time and the accumulated time of correction according to the actual situation, thereby realizing the flexible adjustment of correction precision, tracking speed and power consumption.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a pipeline analog-to-digital converter capable of correcting capacitor mismatch and interstage gain errors.
Background
The analog-to-digital converter is a circuit module for converting an analog signal into a digital signal, and is widely applied to various fields, such as audio and video acquisition, high-definition image processing, communication systems and the like, and different fields also put different requirements on the performance of the analog-to-digital converter, so that analog-to-digital converters with different structures are developed. The Pipeline analog-to-digital converter (Pipeline ADC) has important characteristics of both speed and precision in the application, and thus is widely applied. The pipeline analog-to-digital converter is formed by cascading a series of high-speed low-precision sub analog-to-digital converters (sub-ADCs) with similar structures. For each stage, after an input signal is sampled and quantized by a sub-analog-to-digital converter, a residual error is amplified to be used as the input of the next stage, and the stages are connected and work simultaneously, so that the conversion between high-speed and high-precision analog signals and digital signals is realized.
Fig. 1 shows a basic architecture of a typical two-stage pipeline analog-to-digital converter, each stage of which includes a sub analog-to-digital converter 101 (201), a sub digital-to-analog converter 102, a subtractor 103, and an amplifier 104. Capacitive digital-to-analog converters (DACs) are commonly used sub-digital-to-analog converters, and there are two structures in the prior art: a binary code type and a thermometer code type. Due to process problems, the actual capacitance value of the capacitance digital-to-analog converter has deviation, so that the output of the sub-digital-to-analog converter has errors. At the same time, the amplification of the amplifier will also vary. Ultimately, capacitive mismatch and inter-stage gain errors lead to Spurious Free Dynamic Range (SFDR) and signal-to-noise ratio (SNDR) degradation.
Disclosure of Invention
The invention mainly aims to provide a pipeline analog-to-digital converter capable of correcting capacitance mismatch and interstage gain errors aiming at the capacitance mismatch and interstage gain errors of a binary code type digital-to-analog converter, so that the normal work of the pipeline analog-to-digital converter can not be interrupted, and the performance index of the pipeline analog-to-digital converter is improved.
In order to achieve the above object, the present invention provides a pipeline analog-to-digital converter, which includes a PN code injection module, a digital correction circuit, and a plurality of pipeline stages, wherein the plurality of pipeline stages are coupled in a cascade manner, each pipeline stage includes a sub analog-to-digital converter, a sub digital-to-analog converter, and an interstage gain amplifier, and the sub digital-to-analog converter is of a binary code type;
PN code generators and digital correction circuits are arranged between all adjacent two stages of pipeline stages; the preceding stage pipeline stage is the ith stage of the pipeline analog-to-digital converter, the adjacent following stage pipeline stage is the (i + 1) th stage of the pipeline analog-to-digital converter, wherein i is more than or equal to 1 and less than or equal to N-1, N is the number of pipeline stages, and N is more than or equal to 2; the number of the PN code generator and the number of the digital correction circuits are both N-1;
a PN code generator between the i-th level pipeline stage and the i + 1-th level pipeline stage, for randomly generating a PN code and inputting the PN code into the i-th level pipeline stage, wherein the value of the PN code is +1 or-1; PN codes are input into the ith stage pipeline stage in a digital signal mode or an analog signal mode;
if the PN code is input into the ith level pipeline stage in a digital signal mode, converting an analog input signal of the ith level into a code word by the sub analog-to-digital converter of the ith level pipeline stage, taking a digital signal obtained by adding the PN code output by the PN code generator and the code word output by the sub analog-to-digital converter of the ith level pipeline stage as an input signal of the ith level pipeline stage sub analog-to-digital converter, amplifying a difference value of an analog input signal of the ith level pipeline stage and an analog output signal of the ith level pipeline stage sub analog-to-digital converter by the interstage gain amplifier of the ith level pipeline stage, and outputting the difference value to the (i + 1) th level pipeline stage as an analog input signal of the (i + 1) th level pipeline stage;
if the PN code is input into the ith level pipeline stage in an analog signal mode, the sub analog-to-digital converter of the ith level pipeline stage converts the analog input signal of the ith level into a code word and outputs the code word to the sub analog-to-digital converter of the ith level pipeline stage; subtracting an analog output signal of an ith pipeline level sub digital-to-analog converter from an analog input signal of the ith pipeline level to obtain a quantization residual error of the ith pipeline level, inputting an analog signal obtained by digital-to-analog conversion of a PN code output by a PN code generator into the ith pipeline level to increase or reduce the quantization residual error, wherein the increased or reduced amplitude is the amplitude of the lowest effective bit of a code word of the ith pipeline level sub analog-to-digital converter converted by the ith pipeline level analog-to-digital converter, and the quantization residual error with the increased or reduced amplitude is amplified by an interstage gain amplifier and then output to the (i + 1) th pipeline level as an analog input signal of the (i + 1) th pipeline level;
the digital correction circuit receives a PN code output by the PN code generator, a code word output by the ith-level pipeline-level sub analog-to-digital converter and a code word output by the (i + 1) -level pipeline-level sub analog-to-digital converter, and counts the average value of the code words output by the (i + 1) -level pipeline-level sub analog-to-digital converter under the condition that the code word output by the ith-level pipeline-level sub analog-to-digital converter is b, wherein b represents the code word output by the ith-level pipeline-level sub analog-to-digital converter, k is the binary digit number of the code words output by the ith-level pipeline-level sub analog-to-digital converter, and b is more than or equal to 0 and less than or equal to 2 k -1，And estimating the capacitance mismatch error and the actual interstage gain of the ith-stage pipeline stage according to the average value of the output code words of the (i + 1) -stage pipeline-stage sub analog-to-digital converter and the relation between the capacitance mismatch error and the actual interstage gain error of the ith-stage pipeline stage, and correcting the capacitance mismatch and the interstage gain error of the output code words of the (i + 1) -stage pipeline-stage sub analog-to-digital converter by adopting the obtained capacitance mismatch error and the actual interstage gain.
Further, the digital correction circuit includes an error detection circuit and an error correction circuit, the error detection circuit is configured to count a mean value of output code words of the i +1 th-stage pipeline sub analog-to-digital converter under two conditions that a PN code is equal to +1 and the PN code is equal to-1 under the condition that an output of the i-th-stage pipeline sub analog-to-digital converter is a specific code word b, and estimate a capacitance mismatch error and an actual inter-stage gain of the i-th-stage pipeline according to the mean value of the output code words of the i + 1-stage pipeline sub analog-to-digital converter and a relationship between the capacitance mismatch error and the actual inter-stage gain error of the i + 1-stage pipeline sub analog-to-digital converter; the error correction circuit is used for correcting the capacitance mismatch and the interstage gain error of the output code word of the (i + 1) th-stage pipeline stage sub analog-to-digital converter by adopting the capacitance mismatch error and the actual interstage gain obtained by the error detection circuit.
Further, the error detection circuit comprises a first memory, a second memory, a third memory, an error calculation module and a control module; in a first accumulation time period, under the control of a control module, a PN code equal to +1 is used as a chip selection signal of a first memory, and a code word output by an i + 1-level pipeline level sub analog-to-digital converter when the PN code is equal to +1 is stored in a row of a row address which is the code word output by the i-level pipeline level sub analog-to-digital converter in the first memory; using the PN code equal to-1 as a chip selection signal of a second memory, and storing a code word output by the (i + 1) th level pipeline level sub analog-to-digital converter when the PN code is equal to-1 in a row which uses the code word output by the ith level pipeline level sub analog-to-digital converter as a row address in the second memory; the error calculation module reads the first memory and the second memory at a first interval time under the control of the control module, calculates the average value of each row of code words of the first memory and the average value of each row of code words of the second memory, estimates the capacitance mismatch error and the actual interstage gain by using two average values of the first memory and the second memory with the same row address, and stores the capacitance mismatch error and the actual interstage gain in the third memory for the error correction circuit to call; the control module is used for controlling the time length of the first storage and the second storage for storing the code words of the (i + 1) th-level pipeline-level sub analog-to-digital converter according to the first accumulation time, and controlling the error calculation module to calculate and update the frequency of the capacitance mismatch error and the actual interstage gain according to the first interval time.
Furthermore, the error correction circuit comprises a subtracter, an adder, a multiplier, an amplifier and a divider, wherein the amplification factor of the amplifier is equal to the ideal interstage gain of the ith stage of pipeline stage interstage gain amplifier, and the divisor of the divider is equal to the calculated actual interstage gain of the ith stage of pipeline stage interstage gain amplifier; the code words output by the i-level pipeline sub analog-to-digital converter are sent to the subtracted end of the subtracter, the calculated capacitor mismatch error is sent to the subtracted end of the subtracter, and the output of the subtracter is sent to the adder; the PN code and the actual interstage gain of the ith stage pipeline stage obtained by calculation are sent to a multiplier for multiplication, and the output of the multiplier is sent to an adder to be added with the output of a subtracter; the output of the adder passes through an amplifier and a divider and then outputs the corrected code word.
Advantageous effects
The pipeline analog-to-digital converter corrects the capacitance mismatch and the interstage gain error through PN code injection, and can flexibly adjust the corrected working interval time and accumulated time according to the actual condition, so that the flexible adjustment of the correction precision, the tracking speed and the power consumption is realized.
Drawings
Fig. 1 is a basic structure diagram of a Pipeline analog-to-digital converter (Pipeline ADC) in the prior art;
FIG. 2 is a block diagram of a 4-bit capacitive digital-to-analog converter (DAC) of the prior art;
FIG. 3 is a basic schematic diagram of the digital domain PN code injection pipeline analog-to-digital converter of the present invention;
FIG. 4 is a basic schematic diagram of a pipeline analog-to-digital converter of the present invention for injecting PN codes in the analog domain;
FIG. 5 is a block diagram of an embodiment of an error detection circuit of the digital correction circuit of the present invention;
FIG. 6 shows an embodiment of an error correction circuit of the digital correction circuit of the present invention.
Detailed Description
The following describes in detail embodiments of the present invention with reference to the drawings.
The pipeline analog-to-digital converter comprises N pipeline stages, wherein N is more than or equal to 2, each pipeline stage comprises a sub analog-to-digital converter, a sub digital-to-analog converter, a subtracter and an interstage gain amplifier, and the sub digital-to-analog converter is of a binary code type.
Fig. 1 shows two stages of pipeline analog-to-digital converter 100 before and after. Referring to FIG. 1, the preceding stage pipeline stages are labeled with i, and the subsequent stage pipeline stages are labeled with i +1, where i is greater than or equal to 1 and less than or equal to N-1.V in The voltage value of an ith-level pipeline-level input Analog signal 1 (Analog input) is represented, the output of the ith-level pipeline-level sub Analog-to-digital converter 101 is a codeword b, and is also the input of the ith-level pipeline-level sub digital-to-Analog converter 102, wherein b is greater than or equal to 0 and less than or equal to 2 k -1, k is the binary number of the i-th level pipeline codeword; DAC i (b) The sub-DAC 102 representing the pipeline stage of the i-th stage converts the input codeword b into an analog output 2, V in -DAC i (b) Is the quantized residual 3,V output by the i-th pipeline subtractor 103 res The voltage value of the analog signal 4 output by the ith stage of the pipeline stage, G is the gain amplifier G between the ith stage of the pipeline stage i Ideal inter-stage gain values.
For the ith stage pipeline stage of the pipeline analog-to-digital converter, under the ideal condition that no error exists, the signal input and output formula of the ith stage pipeline stage is as follows:
V res ＝(V in -DAC i (b))*G (1)
the codeword output by the i +1 th-stage pipelined analog-to-digital converter 201 is c = ADC i+1 (V res ) (2)
Wherein, ADC i+1 (V res ) The analog quantity voltage value V of the i +1 th level pipeline stage sub analog-to-digital converter is represented res Converted into a digital quantity.
When there is capacitance mismatch and interstage gain error, use V res 'represents the voltage value of the analog signal 4 output by the i-th stage pipeline stage, and G' represents the inter-stage gain amplifier G i The actual inter-stage gain values of sub-adc 101 and 201 are represented by b 'and c', then the signal input and output of the i-th stage pipeline is expressed as,
the codeword of the output of the i +1 th-stage pipeline-level sub analog-to-digital converter 201 is,
wherein, ε (b ') is the capacitance mismatch value when the sub-ADC 102 inputs the codeword b'. Thus, the ADC is estimated i+1 (e (b ')) G ' and G ', errors due to capacitance mismatch and inter-stage gain can be corrected.
Fig. 3 and 4 illustrate two embodiments 200 and 300, respectively, of a pipeline analog-to-digital converter of the present invention capable of capacitance mismatch and inter-stage gain error correction. The basic principle of the pipeline analog-to-digital converter for performing capacitance mismatch and interstage gain error correction by injecting PN codes in the digital domain and the analog domain is explained below. Referring to fig. 3 and 4, the preceding stage pipeline stages are identified by i, and the subsequent stage pipeline stages are identified by i +1, where i is greater than or equal to 1 and less than or equal to N-1. The digital domain PN code injection refers to the fact that PN codes are input into the ith level pipeline stage in a digital signal mode, and the analog domain PN code injection refers to the fact that PN codes are input into the ith level pipeline stage in an analog signal mode. The PN code takes a value of +1 or-1 in a digital domain, and the amplitude increased or decreased in an analog domain is the amplitude of the lowest effective bit of the ith-level pipeline-level sub analog-to-digital converter after being converted by the ith-level analog-to-digital converter. Drawing (A)In fig. 3, the digital output 7 of the PN code generator 105, i.e., the PN code, is added to the code word b output from the sub adc 101 by the adder 110, and the input code word of the sub adc 102 becomes b "= b' + PN. In fig. 4, PN code generator 105 converts digital output 7, i.e., the PN code, to the analog domain via DAC 106, and adds it to output 2 of sub-DAC 102 via adder 111, i.e., the DAC i (b') add, the output 9 of the adder 111 is DAC i (b')+DAC i (PN*(1+ε c ) Therein, epsilon c Errors introduced by PN code injection, e when digital domain is injected c =0, analog domain epsilon c Typically in the order of 1%, neglecting ε c The Spurious Free Dynamic Range (SFDR) requirement of a part of high-speed high-precision analog-to-digital converters can be met.
Whether the PN code is injected in the analog domain or the digital domain, when the codeword output by the i-th pipeline sub analog-to-digital converter 101 is b', the voltage value of the analog signal 4 output by the i-th pipeline is equal to
The codeword c "output by the i +1 th-stage pipeline-level sub analog-to-digital converter 201 is
On the premise that the codeword output by the i-th pipeline-level sub analog-to-digital converter 101 is b ', the average values of the codewords c' output by the subsequent pipeline-level sub analog-to-digital converter 201 when the PN code is +1 and-1 are respectively
E(ADC i+1 (V res "| b',PN＝+1 ))＝E(ADC i+1 ((V in -DAC i (b'))*G'-(1+ε c )*G'-ε(b')*G'))
＝E(ADC i+1 ((V in -DAC i (b'))*G'))-E((1+ε c )*G')-E(ADC i+1 (ε(b')*G'))
＝-(1+ε c )*G'-E(ADC i+1 (ε(b')))*G'
(7)
E(ADC i+1 (V res "| b',PN＝-1 ))＝E(ADC i+1 ((V in -DAC i (b'))*G'+(1+ε c )*G'-ε(b')*G'))
＝E(ADC i+1 ((V in -DAC i (b'))*G'))+E((1+ε c )*G')-E(ADC i+1 (ε(b')*G'))
＝(1+ε c )*G'-E(ADC i+1 (ε(b')))*G'
(8)
Wherein, E ((1 + ε) c )*G')＝(1+ε c ) G'; residual mean value of 0,E (ADC) i+1 ((V in -DAC i (b'))*G'))＝0；
Furthermore, therefore, addition or subtraction of both averages can be done, and addition or subtraction of both averages can be done
E(ADC i+1 (V res "| b',PN＝+1 ))+E(ADC i+1 (V res "| b',PN＝-1 ))＝-2*E(ADC i+1 (ε(b')))*G' (9)
E(ADC i+1 (V res "| b',PN＝+1 ))-E(ADC i+1 (V res "| b',PN＝-1 ))＝2*(1+ε c )*G'≈-2*G' (10)
It can be seen that, on the premise that the codeword output by the i-th pipeline sub analog-to-digital converter 101 is b', the average value of the codewords c ″ output by the i + 1-th pipeline sub analog-to-digital converter 201 when the PN code is +1 and-1 is respectively counted, and then E (ADC) can be estimated i+1 (ε (b '))) G' and then E (ADC) i+1 (ε (b '))) G' as ADC i+1 (epsilon (b ')). G ' is estimated, and the codeword c ' can be corrected for errors caused by capacitance mismatch and inter-stage gain according to the formula (6) to obtain the codeword c in an ideal state.
G'≈(E(ADC i+1 (V res "| b',PN＝-1 ))-E(ADC i+1 (V res "| b',PN＝+1 )))/2 (11)
E(ADC i+1 (ε(b')))*G'＝-(E(ADC i+1 (V res "| b',PN＝+1 ))+E(ADC i+1 (V res "| b',PN＝-1 )))/2 (12)
For convenience of circuit design, it is possible to define
ε'(b')＝-E(ADC i+1 (ε(b' )) )*G'＝(E(ADC i+1 (V res "| b',PN＝+1 ))+E(ADC i+1 (V res "| b',PN＝-1 )))/2 (13)
Based on the principle, the pipeline analog-to-digital converter provided by the invention comprises a digital correction circuit, wherein the digital correction circuit receives a PN code, a code word output by an ith-level pipeline sub-analog-to-digital converter and a code word output by an (i + 1) -level pipeline sub-analog-to-digital converter, and counts the average value of the code words output by the (i + 1) -level pipeline sub-analog-to-digital converter when the PN code is +1 and the PN code is-1 under the condition that the output of the ith-level pipeline sub-analog-to-digital converter is a specific code word b, wherein b represents the code word of the ith-level pipeline, k is the bit number of the code word of the ith-level pipeline, b is more than or equal to 0 and less than or equal to 2 and b is more than or equal to 0 and less than or equal to 2 k And 1, calculating a capacitance mismatch error and an actual interstage gain of the ith stage pipeline stage by using the average value, and correcting output code words of the i +1 stage pipeline stage sub analog-to-digital converter.
One embodiment of the digital correction circuit includes an error detection circuit and an error correction circuit. The error detection circuit is used for counting the average value of the code words output by the i +1 th-stage pipeline stage sub analog-to-digital converter when the PN code is +1 and the PN code is-1 under the condition that the output of the i-th-stage pipeline stage sub analog-to-digital converter is a specific code word b, and calculating the capacitance mismatch error and the actual interstage gain of the i-th-stage pipeline stage by adopting the average value; the error detection circuit is used for correcting the output code words of the i +1 level pipeline level sub analog-to-digital converter.
FIG. 5 shows an embodiment of an error detection circuit in the digital correction circuit of the present invention. As shown, the error detection circuit 107 includes a first memory 1071, a second memory 1072, a third memory 1073, an error calculation module 1074, and a control module 1075; in a first accumulation time period t1, under the control of the control module 1075, the PN code equal to +1 is used as a chip select signal of the first memory 1071, and the codeword output by the i +1 th-stage pipeline stage sub analog-to-digital converter when the PN code is equal to +1 is stored in the row of the first memory 1071 where the codeword output by the i-th-stage pipeline stage sub analog-to-digital converter is used as a row address; using the PN code equal to-1 as a chip select signal of the second memory 1072, and storing the codeword output by the i +1 th-stage pipeline stage sub analog-to-digital converter when the PN code is equal to-1 in the row of the second memory 1072 using the codeword output by the i-th-stage pipeline stage sub analog-to-digital converter as a row address; the error calculation module 1074 reads the first memory 1071 and the second memory 1072 at a first interval time under the control of the control module 1075, calculates the mean value of each row of code words of the first memory 1071 and the mean value of each row of code words of the second memory 1072, calculates a capacitance mismatch error e '(b') and an actual inter-stage gain G 'using two mean values of the first memory 1071 and the second memory 1072 having the same row address, and stores the capacitance mismatch error e' (b ') and the actual inter-stage gain G' in the third memory 1073 for the error correction circuit to call; the control module 1075 is configured to control a time duration for which the first memory 1071 and the second memory 1072 store the i +1 th stage pipeline stage sub analog-to-digital converter codeword according to the first accumulated time, control the error calculation module 1074 to calculate a frequency of the capacitance mismatch error and the actual inter-stage gain according to the first interval time t2, and update the frequency of the capacitance mismatch error and the actual inter-stage gain in the third memory 1073.
According to the inverse operation of the formula (6), that is, the formula (14), the codeword c ″ is corrected by the capacitance mismatch and the error caused by the inter-stage gain, so that the codeword c in an ideal state can be obtained.
c＝(c"+ADC i+1 (ε(b'))*G'+PN*G')G/G'＝(c"-ε'(b')+PN*G')G/G' (14)
FIG. 6 shows an embodiment of an error correction circuit of the digital correction circuit of the present invention. The error correction circuit 108 includes a subtractor 1081, an adder 1082, an amplifier 1083, a divider 1084, and a multiplier 1085. The amplification of amplifier 1083 is the desired interstage gain G and the divisor of divider 1084 is the actual interstage gain G'. The code word c ″ and the capacitance mismatch error ∈ ' (b ') output by the i + 1-stage pipeline sub analog-to-digital converter 201 are respectively sent to the subtracted end and the subtracted end of the subtractor 1081, the subtracted result is sent to an adder 1082, the pn code and the actual inter-stage gain G ' are sent to a multiplier 1085 for multiplication and then sent to the adder 1082, and the two are added by the adder 1082 and then output by an amplifier 1083 and a divider 1084 to obtain the corrected code word c.
Taking a two-stage pipeline analog-to-digital converter as an example, the first stage is 6 bits, the second stage is 8 bits, and the inter-stage gain is 16, so that the input codeword range b' of the sub-digital-to-analog converter of the 1 st stage pipeline stage is 0-63, and the quantization codeword range of the sub-analog-to-digital converter of the 2 nd stage pipeline stage is 0-255.
Inputting code words 0-63 as row addresses by using a sub-digital-to-analog converter DAC1 of a 1-level pipeline level, recording quantized code words of the sub-analog-to-digital converter of the 2-level pipeline level into a first memory when PN =1, recording quantized code words of the sub-analog-to-digital converter of the 2-level pipeline level into a second memory when PN = -1, and recording accumulated time t1=256 × 64 × 16=262144 sub-analog-to-digital converter (ADC) clock cycles; calculating the average value of each line of the first memory and the average value of each line of the second memory, calculating the capacitance mismatch error and the actual interstage gain according to the obtained average values, wherein the actual interstage gain is irrelevant to the input code word b ' of the neutron digital-to-analog converter in the 1 st stage pipeline stage, so that the actual interstage gain obtained from one line of the average values can be used as the actual interstage gain for correction, and the actual interstage gain value for correction can be obtained by averaging the actual interstage gain G ' (b ') obtained by calculating the average value of each line
The latter is adopted in the present embodiment; errors caused by capacitance mismatch are related to input code words b 'of the sub digital-to-analog converters in the 1 st-stage pipeline structure, therefore, epsilon' (b ') is the capacitance mismatch error when the sub digital-to-analog converters in the current pipeline stage input the code words b', different capacitance mismatch errors epsilon '(b') are adopted for correction according to different input code words b ', 64 epsilon' (b ') values and 1G' value are stored, and a control module in the error detection circuit outputs G 'and the corresponding epsilon' (b ') to the error calibration circuit for calibration according to the b' value. Tracking the capacitance mismatch and inter-stage gain error of the digital-to-analog converter over time by setting the interval time t2 to 60s by the control module in the error detection circuit, i.e. the time interval for updating the values of 64 epsilon ' (b ') and 1G ' in the memory each time is calculated to be 60sTo change in time.
Through the correction, the spurious-free dynamic range SFDR of the pipeline analog-to-digital converter can reach over 75 dB.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalents, improvements, etc. made within the principle of the present invention are included in the scope of the present invention.
Claims (4)
1. A pipeline analog-to-digital converter comprises a PN code injection module, a digital correction circuit and a plurality of pipeline stages, wherein the pipeline stages are coupled in a cascading mode, each pipeline stage comprises a sub analog-to-digital converter, a sub digital-to-analog converter and an interstage gain amplifier, and the sub digital-to-analog converter is of a binary code type;
a PN code generator and a digital correction circuit are arranged between all adjacent front and back two stages of pipeline; the preceding stage pipeline stage is the ith stage of the pipeline analog-to-digital converter, the adjacent following stage pipeline stage is the (i + 1) th stage of the pipeline analog-to-digital converter, wherein i is more than or equal to 1 and less than or equal to N-1, N is the number of pipeline stages, and N is more than or equal to 2; the number of the PN code generator and the number of the digital correction circuits are both N-1;
a PN code generator between the i-th level pipeline stage and the i + 1-th level pipeline stage, for randomly generating a PN code and inputting the PN code into the i-th level pipeline stage, wherein the value of the PN code is +1 or-1; PN codes are input into the ith stage pipeline stage in a digital signal mode or an analog signal mode;
if the PN code is input into the ith level pipeline stage in a digital signal mode, converting an analog input signal of the ith level into a code word by the sub analog-to-digital converter of the ith level pipeline stage, taking a digital signal obtained by adding the PN code output by the PN code generator and the code word output by the sub analog-to-digital converter of the ith level pipeline stage as an input signal of the ith level pipeline stage sub analog-to-digital converter, amplifying a difference value of an analog input signal of the ith level pipeline stage and an analog output signal of the ith level pipeline stage sub analog-to-digital converter by the interstage gain amplifier of the ith level pipeline stage, and outputting the difference value to the (i + 1) th level pipeline stage as an analog input signal of the (i + 1) th level pipeline stage;
if the PN code is input into the ith level pipeline stage in an analog signal mode, the sub analog-to-digital converter of the ith level pipeline stage converts the analog input signal of the ith level into a code word and outputs the code word to the sub analog-to-digital converter of the ith level pipeline stage; subtracting an analog output signal of an ith pipeline level sub digital-to-analog converter from an analog input signal of the ith pipeline level to obtain a quantization residual error of the ith pipeline level, inputting an analog signal obtained by digital-to-analog conversion of a PN code output by a PN code generator into the ith pipeline level to increase or reduce the quantization residual error, wherein the increased or reduced amplitude is the amplitude of the lowest effective bit of a code word of the ith pipeline level sub analog-to-digital converter converted by the ith pipeline level analog-to-digital converter, and the quantization residual error with the increased or reduced amplitude is amplified by an interstage gain amplifier and then output to the (i + 1) th pipeline level as an analog input signal of the (i + 1) th pipeline level;
the digital correction circuit receives a PN code output by the PN code generator, a code word output by the ith-level pipeline-level sub analog-to-digital converter and a code word output by the (i + 1) -level pipeline-level sub analog-to-digital converter, and counts the average value of the code words output by the (i + 1) -level pipeline-level sub analog-to-digital converter under the condition that the code word output by the ith-level pipeline-level sub analog-to-digital converter is b, wherein b represents the code word output by the ith-level pipeline-level sub analog-to-digital converter, k is the binary digit number of the code words output by the ith-level pipeline-level sub analog-to-digital converter, and b is more than or equal to 0 and less than or equal to 2 k And-1, estimating a capacitance mismatch error and an actual interstage gain of the ith stage pipeline stage according to the average value of the codeword output by the (i + 1) th stage pipeline stage sub analog-to-digital converter and the relation between the capacitance mismatch error and the actual interstage gain error of the ith stage pipeline stage, and correcting the capacitance mismatch and the interstage gain error of the codeword output by the (i + 1) th stage pipeline stage sub analog-to-digital converter by using the obtained capacitance mismatch error and the actual interstage gain.
2. An analog to digital converter as claimed in claim 1, in which the digital correction circuit comprises an error detection circuit and an error correction circuit,
the error detection circuit is used for counting the mean value of the output code words of the i +1 th-stage pipeline sub analog-to-digital converter under the condition that the output of the i-th-stage pipeline sub analog-to-digital converter is the code word b, and estimating the capacitance mismatch error and the actual interstage gain of the i-th-stage pipeline according to the relation between the mean value of the output code words of the i + 1-stage pipeline sub analog-to-digital converter and the capacitance mismatch error and the actual interstage gain error of the i-th-stage pipeline;
the error correction circuit is used for correcting the capacitance mismatch and the interstage gain error of the output code word of the (i + 1) th-level pipeline-level sub analog-to-digital converter by adopting the capacitance mismatch error and the actual interstage gain obtained by the error detection circuit.
3. An analog-to-digital converter as claimed in claim 2,
the error detection circuit comprises a first memory, a second memory, a third memory, an error calculation module and a control module; in a first accumulation time period, under the control of a control module, a PN code equal to +1 is used as a chip selection signal of a first memory, and a code word output by an i + 1-level pipeline level sub analog-to-digital converter when the PN code is equal to +1 is stored in a row of a row address which is the code word output by the i-level pipeline level sub analog-to-digital converter in the first memory; using the PN code equal to-1 as a chip selection signal of a second memory, and storing a code word output by the (i + 1) th level pipeline level sub analog-to-digital converter when the PN code is equal to-1 in a row which uses the code word output by the ith level pipeline level sub analog-to-digital converter as a row address in the second memory; the error calculation module reads the first memory and the second memory at a first interval time under the control of the control module, calculates the mean value of each row of code words of the first memory and the mean value of each row of code words of the second memory, estimates the capacitance mismatch error and the actual interstage gain by using two mean values of the first memory and the second memory with the same row address, and stores the capacitance mismatch error and the actual interstage gain in a third memory for the error correction circuit to call; the control module is used for controlling the time length of the first storage and the second storage for storing the code words of the (i + 1) th-level pipeline-level sub analog-to-digital converter according to the first accumulation time, and controlling the error calculation module to calculate and update the frequency of the capacitance mismatch error and the actual interstage gain according to the first interval time.
4. An analog-to-digital converter as claimed in claim 2,
the error correction circuit comprises a subtracter, an adder, a multiplier, an amplifier and a divider, wherein the amplification factor of the amplifier is equal to the ideal interstage gain of the ith-stage pipelined interstage gain amplifier, and the divisor of the divider is equal to the calculated actual interstage gain of the ith-stage pipelined interstage gain amplifier; the code words output by the i-level pipeline-level sub-analog-to-digital converter are sent to a subtracted end of the subtracter, the calculated capacitor mismatch error is sent to the subtracted end of the subtracter, and the output of the subtracter is sent to the adder; the PN code and the actual interstage gain of the ith stage pipeline stage obtained by calculation are sent to a multiplier for multiplication, and the output of the multiplier is sent to an adder to be added with the output of a subtracter; the output of the adder passes through an amplifier and a divider and then outputs a corrected code word.
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