CN111555989B

CN111555989B - Configurable switching chip port

Info

Publication number: CN111555989B
Application number: CN202010333311.5A
Authority: CN
Inventors: 刘多一
Original assignee: Beijing Wuxin Technology Co ltd
Current assignee: Beijing Wuxin Technology Co ltd
Priority date: 2020-04-24
Filing date: 2020-04-24
Publication date: 2022-01-11
Anticipated expiration: 2040-04-24
Also published as: CN111555989A

Abstract

The invention discloses a configurable exchange chip port, which comprises a processor, a multimedia control MAC device, a shared data bus, a first shared coding layer PCS device and a shared serial-parallel and digital-to-analog conversion layer PHY device, wherein the processor is connected with the first shared data bus; the processor is used for controlling the shared data bus to disconnect the connected 1G MAC devices according to the configuration information of the first port, and controlling the first shared PCS device and the shared PHY device to adapt to the 10G MAC device; and according to the second port configuration information, controlling the common data bus to disconnect the hooked 10G MAC devices, and controlling the first common PCS device and the common PHY device to be matched with the 1G MAC device. The technical scheme of the embodiment of the invention solves the problem that the port configuration mode of the existing exchange chip is single; the ports of the switching chip are integrated on the same switching chip in various different working modes, so that the development cost is saved for manufacturers of the switching chip.

Description

Configurable switching chip port

Technical Field

The embodiment of the invention relates to the field of digital communication, in particular to a configurable exchange chip port.

Background

Two ports with preset bandwidth are commonly used by the switching chip in the process of completing information exchange, namely a 1G port and a 10G port. The existing switch chip has a single configuration mode for the two ports, for example, a 128G switch chip, the port allocation mode of the chip is fixed, the common allocation modes are divided into two types, the first type divides the ports of the switch chip into 48 ports of 1G and 8 ports of 10G; the second divides the switch chip ports into 28 1G ports and 12 10G ports.

However, it is difficult for the existing switch chip to simultaneously satisfy the requirements of users in different scenarios, for example, in a scenario where a large bandwidth port is applied more, the requirements of users for 10G ports are very large, only 8 10G ports in the switch chip may not be enough to be used, but 48 1G ports appear redundant, and if 28 1G ports and 12 10G ports are changed to satisfy the above scenario, the situation that a large bandwidth is not required, but a large number of 1G ports are required cannot be satisfied. In order to meet different user requirements, manufacturers need to supply two switching chips, which is time-consuming and labor-consuming.

Disclosure of Invention

The embodiment of the invention provides a configurable switch chip port, solves the problem that the existing switch chip port is single in configuration mode, and saves development cost for manufacturers of switch chips.

The embodiment of the invention provides a configurable exchange chip port, which comprises: the device comprises a processor, a multimedia control MAC device, a shared data bus, a first shared coding layer PCS device, a shared serial-parallel and digital-to-analog conversion layer PHY device, a first serial-parallel and digital-to-analog conversion layer PHY device and a second serial-parallel and digital-to-analog conversion layer PHY device, wherein the shared data bus, the first shared coding layer PCS device and the shared serial-parallel and digital-to-analog conversion layer PHY device are respectively connected with the processor; the MAC device comprises a 1G MAC device and a 10G MAC device;

a first number of 1G MAC devices and a second number of 10GMAC devices are respectively hung on the shared data bus, and every third number of 1G MAC devices and every fourth number of 10GMAC devices on the shared data bus are commonly connected with the same first shared PCS device; each of the shared PHY devices is connected to a fifth number of the first shared PCS devices;

the processor is used for controlling the common data bus to disconnect the hooked 1G MAC devices according to first port configuration information and controlling the first common PCS device and the common PHY device to adapt to a 10G MAC device; and controlling the common data bus to disconnect the hooked 10G MAC devices according to second port configuration information, and controlling the first common PCS device and the common PHY device to adapt to the 1G MAC device.

Optionally, the switch chip port in the embodiment of the present invention further includes: a hybrid data bus, a second shared PCS device, and a first dedicated PCS device;

the mixed data bus is hung with the first number of 1G MAC devices, wherein a third number of 1G MAC devices on the mixed bus and a fourth number of 10G MAC devices hung on the shared data bus are connected with the same second shared PCS device together, and every third number of 1G MAC devices in the remaining number of 1G MAC devices on the mixed bus are connected with the same first special PCS device together;

the processor is further configured to control the mixed data bus to disconnect the hooked connection of each 1G MAC device connected to a second shared PCS device according to the first port configuration information, and control the second shared PCS device to adapt to a 10G MAC device; and controlling the mixed data bus to disconnect the hooked 10G MAC device connected with the second shared PCS device and to control the second shared PCS device to adapt to the 1G MAC device according to the configuration information of the second port.

Optionally, the first shared PCS device and the second shared PCS device in the embodiment of the present invention are connected to the shared PHY device in common.

Optionally, in this embodiment of the present invention, the first shared PCS device or the second shared PCS device includes: a 10G processing module and a 1G processing module, wherein clock signals in the 10G processing module and the 1G processing module are supplied by the processor; the clock frequency of the shared PHY device is adjustable;

optionally, the processor is specifically configured to disconnect clock supply of the 1G processing module in the first shared PCS device and the second shared PCS device according to first port configuration information, and adjust a clock frequency of the shared PHY device to match with the 10G MAC device; and the number of the first and second groups,

according to the second port configuration information, clock supply of 10G processing modules in the first shared PCS device and the second shared PCS device is disconnected, and the clock frequency of the shared PHY device is adjusted to be matched with that of the 1G MAC device.

Optionally, the switch chip port in the embodiment of the present invention further includes: a first register to store the first port configuration information and the second port configuration information;

optionally, the switch chip port in the embodiment of the present invention is specifically configured to obtain the first port configuration information from the first register according to a first port configuration instruction, or obtain the second port configuration information from the first register according to a second port configuration instruction.

Optionally, the switch chip port in the embodiment of the present invention further includes: at least one dedicated data bus, and a first dedicated PHY device;

optionally, each dedicated data bus is respectively hooked with the first number of 1G MAC devices or the second number of 10G MAC devices, and each third number of 1G MAC devices or each fourth number of 10G MAC devices on each dedicated data bus are commonly connected to the same first dedicated PCS device; each of the first dedicated PHY devices is connected to a fifth number of the first dedicated PCS devices.

Optionally, the first common PCS device, the second common PCS device, and the first dedicated PCS device support an electrical port mode.

Optionally, the switch chip port in the embodiment of the present invention further includes: a second dedicated PCS device and a second dedicated PHY device respectively connected to the processor; the second dedicated PCS device supports an optical port mode;

optionally, in the embodiment of the present invention, each 1G MAC device hooked to at least one target dedicated data bus is connected to each second dedicated PCS device, and each second dedicated PHY device is connected to a fifth number of second dedicated PCS devices;

optionally, the processor in the embodiment of the present invention is further configured to control, according to the communication mode configuration information, each 1G MAC device hooked to the at least one target dedicated data bus to selectively connect to the first dedicated PCS device and the first dedicated PHY device, so as to support an electrical port mode; or, controlling each 1G MAC device hooked on the at least one target special data bus to selectively connect with a second special PCS device and a second special PHY device so as to support an optical interface mode.

Optionally, the first common PCS device, the second common PCS device, and the first dedicated PCS device in the embodiment of the present invention further support an optical port mode;

optionally, the processor in this embodiment of the present invention is further configured to adjust the first common PCS device, the second common PCS device, and the first dedicated PCS device to be in an optical port mode according to the communication mode configuration information.

Optionally, the switch chip port in the embodiment of the present invention further includes: a second register for storing the communication mode configuration information;

optionally, the switch chip port is further configured to obtain the communication mode configuration information from the second register according to a communication mode configuration instruction.

The embodiment of the invention sets the forwarding ports of the switching chip in two working modes by utilizing the mixed data bus, the common data bus and the special data bus, and realizes the switching of the working modes of the forwarding ports of the switching chip by controlling the connection of the mounting devices on each data bus and the working modes of each device. The embodiment of the invention provides the switch chip port suitable for different bandwidth port requirements, solves the problem that the configuration mode of the existing switch chip port is single, and improves the experience of users; the ports of the switching chip are integrated on the same switching chip in various different working modes, so that the development cost is saved for manufacturers of the switching chip.

Drawings

FIG. 1a is a schematic structural diagram of a configurable switch chip port according to a first embodiment of the present invention;

FIG. 1b is a diagram illustrating a connection of a processor according to a first embodiment of the present invention;

FIG. 2a is a schematic structural diagram of a configurable switch chip port according to a first embodiment of the present invention;

FIG. 2b is a diagram illustrating a connection of a processor according to a first embodiment of the present invention;

FIG. 3a is a schematic structural diagram of a configurable switch chip port according to a first embodiment of the present invention;

FIG. 3b is a diagram illustrating a connection of a processor according to a first embodiment of the present invention;

FIG. 4a is a schematic structural diagram of a configurable switch chip port according to a second embodiment of the present invention;

fig. 4b is a schematic diagram of a connection manner of the processor in the second embodiment of the invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Example one

Aiming at the problem that the port configuration mode of the existing switching chip is single, the inventor provides a configurable switching chip port, so that a user can select the port configuration modes in different modes according to the self requirement, the embodiment takes 152G ports and 128G ports as examples, and two port working modes are designed, wherein the first mode provides 152G ports which are divided into 32 1G ports and 12 10G ports so as to meet the condition that the requirement of the 10G ports is large; the second mode provides 128G ports, which are divided into 48 1G ports and 8 10G ports to satisfy the condition that the demand of the 1G ports is large.

Fig. 1a is a schematic structural diagram of a configurable switch chip port in a first embodiment of the present invention, as shown in fig. 1a, the switch chip port includes: a processor 101, a multimedia control MAC device 102, a shared data bus 103, a first shared coding layer PCS device 104 and a shared serial-parallel and digital-to-analog conversion layer PHY device 105; the MAC devices include a 1G MAC device 106 and a 10G MAC device 107; wherein, the shared data bus 103 is connected with the processor 101;

to more clearly illustrate the connection manner of the processors in this embodiment, fig. 1b is a schematic diagram of the connection manner of the processor corresponding to fig. 1a, and as shown in fig. 1b, the processor 101 is connected to the first common coding layer PCS device 104 and the common serial-parallel digital-to-analog conversion layer PHY device 105, in addition to the common data bus 103.

In this embodiment, the processor 101 is configured to process a received network data packet, and implement configuration of a forwarding Port of a switch chip according to a data type of the network data packet in combination with a MAC (Media Access Control) device, a PCS (Physical coding sublayer) device, and a PHY (Port Physical layer) device. The shared data bus 103 is called a shared data bus 103, because 1G MAC devices and 10G MAC devices are respectively attached to the shared data bus 103 according to different operating modes of the ports of the switching chip.

A first number of 1G MAC devices and a second number of 10G MAC devices are respectively hung on the shared data bus 103, and every third number of 1G MAC devices and every fourth number of 10G MAC devices on the shared data bus 103 are commonly connected with the same first shared PCS device 104; each of the shared PHY devices 105 is connected to a fifth number of the first shared PCS devices 104;

in a specific embodiment, as shown in fig. 1a, the shared data bus 103 is hooked with 12 1G MAC devices and 4 10G MAC devices, wherein each 4 1G MAC device and each 10G MAC device are connected to a same first shared PCS device 104, and each shared PHY device 105 is connected to 3 first shared PCS devices 104.

The operation type of the first shared PCS device 104 depends on the MAC device mounted on the shared data bus 103, the first shared PCS device 104 is set to QSGMII type when the shared data bus 103 mounts 12 1G MAC devices (when the first shared PCS device 104 is set to QSGMII type, the first shared PCS device 104 supports 1G MAC device operation), and the first shared PCS device 104 is set to KR type when the shared data bus 103 mounts 4 10GMAC devices (when the first shared PCS device 104 is set to KR type, the first shared PCS device 104 supports 10G MAC device operation).

The processor 101 is configured to control the shared data bus 103 to disconnect the hooked 1G MAC devices according to first port configuration information, and control the first shared PCS device 104 and the shared PHY device 105 to adapt to a 10G MAC device; and according to the second port configuration information, controlling the common data bus 103 to disconnect each hooked 10G MAC device, and controlling the first common PCS device 104 and the common PHY device 105 to adapt to 1G MAC devices.

In this embodiment, the inventor designs a forwarding port in two operating modes, the first operating mode is that the shared data bus 103 disconnects each hooked 1G MAC device, and controls the operating mode of the first shared PCS device 104 and the shared PHY device 105 to adjust to the operating mode of the connected 10G MAC device; the second operation mode is that the common data bus 103 disconnects each of the attached 10G MAC devices, and controls the operation mode of the first common PCS device 104 and the common PHY device 105 to be adjusted to the operation mode in which the 1G MAC device is connected. Specifically, the first port configuration information is to control the switching chip to switch the forwarding port working mode from the second working mode to the first working mode in a scene that a large bandwidth port is applied more; the second port configuration information is used for controlling the switching chip to switch the forwarding port working mode from the first working mode to the second working mode under the scene that the small-bandwidth port is applied more.

In a specific embodiment, as known from the design manners of the two forwarding ports, in the first operation mode, 4 10G MAC devices are connected to the common data bus 103, and the operation modes of the first common PCS device 104 and the common PHY device 105 are adjusted to the operation mode of the 10G MAC device; in the second operation mode, 12 1G MAC devices are connected to the common data bus 103, and the operation modes of the first common PCS device 104 and the common PHY device 105 are adjusted to the operation mode in which the 1G MAC devices are connected.

In this embodiment, as shown in fig. 2a, the switch chip port further includes: a mixed data bus 108, a second shared PCS device 109, and a first dedicated PCS device 110; the mixed data bus 108 may be configured to simultaneously attach a certain number of 1G MAC devices and 10G MAC devices according to different operating modes selected by the ports of the switch chip, and is referred to as a mixed data bus 108.

Fig. 2b is a schematic diagram of a connection mode of the processor corresponding to fig. 2a, and as shown in fig. 2b, the processor 101 is connected to the shared data bus 103, the first shared encoding layer PCS device 104, and the shared serial-parallel conversion layer PHY device 105, and is also connected to the shared data bus 108, the second shared PCS device 109, and the first dedicated PCS device 110, respectively.

The mixed data bus 108 is connected with the first number of 1G MAC devices in a hanging mode, wherein a third number of 1G MAC devices on the mixed data bus 108 and a fourth number of 10G MAC devices on the shared data bus 103 are connected with the same second shared PCS device 109 in a common mode, and in the remaining number of 1G MAC devices on the mixed data bus, every third number of 1G MAC devices are connected with the same first special PCS device 110 in a common mode;

in a specific embodiment, as shown in fig. 2a, 12 1G MAC devices are hooked on the mixed data bus 108, wherein 4 1G MAC devices on the mixed bus 108 and 1 10G MAC device hooked on the common data bus 103 are commonly connected to the same second common PCS device 109, and every 4 1G MAC devices in the remaining 8 1G MAC devices on the mixed bus are commonly connected to the same first dedicated PCS device 110.

The processor 101 is further configured to control, according to the first port configuration information, the mixed data bus 108 to disconnect the attached 1G MAC devices connected to the second shared PCS device 109, and control the second shared PCS device 109 to adapt to 10G MAC devices (that is, the second shared PCS device 109 is connected to 1 10G MAC device attached to the shared data bus), so that a forwarding port of the switch chip is in a first operating mode; and according to the second port configuration information, controlling the mixed data bus 108 to disconnect the 10G MAC device connected to the second shared PCS device 109, and controlling the second shared PCS device 109 to adapt to the 1G MAC device (that is, the second shared PCS device 109 is connected to 4 1G MAC devices on the mixed data bus 108), so that the forwarding port of the switch chip is in the second operation mode. As shown in fig. 2, the first shared PCS device 104 and the second shared PCS device 109 are commonly connected to the shared PHY device 105.

In a specific embodiment, as can be seen from the design manners of the two forwarding ports, the mixed data bus 108 is connected with 8 1G MAC devices in the first operation mode, and the second shared PCS device 109 is connected with 1 10G MAC device hooked to the shared data bus; in the second mode of operation, 12 1G MAC devices are connected to the mixed data bus 108, and the second shared PCS device 109 is connected to 4 1G MAC devices on the mixed data bus 108.

The first port configuration information is to control the operating mode of the second shared PCS device 109 and the shared PHY device 105 to adjust to the operating mode of the 10G MAC device under the scenario that the large bandwidth port is applied more; the second port configuration information is to control the operating mode of the second shared PCS device 109 and the shared PHY device 105 to be adjusted to the operating mode of the connected 1G MAC device in a scenario where a large number of small-bandwidth ports are used.

The first shared PCS device 104 or the second shared PCS device 109 includes: a 10G processing module and a 1G processing module, in which clock signals are supplied from the processor 101; the clock frequency of the common PHY device 105 is adjustable;

the processor 101 is specifically configured to, according to the first port configuration information, disconnect the clock supply of the 1G processing module in the first shared PCS device 104 and the second shared PCS device 109, and adjust the clock frequency of the shared PHY device 105 to match the 10G MAC device; and the number of the first and second groups,

according to the second port configuration information, the clock supply of the 10G processing module in the first shared PCS device 104 and the second shared PCS device 109 is disconnected, and the clock frequency of the shared PHY device 105 is adjusted to match the 1G MAC device.

In a specific embodiment, the 10G processing module in the first shared PCS device 104 or the second shared PCS device 109 is set to KR type, and the 1G processing module is set to QSGMII type. The first port configuration information is that under the scene that a large bandwidth port is applied more, the switching chip forwarding port working mode is controlled to be switched from the second working mode to the first working mode, and under the configuration information, the processor 101 cuts off the clock supply of the 1G processing module, so that the 1G processing module is in an idle state, and the power consumption is saved; the second port configuration information is to control the switching chip to switch the forwarding port working mode from the first working mode to the second working mode in a scene that the small bandwidth port is applied more, and under the configuration information, the processor 101 cuts off the clock supply of the 10G processing module, so that the processor is in an idle state. In addition, in the two application scenarios, the shared PHY device 105 provides a corresponding clock frequency for the setting mode of the first shared PCS device 104 or the second shared PCS device 109, so as to implement switching of the working mode of the forwarding port of the switch chip.

The switch chip port in this embodiment further includes: a first register to store the first port configuration information and the second port configuration information;

the switch chip port is specifically configured to obtain the first port configuration information from the first register according to a first port configuration instruction, or obtain the second port configuration information from the first register according to a second port configuration instruction.

In this embodiment, when the switch chip needs to meet a scenario that a large bandwidth port is applied more, a user triggers a first port configuration instruction on the switch chip, and the switch chip port acquires first port configuration information from a first register according to the first port configuration instruction; when the switching chip needs to meet the situation that the application of the small-bandwidth port is more, a user triggers a second port configuration instruction on the switching chip, and the port of the switching chip acquires second port configuration information from the first register according to the second port configuration instruction.

As shown in fig. 3a, the switch chip port in this embodiment further includes: at least one dedicated data bus 111, and a first dedicated PHY device 112; the configuration mode of the dedicated data bus 111 in the two working modes of the switch chip port is not changed, and the dedicated data bus is only hooked with 1G MAC devices or only hooked with 10G MAC devices in all working modes, so that the dedicated data bus 111 is called a dedicated data bus.

As shown in fig. 3a, the first number of 1G MAC devices or the second number of 10G MAC devices are respectively attached to each dedicated data bus 111, and every third number of 1G MAC devices or every fourth number of 10G MAC devices on each dedicated data bus 111 are commonly connected to the same first dedicated PCS device 110; each of the first dedicated PHY devices 112 is connected to a fifth number of the first dedicated PCS devices 110.

Specifically, as shown in fig. 3a, two dedicated data buses in the switch chip port are 111 and 113, each dedicated data bus is respectively connected with 12 1G MAC devices or 4 10G MAC devices, each 4 1G MAC devices or each 10G MAC device on the dedicated data bus are commonly connected with the same first dedicated PCS device 110, and each first dedicated PHY device 112 is connected with 4 first dedicated PCS devices 110.

Fig. 3b is a schematic diagram of the connection of the processor corresponding to fig. 3a, and as shown in fig. 3b, the processor 101 is connected to a dedicated data bus 111, a dedicated data bus 113, a first dedicated PCS device 110 and a first dedicated PHY device 112, respectively.

The first dedicated PCS device 110 includes a 10G processing module and a 1G processing module, and when 12 1G MAC devices are hooked on the dedicated data bus, the processor 101 disconnects the clock supply of the 10G processing module in the first dedicated PCS device 110, and sets the 1G processing module to be of QSGMII type; when 4 10G MAC devices are hooked on the dedicated data bus, the processor 101 disconnects the clock supply of the 1G processing module in the first dedicated PCS device 110, and sets the 10G processing module to KR type.

Specifically, in this embodiment, the operation modes of the first common PCS device 104, the second common PCS device 109, and the first dedicated PCS device 110 are configured to be SGMII or QSGMII modes, so that the forwarding port of the switch chip supports the electrical interface mode.

In this embodiment, the switch chip port includes four dedicated data buses, wherein the first dedicated data bus and the second dedicated data bus are respectively hooked with 12 1G MAC devices, and the third dedicated data bus and the fourth dedicated data bus are respectively hooked with 4 10G MAC devices.

When the switching chip is in a scene with more applications of the large-bandwidth port, that is, when the forwarding port of the switching chip is in the first working mode, the first dedicated data bus and the second dedicated data bus are respectively connected with 12 1G MAC devices, the mixed data bus 108 is connected with 8 1G MAC devices, the shared data bus 103 is connected with 4 10G MAC devices, and the third dedicated data bus and the fourth dedicated data bus are respectively connected with 4 10G MAC devices. Therefore, when the forwarding port of the switch chip is in the first operation mode, the ports of the switch chip in the embodiment of the present invention provide 152G ports, which are divided into 32 ports of 1G and 12 ports of 10G.

When the switching chip is in a scene with more applications of a small-bandwidth port, namely when a forwarding port of the switching chip is in a second working mode, a first special data bus and a second special data bus are respectively connected with 12 1G MAC devices in a hanging mode, and every 4 1G MAC devices are connected with 1 first special PCS device 110; 12 1G MAC devices are connected to the mixed data bus 108, wherein 4 1G MAC devices are connected to the second shared PCS device 109, and every 4 1G MAC devices in the remaining 8 1G MAC devices are connected to 1 first dedicated PCS device 110; 12 1G MAC devices are connected to the common data bus 103, and every 4 1G MAC devices are connected to the first common PCS device 104; the third dedicated data bus and the fourth dedicated data bus are respectively connected with 4 10G MAC devices, and each 10G MAC device is connected with 1 first dedicated PCS device 110. Therefore, when the forwarding port of the switch chip is in the second operation mode, the port of the switch chip in the embodiment of the present invention provides 128G ports, which are divided into 48 ports of 1G and 8 ports of 10G. The number of the first dedicated PCS device 110, the second shared PCS device 109, and the first shared PCS device 104 provided in this embodiment is 20 in total.

The embodiment of the invention sets the forwarding ports of the processor in two working modes by utilizing the mixed data bus, the shared data bus and the special data bus, and realizes the switching of the working modes of the forwarding ports of the processor by controlling the connection of the mounting devices on the data buses and the working modes of the devices. The embodiment of the invention provides the switch chip port suitable for different bandwidth port requirements, solves the problem that the configuration mode of the existing switch chip port is single, and improves the experience of users; two different working modes of the port of the switching chip are integrated on the same processor, so that the development cost is saved for manufacturers of the processor.

Example two

Fig. 4a is a schematic structural diagram of a configurable switch chip port in a second embodiment of the present invention, which is detailed based on the above-described embodiment.

At present, two main communication modes in digital communication are optical interface communication and electrical interface communication, the number of optical interfaces and the number of electrical interfaces provided by the existing switching chip are fixed, and switching is not flexible enough for different photoelectric application scenes, for example, the number of optical interfaces used by a user can only use the number of optical interfaces less than or equal to the number of optical interfaces specified by the switching chip, so that the experience of the user is reduced. Therefore, the embodiment of the invention provides a configurable switch chip port suitable for multiple scenarios on the basis of the above embodiment.

In this embodiment, taking the 128G port in the first embodiment as an example, as shown in fig. 4a, the switch chip port further includes: a second dedicated PCS device 114 and a second dedicated PHY device 115; the second dedicated PCS device 114 supports an optical port mode; FIG. 4b is a schematic diagram of the connection of the processor corresponding to FIG. 4a, as shown in FIG. 4b, the processor 101 is connected to a second dedicated PCS device 114 and a second dedicated PHY device 115, respectively;

each 1G MAC device hooked to at least one target dedicated data bus is connected to each of the second dedicated PCS devices 114, and each of the second dedicated PHY devices 115 is connected to a fifth number of the second dedicated PCS devices 114;

the processor 101 is further configured to control, according to the communication mode configuration information, each 1G MAC device hooked to the at least one target dedicated data bus to selectively connect the first dedicated PCS device 110 and the first dedicated PHY device 112, so as to support an electrical port mode; or, each 1G MAC device hooked to the at least one target dedicated data bus is controlled to selectively connect to the second dedicated PCS device 114 and the second dedicated PHY device 115 to support the optical interface mode.

In this embodiment, when a user needs to set a port of a switch chip to an electrical port mode, as shown in fig. 4a, in this embodiment, the first dedicated data bus 116 and the second dedicated data bus 117 in the first embodiment are used as target dedicated data buses, each 1G MAC device hooked on the target dedicated data buses can be selectively connected to the first dedicated PCS device 110 and the first dedicated PHY device 112, and the operating mode of the first dedicated PCS device 110 is configured to be an SGMII mode or a QSGMII mode, so that a forwarding port of the switch chip supports the electrical port mode;

as shown in fig. 4b, in addition to being connected to the second dedicated PCS device 114 and the second dedicated PHY device 115, the processor 101 is also connected to a first dedicated data bus 116, a second dedicated data bus 117, a first dedicated PCS device 110 and a first dedicated PHY device 112, respectively.

In a specific embodiment, when the forwarding port of the switch chip supports the optical port mode, as shown in fig. 4a, 20 second dedicated PCS devices 114 are introduced in the embodiment, and the operation mode of each second dedicated PCS device 114 is configured to be the 1000BASE _ X mode, so that the forwarding port of the switch chip supports the optical port mode. The first dedicated data bus 116 and the second dedicated data bus 117 are used as target dedicated data buses, and the first dedicated data bus 116 and the second dedicated data bus 117 are respectively provided with 12 1G MAC devices, so that the target dedicated data bus is provided with 24 1G MAC devices in total. 20 1G MAC devices hooked on the target dedicated data bus are connected to 20 second dedicated PCS devices 114, respectively, and 4 second dedicated PCS devices 114 are connected to each second dedicated PHY device 115; the remaining 4 1G MAC devices attached to the destination private data bus are connected to each first private PCS device 110, and each first private PHY device 112 is connected to 4 first private PCS devices 110. At this time, the switch chip port in this embodiment may provide 20 forwarding ports supporting the optical port mode.

In another specific embodiment, the first common PCS device 104, the second common PCS device 109, and the first dedicated PCS device 110 also support an optical port mode;

the processor is further configured to adjust the first shared PCS device, the second shared PCS device, and the first dedicated PCS device to an optical port mode according to the communication mode configuration information.

Specifically, when the number of optical ports of the switch chip required by the user is greater than 20, the processor obtains configuration information for switching the electrical port mode of at least one forwarding port to the optical port mode, and then configures the operating modes of the first dedicated PCS device 110, the second common PCS device 109, and the first common PCS device 104 in the first embodiment to the 1000BASE _ X mode, so that the forwarding port of the switch chip supports the optical port mode.

In this embodiment, when the number of optical ports of the switch chip required by the user is greater than 20, the first dedicated PCS device 110, the second shared PCS device 109, and the first shared PCS device 104 (20 PCS devices in total) provided in the first embodiment may be respectively connected to 20 1G MACs, and the operation modes of the 20 PCS devices are all configured to be 1000BASE _ X mode, so that 20 extra forwarding ports supporting the optical port mode may be provided.

Therefore, by connecting 20 1G MAC devices hooked on the target dedicated data bus to 20 second dedicated PCS devices 114 respectively, and by combining a mode that the operation modes of the first dedicated PCS device 110, the second shared PCS device 109, and the first shared PCS device 104 are all configured to be 1000BASE _ X mode, 40 forwarding ports supporting the optical interface mode are provided in total in this embodiment, and the actual requirement of most users on the number of optical interfaces can be met.

The switch chip port in the embodiment of the invention further comprises: a second register for storing the communication mode configuration information;

the switch chip port is further configured to acquire the communication mode configuration information from the second register according to a communication mode configuration instruction.

In this embodiment, when the switch chip needs to set the communication mode of the forwarding port, the user triggers a communication mode configuration instruction on the switch chip, and the switch chip port acquires the communication mode configuration information from the second register according to the communication mode configuration instruction, thereby implementing the configuration of the optical port number or the electrical port number of the switch chip.

In the embodiment of the invention, the exchange chip can provide optical ports with fixed quantity by introducing the second special PCS device and the second special PHY device, and when all forwarding ports of the exchange chip need to support the electric port mode, the embodiment realizes that the forwarding ports of the exchange chip are switched from the optical port mode to the electric port mode by changing the PCS device connected with the special data bus; when the number of optical ports required by the user is greater than the fixed number of optical ports available in this embodiment, the number of optical ports of the switch chip is made to be consistent with the number of optical ports required by the user by setting the operating modes of the first dedicated PCS device, the second common PCS device, and the first common PCS device. The embodiment of the invention provides a switching chip port suitable for different communication modes, and solves the problem that the number of optical ports and the number of electric ports provided by the conventional switching chip are not changeable, so that the forwarding port of the switching chip is more flexible to switch under different photoelectric application scenes, and the experience of a user is improved.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A configurable switch chip port, comprising: the device comprises a processor, a multimedia control MAC device, a shared data bus, a first shared coding layer PCS device, a shared serial-parallel and digital-to-analog conversion layer PHY device, a first serial-parallel and digital-to-analog conversion layer PHY device and a second serial-parallel and digital-to-analog conversion layer PHY device, wherein the shared data bus, the first shared coding layer PCS device and the shared serial-parallel and digital-to-analog conversion layer PHY device are respectively connected with the processor; the MAC device comprises a 1G MAC device and a 10G MAC device;

the shared data bus is respectively connected with a first number of 1G MAC devices and a second number of 10G MAC devices in a hanging mode, and every third number of 1G MAC devices and every fourth number of 10G MAC devices on the shared data bus are connected with the same first shared PCS device; each of the shared PHY devices is connected to a fifth number of the first shared PCS devices;

2. The switch chip port of claim 1, further comprising: a hybrid data bus, a second shared PCS device, and a first dedicated PCS device;

the mixed data bus is hung with the first number of 1G MAC devices, wherein a third number of 1G MAC devices on the mixed data bus and a fourth number of 10G MAC devices hung on the shared data bus are connected with the same second shared PCS device together, and every third number of 1G MAC devices in the remaining number of 1G MAC devices on the mixed data bus are connected with the same first special PCS device together;

3. The switch chip port of claim 2, wherein the first and second common PCS devices are commonly connected to the common PHY device.

4. The switch chip port of claim 3, wherein the first or second common PCS device comprises: a 10G processing module and a 1G processing module, wherein clock signals in the 10G processing module and the 1G processing module are supplied by the processor; the clock frequency of the shared PHY device is adjustable;

the processor is specifically configured to disconnect clock supply of the 1G processing module in the first shared PCS device and the second shared PCS device according to first port configuration information, and adjust a clock frequency of the shared PHY device to match with the 10G MAC device; and the number of the first and second groups,

5. The switch chip port of claim 1, further comprising: a first register to store the first port configuration information and the second port configuration information;

6. The switch chip port of claim 1, further comprising: at least one dedicated data bus, and a first dedicated PHY device;

each special data bus is respectively connected with the 1G MAC devices of the first quantity or the 10G MAC devices of the second quantity in a hanging mode, and each 1G MAC device of the third quantity or each 10G MAC device of the fourth quantity on each special data bus is connected with the same first special PCS device; each of the first dedicated PHY devices is connected to a fifth number of the first dedicated PCS devices.

7. The switch chip port of claim 4, in which the first common PCS device, the second common PCS device, and the first dedicated PCS device support an electrical port mode.

8. The switch chip port of claim 7, further comprising: a second dedicated PCS device and a second dedicated PHY device respectively connected to the processor; the second dedicated PCS device supports an optical port mode;

each 1G MAC device hooked on at least one target special data bus is respectively connected with each second special PCS device, and each second special PHY device is connected with a fifth number of second special PCS devices;

the processor is further configured to control, according to the communication mode configuration information, each 1G MAC device hooked on the at least one target dedicated data bus to selectively connect to the first dedicated PCS device and the first dedicated PHY device to support an electrical port mode; or, controlling each 1G MAC device hooked on the at least one target special data bus to selectively connect with a second special PCS device and a second special PHY device so as to support an optical interface mode.

9. The switch chip port of claim 8, wherein the first common PCS device, the second common PCS device and the first dedicated PCS device further support an optical port mode;

10. The switch chip port of claim 8 or 9, further comprising: a second register for storing the communication mode configuration information;