CN111552205A - Managing pulse width modulated trip signals from multiple sources - Google Patents

Abstract

Embodiments of the present application relate to managing pulse width modulated trip signals from multiple sources. An integrated communication subsystem ICSS (200) includes a pulse width modulator (244) that drives a power stage, such as an electric motor. The pulse width modulator (244) is configured to cut off the power stage when the pulse width modulator (244) receives a trip signal from a logic circuit (421) of the ICSS (200). The logic circuit (421) can be easily reprogrammed to send a trip signal only when a particular error condition is detected. Further, the ICSS (200) contains one or more filters that can adjust the sensitivity of the logic circuit (421) to error signals, enabling the ICSS (200) to distinguish between real errors that require shutdown and negligible glitches during operation of the ICSS (200).

Description

Managing pulse width modulated trip signals from multiple sources

Cross reference to related applications

The present application claims priority from U.S. provisional application No. 62/677,878 filed on 30.5.2018 and U.S. provisional application No. 62/786,477 filed on 30.12.2018, both of which are incorporated herein by reference in their entirety.

Technical Field

The present invention relates generally to an industrial communication subsystem (ICSS) that may be formed as part of an integrated circuit, such as a Digital Signal Processor (DSP), a system on a chip (SoC) or an Application Specific Integrated Circuit (ASIC), or a Field Programmable Gate Array (FPGA). More particularly, the present invention relates to systems and methods for managing pulse width modulated trip signals from multiple sources in an industrial control subsystem.

Background

Industrial motor control applications such as robotics, servo drives and computer numerical control require the following capabilities: the powered device is turned off when an error condition occurs that can cause damage to the motor, machine, and/or person.

Disclosure of Invention

At least one example of the invention includes a control system comprising: a power stage; a pulse width modulator coupled to the power stage, the pulse width modulator configured to cut off the power stage when the pulse width modulator receives a trip signal; a processor coupled to the pulse width modulator; a logic circuit coupled to the pulse width modulator and the processor, the logic circuit comprising: a first interface comprising a plurality of inputs, wherein the plurality of inputs comprises: a first input configured to receive a first trip event indication signal originating at the pulse width modulator; a second input configurable to receive a second trip event indication signal originating at an electronic device releasably coupled to the second input at a connection port; and a third input configured to receive a third trip event indication signal from the processor; and a second interface comprising: a first selection input configured to receive a first selection; and a second selection input configured to receive a second selection, wherein the logic circuit is configured to send the trip signal to the pulse width modulator when the logic circuit receives at least one of the three trip event indication signals.

At least one other example of the present disclosure includes a logic circuit coupled to a pulse width modulator, the logic circuit configured to receive a plurality of inputs, the plurality of inputs comprising: a first input corresponding to a first signal originating at the pulse width modulator; a second input corresponding to a second signal originating at the electronic device; and a third input corresponding to a third signal originating at the one or more processors; wherein the logic circuit is configured to controllably select which of the plurality of inputs to output to the pulse width modulator as a trip signal to cause the pulse width modulator to shut down a power stage driven by the pulse width modulator.

At least one additional example of the present invention is a method for managing a trip signal for a pulse width modulator, the method comprising: driving the power stage using a pulse width modulator; receiving a first input at a logic circuit, the first input corresponding to a first trip event indication signal originating at the pulse width modulator; receiving a second input at the logic circuit, the second input corresponding to a second trip event indication signal originating at an electronic device releasably coupled to the logic circuit at a port; receiving a third input corresponding to a third trip event indication signal from the processor; selecting, by the logic circuit, which input to output to the pulse width modulator as a trip signal to cause the pulse width modulator to turn off a power stage driven by the pulse width modulator, wherein selecting comprises selecting from a plurality of inputs including the first input, the second input, and the third input; and outputting the selected input from the logic circuit.

Drawings

For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

FIG. 1 is a block diagram of a system having an architecture according to an example of the present invention;

FIG. 2A illustrates a first communication and control portion of a system, such as the system illustrated in FIG. 1, according to an example of the present invention;

FIG. 2B illustrates a shared components portion of a system, such as the system illustrated in FIG. 1, according to an example of the present invention;

FIG. 2C illustrates a second communication and control portion of a system, such as the system illustrated in FIG. 1, according to an example of the present invention;

FIG. 3 illustrates aspects of pulse width generation according to examples of this disclosure;

FIG. 4A illustrates a logic configuration of a pulse width modulation monitor and controller according to an example of the present disclosure;

FIG. 4B illustrates a trip signal logic unit interacting with the logic configuration illustrated in FIG. 4A, according to an example of the present invention;

FIG. 5 illustrates aspects of a system such as the systems illustrated in FIG. 1 and FIGS. 2A-2C, according to an example of the disclosure;

FIG. 6 is a state diagram showing the relationship of possible states of one or more components of a system, such as the systems illustrated in FIGS. 1 and 2A-2C, according to an example of the present invention; and is

Fig. 7 is a block diagram of a state machine 700 according to an example of the invention.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments disclosed herein. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the disclosed examples.

When introducing elements of various examples of the present invention, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. The examples discussed below are intended to be illustrative in nature and should not be construed to mean that the examples described herein must be preferred in nature.

The examples described in this disclosure are neither mutually exclusive nor collectively exhaustive. References to "one example" or "an example" are not intended to be interpreted as excluding the existence of additional examples that also incorporate the recited features.

As used herein, the term "media" refers to one or more non-transitory physical media that together store content described as being stored thereon. The term "media" does not include signals, electrical or otherwise. Examples may include non-volatile secondary storage, read-only memory (ROM), and/or Random Access Memory (RAM).

As used herein, the terms "application" and "function" refer to one or more computing modules, programs, processes, workloads, threads, and/or a set of computing instructions executed by a computing system. Example implementations of applications and functions include software modules, software objects, software instances, and/or other types of executable code.

One or more examples of the present invention are implemented on a 'system on a chip' (SoC). In at least one example, the SoC includes a plurality of hardware components. In at least one example, the SoC includes a microcontroller, a microprocessor, a Digital Signal Processor (DSP) core, and/or a multi-processor SoC having more than one processor core. In at least one example, the SoC includes a memory block that includes a selection of ROM, RAM, electrically erasable programmable read-only memory, and flash memory. In at least one example, the SoC includes a timing source that includes an oscillator and a phase-locked loop. In at least one example, the SoC includes peripheral devices including a counter-timer, a real-time timer, and a power-on-reset generator. In at least one example, the SoC includes an analog interface including an analog-to-digital converter and a digital-to-analog converter. In at least one example, the SoC includes a voltage regulator and a power management circuit.

In at least one example, the SoC includes both the hardware described above, as well as software and/or firmware that controls the microcontroller, microprocessor or DSP core, peripherals, and interfaces.

Within the present invention, pulse width modulation refers to the process of modifying the width of a pulse in a pulse train in proportion to a small control signal; the larger the control voltage, the wider the resulting pulse becomes. By using a sine wave of a desired frequency as a control voltage for a pulse width modulation control circuit (also referred to as a 'pulse width modulator'), it is possible to generate a high power waveform whose average voltage varies in a sine wave in a manner suitable for driving an Alternating Current (AC) motor. AC motors are used in many industrial applications such as robotics, servo drives and computer numerical control. Pulse width modulation is a way of describing a digital (binary/discrete) signal formed by a modulation technique that involves encoding a message into a pulse signal.

In an example of the present invention, pulse width modulation is used to control the amount of power supplied to an electrical device that includes an inertial load (e.g., an electric motor). The average value of the voltage (and current) fed to such a load is controlled by quickly switching on and off the switch between the power supply and the load. The longer the switch is on, the higher the total power supplied to the load will be, compared to the period when the switch is off. In the examples of the present invention, the pulse width modulation switching frequency is much higher than the switching frequency that will affect the load (the device using power). The resulting waveform as perceived by the load (e.g., the motor) is made as smooth as possible. Thus minimizing jitter.

It is sometimes necessary (e.g., when an error condition exists) to have a Pulse Width Modulator (PWM) rapidly shut down one or more motors under PWM control. Examples of the present invention relate to an apparatus and method for quickly shutting down a device for PWM control while minimizing the possibility of injury to people, motors, and machinery due to the shutdown.

Within this disclosure, the term 'event indication signal' refers to a signal (e.g., within a device or network) that indicates that a Pulse Width Modulator (PWM) may be required to rapidly shut down one or more motors, such as in a power stage cut-off. In examples of the present disclosure, the one or more Event Indication Signals (EIS) may come from various sources. One or more examples of the invention relate to systems and methods for managing EISs from such sources. At least one example of the invention pertains to a method of reducing unnecessary EIS production by such sources.

EIS may be caused by operational errors of devices, circuits, components, etc. EIS may also correspond to a transient fluctuation. The glitches contain signals caused by minor operational errors that do not actually necessitate a power stage shutdown. Transient fluctuations contain transient signal errors that may be caused by non-error events, such as electromagnetic interference caused by environmental factors. The glitch corresponds to a 'false positive' detection of an error event. At least one example of the invention is a method of mitigating the effects of glitches. In one or more examples, if the filter determines that the EIS is not due to a glitch, the filter will transmit a Trip Event Indication Signal (TEIS); in an ideal situation, all false alarm EISs are filtered out, and all positive alarm (true positive) EISs are communicated to a trip signal transmitter (e.g., logic circuit 421 shown in fig. 4B). Notably, EISs may have varying lengths, and in general, the longer the EIS is sustained, the greater the likelihood that the EIS indicates a fault rather than just a glitch.

At least one example of the invention is a method of combining multiple TEIS into a single TEIS.

Examples of the present invention include diagnostic mechanisms and methods for identifying sources of EIS, determining with great accuracy when an event that produces a given EIS occurs (accurate to within plus or minus three nanoseconds), and storing this source and timing information for consideration. Unlike conventional solutions, mechanisms and methods provide the ability to read back EIS source information and timing information for multiple events. The ability to immediately respond to errors is a corollary to the accuracy of the miscoordinated determination. For example, in an implementation of the present technology, a Field Effect Transformer (FET) -based power stage must be shut down within the wrong 1 microsecond to avoid damaging the FET-based power stage. In some implementations, the damage prevention requires that the FET-based power stage be shut off before no more than 500 nanoseconds of error conditions have elapsed. For error conditions to be handled quickly, the error condition must be passed quickly to the shutdown mechanism; the delay from detecting a false signal to tripping the PWM should be minimized.

Depending on the operating environment of a given ICSS, and taking into account propagation delays in the signal chain of one or more devices with which the ICSS interacts (and/or communicates and/or controls), the longest acceptable delay between transmitting the EIS and issuing the trip signal will be 10 nanoseconds. However, as described above, the longer the EIS is sustained, the greater the likelihood that the EIS indicates a fault rather than just a glitch. And vice versa; the shorter the EIS, the greater the probability that the EIS is caused by a transient fluctuation. Thus, there is a tradeoff between ensuring that errors are immediately resolved (e.g., by powering down components) and avoiding acting on false positives (e.g., glitches caused by extraneous signal fluctuations).

In one or more examples of the disclosure, the ICSS user may adjust the response time to avoid acting on false detections. In some examples, a user may change the setting of the glitch filter, such as by lengthening or shortening the length of the EIS that is required for the glitch filter to send the TEIS to the trip signal controller (e.g., the logic circuit 421 illustrated in fig. 4B). Typical glitch filter settings are from 10 ns to 100 ns. In at least one example, if the glitch filter is not set to zero (0), the glitch filter will cancel all of the noise, but (as explained) will also increase the propagation delay. In some examples, the user may also adjust the sensitivity of the trip signal controller (such as the logic circuit 421 illustrated in fig. 4B) itself. Here, a user may increase or decrease the length of time required for the trip signal controller to read one or more incoming TEIS (e.g., from one or more error signal sources) before the trip signal controller will trip the PWM.

At least one example within this disclosure is a system that includes a position feedback interface, a motor current and voltage interface, a Pulse Width Modulator (PWM), a programmable real-time unit, and trip generation hardware configured to generate a trip signal based on a set of static and/or dynamic input events for each motor controlled by a given PWM. In one or more examples, the system may be dynamically configured. In at least one example, the system enables programmable selection of input events to the trip signal generation logic. An example of the present invention is a system configured to enable programming of event-based transient fluctuation mitigation.

At least one example of the present invention is a programmable state machine having an active state and a reset state. In some examples within this disclosure, the reset state is used for a pulse width modulation cycle. In one or more examples, the reset state is controlled by a software reset and/or a timer. In an example of the invention, the system includes a reset function that implements single and/or cycle-by-cycle EIS analysis.

An example of the present invention is a configurable hardware state machine capable of managing pulse width modulation with minimal latency. An example of the present invention is a configurable hardware state machine that is capable of managing a power stage shutdown regardless of the source of the event that requires such power stage shutdown. In at least one example, all EIS inputs are ingested by a single hardware device with minimal latency and minimal jitter for EIS management.

As used in the present invention, the term jitter refers to deviations from the true periodicity of a generally periodic signal (which is typically related to a reference clock signal).

In an example of the present invention, a communication protocol is a system of rules that allow two or more entities of a communication system to communicate information. Certain communication protocols, such as EtherCAT (ethernet for control automation technology), may have multiple datagrams within one packet, requiring that the packet be parsed multiple times with variable start offsets. EtherCAT is an ethernet-based fieldbus system. The fieldbus system is an industrial network system for real-time distributed control. The EtherCAT protocol is standardized in IEC 61158 and is suitable for both hard and soft real-time computing requirements in automation technology. Real-time systems like EtherCAT need to have their data packets parsed during the reception process and make processing/forwarding decisions, e.g. where to send the received packets, before the end of the packets has been reached during the reception process.

As noted, many different communication protocols have been developed across different industries and market segments to address real-time communication for data exchange running on proprietary developed processing devices, such as socs, DSPs, ASICs, and FPGAs. Examples of the present invention are directed to providing and/or enabling multi-protocol flexibility for communication between such processing devices. At least one example of the present invention is directed to providing and/or enabling real-time ethernet communications at speeds of 1 gigabit/second or faster.

At least one example of the present disclosure is an architecture for an industrial communication subsystem (ICSS) that addresses the flexibility requirements of multiprotocols and the performance requirements of real-time gigabit ethernet. With integration onto the directory processor, industrial communication is made as easy as standard ethernet. ICSS has a hybrid architecture. In one example, the ICSS includes four 32-bit Reduced Instruction Set Computer (RISC) cores, referred to as programmable real-time units (PRUs), coupled with a set of compact hardware accelerators. A Reduced Instruction Set Computer (RISC) is a computer that: its Instruction Set Architecture (ISA) allows it to have fewer Cycles Per Instruction (CPI) than Complex Instruction Set Computers (CISCs).

The combination of 128/256 gigabits/second data transfer and a deterministic programming resolution of 4 nanoseconds (ns) is a highly distinguishable method of communication interface. A detailed view of a hardware accelerator in conjunction with an 128/512 gigabit/second data bus architecture is illustrated in fig. 2A-2C.

Examples of the present invention relate to programmable real-time unit subsystems and industrial communication subsystems (PRU-ICSS) that include a dual 32-bit RISC core (PRU), data and instruction memory, internal peripheral modules, and an interrupt controller (INTC). The programmable nature of the PRU-ICSS, along with its access to pins, events, and all SoC resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, peripheral interface control, and in offloading tasks from other processor cores of a system-on-a-chip (SoC).

For industrial ethernet usage scenarios, ICSS may require a trade-off between programmability (flexibility) and the need to maintain line rate packet loading. In one example, a programmable component (PRU) will run at a 250MHz clock and thus limit the firmware (f/w) budget to approximately 84 cycles per packet (for minimum sized transmit and receive frames). This may be insufficient for full 802.1D compliant packet processing at 1GHz rates. Thus, an exemplary ICSS of the present disclosure includes a Hardware (HW) accelerator for time-consuming bridging tasks.

According to the disclosed example, the PRU microprocessor core has a load/store interface to external memory. Using data I/O instructions (load/store), data may be read from or written to external memory, but at the cost of stalling the core while the access is taking place. Reading an N-32 bit word typically takes about 3+ N cycles, while writing takes about 2+ N cycles.

In at least one example, broadside RAM and/or broadside interfaces are optimized for 32-byte wide transfers. Lower transfer widths may be supported by padding the size to 32 bytes. In at least one example, the read location is first written to the attached RAM using the xout broadside instruction, and then the data is read using the xin broadside instruction. Thus, the read operation will take two cycles. For a write transfer, the address is placed in the register just after the register holds 32 bytes of data, and the data plus the address is transferred to the attached RAM with one xout instruction. In at least one example, this approach has the additional advantage of also being able to perform operations on the data, possibly in parallel with the transfer.

In addition to speeding up writes and transfers, examples of the invention provide advantages such as glue logic between the RAM and the broadside interface locally storing the last accessed RAM address, which allows an auto-increment mode of operation so the firmware does not have to continually update addresses (especially useful for bulk reads). Examples of the present invention enable useful operations on data using this interface in parallel with write operations. For example, cut through data may be run through a checksum circuit to calculate a running checksum for a packet while the packet is stored in RAM. In at least one example, the processor may perform byte-order flipping of data within the packet at various data size boundaries. In at least one example, a data perspective (pivot)/swap operation may be performed using this interface, for example, to swap registers r 2-r 5 with r 6-r 9. This is useful when moving data between interfaces with different block sizes, such as the 32-byte RX FIFO and the 16-byte PSI interface. In an alternative example, an organization is associated with attached memory or separate memory 'views' are achieved through different firmware tasks, by using different broadside Identifiers (IDs) (parameters of broadside instructions). The broadside ID may be mapped to different read or write memory addresses (maintained by glue logic) so that data structures such as FIFOs (first-in-first-out) and queues may be implemented in a flexible and firmware-managed manner by the attached RAM. At least one instance utilizes embedded processing.

In at least one example of the present invention, the ingress filter hardware implements hardware decisions for real-time forwarding and processing in conjunction with an ingress classifier. This filter hardware is placed at a variable and content dependent start address, reloaded with a variable and content dependent start address within the packet, masked for the application address range, and compared with greater and smaller operations.

In examples of the present invention, multiple hardware filters may be combined with binary logic to form a complex receive decision matrix. In an example, multiple hardware filters may be combined with a time window to make time-aware reception decisions. Multiple hardware filters may also be combined with a rate counter to make rate-limited reception decisions.

In at least one example of the disclosure, hardware filters and classifiers enable packet-related decisions to be received and forwarded with relatively small bridging delays. In an example, the combination of content, time window, and data rate provides a robust ingress classification for ethernet bridging while maintaining a relatively small bridging delay. As will be explained in more detail below, examples of the present invention achieve a bridge delay of less than 1 microsecond.

Fig. 1 is a functional block diagram of an ICSS architecture based system 100 (which may be a component of SoC 130) according to one example of the present invention. In fig. 1, a 16 kilobyte broadside random access memory (BS-RAM)101 is coupled to (in signal communication with) AUX _ PRU 112. BS-RAM101 is coupled to PRU116 via AUX _ PRU 112. BS-RAM101 may transfer 32 bytes of data in one clock cycle of system 100. The BS-RAM101 has ultra-high bandwidth and ultra-low latency. Within the present invention, coupled components (e.g., circuits) are capable of communicating with each other. Connected components are components that are coupled via a direct connection or an indirect connection. Within the present invention, components coupled to each other are also connected unless an indication to the contrary is provided.

As illustrated in fig. 1, data incoming through the interface circuit 104, which is a real-time interface, is passed to the FIFO receive circuit 105. The classifier 108 is applied to this incoming data as it passes through the receive circuitry 105. The combinatorial logic of filter 106, rate counter 107, and classification engine 108 is applied to the received packet.

The management data input/output (MDIO) circuit 102 is a media interface. The MDIO circuitry 102 uses the PRU116 to communicate with external Reduced Gigabit Media Independent Interface (RGMII) physical layers and Media Independent Interface (MII) physical layers (interface circuitry 104, interface circuitry 119). The MDIO circuit 102 has low latency and is dedicated to the PRU 116. As shown in fig. 1, the system 100 also includes a statistics counter circuit 103 that tracks statistics, such as packet size, errors, etc., of the ethernet port of the real-time interface circuit 104. Real-time interface circuit 104, including RGMII, Serial Gigabit Media Independent Interface (SGMII), and real-time media independent interfaces 231, 259(RTMII), is a hardware layer that connects to the input/output (IO) of system 100, such as MDIO circuit 102. Real time interface circuit 104 is coupled to FIFO receive circuit 105, which includes a level one first-in-first-out (FIFO) receive layer (RX _ L1) and a level two FIFO receive layer (RX _ L2). The FIFO receive circuit 105 may receive level one FIFO data and level two FIFO data.

As noted, system 100 includes filter 106, which is a filter for eight filter type 1 data streams and/or sixteen filter type 3 data streams. The filter 106 determines whether a given packet is a particular "type" of packet. Filter type 3 packets have a variable starting address depending on whether the packet is to be delivered using a virtual LAN. The system 100 also includes a rate tracker 107. In at least one example, the system 100 includes eight rate trackers 107. Based on the filter type hit rate, rate tracker 107 calculates the throughput rate of FIFO receive circuit 105. The system 100 also includes a Filter Database (FDB) 109. FDB 109 is used for routing and redundancy. Receive circuit 105 includes a level one receive layer (RX _ L1) including physical receive ports and a level two receive layer (RX _ L2). The level one receive layer (RX _ L1) and the level two receive layer (RX _ L2) of receive circuitry 105 may access FDB 109 to manage receive and forward decisions based on ieee802.1q learning bridge mode 1. FDB 109 contains a look-up table (LUT) that stores results that may be assigned to PRU116 to assist PRU116 in making data routing decisions. In at least one example, the system 100 also includes a virtual local area network TAG (VLAN TAG) circuit 110. The tag (a/k/a 'ID') is a key or term assigned to a piece of information, such as an internet bookmark, digital image, database record, computer file, or VLAN. The statistics tracker 103, the filter 106, the rate tracker 107, the classifier 108, the FDB 109 and (optionally) the VLAN TAG 110 are aspects of the receiving circuit 105.

The MDIO circuitry 102 controls interaction with an external physical layer (not shown) of the system according to the Open Systems Interconnection (OSI) model. The physical layer connects link layer devices, such as Media Access Controllers (MACs) (see 206(266) and 220(290) of fig. 2A, and 266 and 290 of fig. 2C) to the physical medium of a host (e.g., 246) device/system to which subsystem 200 is coupled for components of the host device/system or subsystem 200. The physical layer includes both Physical Coding Sublayer (PCS) functionality and Physical Media Dependent (PMD) layer functionality. There is a transceiver external to SoC 130 in which system 100 is embedded. The MDIO circuit 102 configures one or more external physical layers (not shown) and minimizes the latency of the ICSS.

Each Central Processing Unit (CPU), such as programmable real-time unit 116, contains a task manager circuit, such as task manager circuit 111. In at least one example, task manager circuit 111 and task manager circuit 121 may recognize 200 events or more. The events correspond to hardware status signals, for example, from the filter 106, from the rate tracker 107, or from the interrupt controller 123. The AUX _ PRU 112 is responsible for control. For example, based on the start frame, the PRU-RTU 112 detects that a new packet will be destined for the data processor-PRU 116, and in parallel with the data processor collecting the data, the PRU-RTU 112 will set an address and Direct Memory Access (DMA) per packet as needed to get the packet to the host (130, 246). Although the data is pushed to the BS-RAM 117, the data may also be pushed to a checksum accelerator, such as CRC 120. Therefore, CRC 120 may cause BS-RAM 117 to abort. Transmit circuit 113 communicates with AUX _ PRU 112 and PRU 116. Transmit circuit 113 may Receive (RX) and Transmit (TX) information, as indicated by the symbol 'RX/TX' in fig. 1. The transfer circuit 113 is configured with DMAs that enable both AUX _ PRU 112 and PRU116 to access the primary system 100 memory. When AUX _ PRU 112 or PRU116 initiates a transaction, transfer circuit 113 will manage the movement of data to SoC 130 memory to pull or push data. The transfer circuit 113 is thus a generic asset that can be used for data transfer. In at least one example, in the architecture of fig. 1, AUX _ PRU 112 may control the address location while PRU116 pushes data. Thus, the architecture is flexible in that a single CPU (e.g., 112, 116) is not responsible for both data management and control functions.

In at least one exemplary subsystem 100, there is a fabric with local memory. The structure in the exemplary subsystem 100 of fig. 1 may be 4 bytes wide. However, there are two sets of data memory 114 dedicated to each CPU (e.g., 112, 116), and the other set of larger memory 115 is shared across the CPUs (112, 116). The data memory 114 may be used with the scratch pad 126 and scratch pad 127, while the shared memory 115 is used for linked lists, which are used for DMA or for storing metadata. The registers 126, 127 are like the BS- RAMs 101, 117. However, the temporary memory 126 and the temporary memory 127 are different from the BS-RAM101 and the BS-RAM 117 in that the temporary memories 126, 127 are shared among slices (see slice _0 of FIG. 2A and slice _1 of FIG. 2C), and the temporary memories 126, 127 are more flexible than the BS-RAM101, 117. The scratch pad (e.g., 126, 127) may save and/or restore the register set. The scratchpad 126, 127 may be used for slice-to-slice communication and perform barrel shifting or remapping of the register sets to physical locations. BS-RAM 117 is similar to BS-RAM101 except that BS-RAM 117 also has an FDB containing a look-up table. When a packet enters the system 100 at the receive circuit 105, the hardware performs a lookup of the FDB 109 and presents the data to the PRU 116. Based on the response of the FDB of BS-RAM 117, PRU116 makes routing decisions, such as whether to route received packets to a host via transfer circuitry 113 and/or to different ports, such as by transmit circuitry 118. PRU116 also accesses BS-RAM 125. The PRU116 acts as a switch while the BS-RAM 117 enables actions to be performed simultaneously. The BS-RAM 117 is thus a dual purpose component. While the BS-RAM 117 performs a lookup of the FDB 109 for the PRU116, the hardware may be connected to the BS-RAM 117. Just as the checksum may be performed by CRC 120 while RAM (e.g., 114) is loaded, FDB operations may be performed for PRU116 by BS-RAM 117 while BS-RAM 125 interacts with hardware.

Transmit circuitry 118 handles data transfer out of PRU 116. The transmission circuit 118 performs preemption, tag insertion, and padding. The transmit circuitry 118 enables the firmware to cleanly terminate the packet. Thereafter, task manager circuit 121 will perform the necessary steps to generate the final CRC and if the packet in question is small, transmit circuit 118 will perform padding. Transmit circuitry 118 may insert a tag so that PRU116 does not have to track the packet. The transmission circuit 118 can thus assist the hardware of the SoC 130. The transmission circuit 118 is coupled to an interface circuit 119. Interface circuit 119 is the final layer. Outside the transmission circuit 118, there are different media independent interfaces, for example RGMII, SGMII and real-time MII (see 104, 119, 225 (295)). Other types of interfaces on the system 100 are also possible within the present invention. The FIFO transmit circuit 118 is agnostic with respect to such interfaces. The interface circuit 119 is a demultiplexer. Interface circuitry 119 provides protocol translation to transmission circuitry 118, thereby enabling transmission circuitry 118, and thus PRU116, to communicate with the hardware of a given piece in a protocol appropriate for that hardware. PRU116 and transmit unit 118 are therefore not constrained to operate in a manner corresponding to only one protocol, making PRU116 and transmit circuit 118 more versatile than they would be in the absence of interface circuit 119. In at least one example of the invention, system 100 has the data flow of interface circuit 119 constrained to connect to an external physical layer. Referring to the level of the Open Systems Interconnection (OSI) model, transmit circuit 118 has a level one FIFO transmit layer (TX _ L1) and a level two FIFO transmit layer (TX _ L2). Level one (or 'layer') corresponds to the physical layer of the OSI model and level two corresponds to the data link layer of the OSI model. This dual-layer connectivity provides several options. For example, level two FIFO transport layer (TX _ L2) may be bypassed and data may be sent to level one FIFO transport layer (TX _ L1), which reduces latency. In at least one example, tier two FIFO transport layer (TX _ L2) has a wider interface than tier one FIFO transport layer (TX _ L1). In at least one example, level two FIFO transport layer (TX _ L2) has a 32 byte interface, while level one FIFO transport layer (TX _ L1) has a 4 byte interface. In at least one example, if at the receive circuit 105, a data packet goes from the level one receive layer (RX _ L1) to the level two receive layer (RX _ L2)272(257), and the PRU116 accesses the packet at the level two receive layer (RX _ L2), then data will be pushed first to the level two FIFO transmit layer (TX _ L2) of the FIFO transmit circuit 118, and then the hardware of the FIFO transmit circuit 118 pushes the data packet directly to the level one FIFO transmit layer (TX _ L1). However, when communicating with a very low latency interface (e.g., EtherCAT), the level two FIFO transport layer (TX _ L2) may be bypassed; data output from PRU116 may be pushed directly to level one FIFO transport layer (TX _ L1), (which as noted, has a 4-byte width).

Interface circuit 104 and interface circuit 119 are at level zero of the OSI model. Thus, data enters system 100 at level zero through interface circuit 104, moves from level zero to either the level one receive layer (RX _ L1) of FIFO receive circuit 105 or the level two receive layer (RX _ L2)272(257) of FIFO receive circuit 105 all the way to PRU116 (which exists at both level one and level two), and from level one or level two of PRU116 through FIFO transmit circuit 118 and back to level zero at interface circuit 119. In at least one example, Cyclic Redundancy Check (CRC) circuit 120 is an accelerator that assists PRU116 in performing computations. PRU116 interfaces with CRC circuitry 120 through BS-RAM 117. CRC circuit 120 applies a hash function to the data of PRU 116. CRC circuit 120 is used to verify the integrity of the data packet. For example, all ethernet packets include a CRC value. CRC circuit 120 performs a CRC check on the packet to see if the CRC value of the packet is consistent with the result calculated by CRC circuit 120. That is, the packet includes a CRC signature and after the signature is computed, the result is compared to the signature appended to the packet to verify the integrity of the packet.

The system 100 also includes an interrupt controller (INTC) 123. The INTC 123 aggregates CPU (e.g., AUX _ PRU 112, PRU116) level events to host (e.g., 130, 146) events. For example, there may be ten host events. INTC 123 determines that a given set of slave level events should be aggregated, mapped and classified into a single entity. A single entity may be routed to and used by PRU116 or task manager circuit 121 to raise events for hosts (130, 146). In that sense, the INTC 123 is both an aggregator and a router.

Enhanced/external capture (eCAP) circuitry 124 is a timer that enables PRU116 to generate an output response based on a time match with Industrial Ethernet Peripheral (IEP) circuitry 122 and capture event times of events external to system 100.

IEP circuitry 122 has two sets of independent timers that enable time synchronization, time stamping, and quality of service for data coming out of system 100. There are several independent capture circuits associated with IEP circuit 122. For example, if there is a Receive (RX) start frame event and it is important to push the frame to the host at a particular time, IEP circuitry 122 may timestamp the event to indicate the particular time. If the event is a time-triggered transmission for egress circuit 118, and if it is desired to deliver the packet at a precise time (within 2 nanoseconds to 3 nanoseconds), transmission of the packet begins upon expiration of the timer independent of PRU 116. Thus, the transmission of packets is effectively decoupled from PRU 116.

In addition to the depicted timer, IEP circuitry 122 also contains an enhanced digital input/output interface (EDIO). EDIO is similar to a general purpose input/output (GPIO) interface, but is more intelligent and better calibrated for ethernet communications. For example, transmitting a start frame or receiving a start frame may cause an event on the EDIO, which in turn may cause an event external to the SoC 130. The synchronization out and lock in are part of the time synchronization. It is also possible for IEP 120 to receive frames and capture analog voltages. In conventional systems, this would require a read operation. But for EDIO, the capture may be event-triggered and/or time-triggered, thus making the capture more accurate than in conventional systems. EDIO enables the system 100 to accurately determine when an incoming frame arrives, which in turn enables the system 100 to sample one or more specific values (e.g., temperature, voltage, etc.) and accurately track as the samples are taken due to the time stamps of the IEP circuit 122. The frame in question may be augmented. When the frame is transmitted by transmit circuit 118, the frame may contain time-stamped sample values without increasing overhead or latency. IEP circuitry 122 also includes a Watchdog (WD) timer. Certain events should occur under normal operating conditions. When such an event occurs, PRU116 will typically clear the WD timer. If the WD timer fires, this means that PRU116 does not timely clear the WD timer or timely reset the WD timer, indicating that there is an undesirable pause or some type of latency. The WD timer is thus used to track errors.

As described, task manager circuits 111 and 121 may recognize a large number of events. PRU116 is the primary data engine of system 100. When a frame is initiated, system 100 begins to prepare and service receive circuitry 105. Once the frame is in transmit circuitry 118, the entry of the next packet may begin. Since PRU116 is the primary processor, PRU116 needs to access all events in real time. Another operation associated with PRU116 is watermarking. Watermarks may be formed at interface circuitry 104, receive circuitry 105, transmit circuitry 118, and interface circuitry 119. It is undesirable to wait until the FIFO is full before loading or unloading a packet, as this will be too late, and to wait until the FIFO is empty, as this will be too early, when a certain amount of vacancy (or fullness) is reached, the task manager circuit 121 may fire, and the PRU116 will determine whether to watermark the packet.

An aspect of BS-RAM 117 is that it enables PRU116 to snoop the packet while system 100 can save the context and variables at BS-RAM 117, and can perform operations on the context and variables without overhead cost, since it is not necessary to move the data of the packet twice. In at least one example of the present disclosure, an incoming data packet may be moved to a storage location and the data operated on simultaneously. This is different from conventional systems that move incoming packets to processing circuitry and then to a storage location. The system 100 thus performs a single operation, whereas a conventional system would perform two operations.

As depicted, AUX _ PRU 112 interacts with BS-RAM 101. AUX _ PRU 112 has task manager circuitry 111 that can preempt PRU116 based on the occurrence of certain events or context exchanges. AUX _ PRU 112 also interacts with transmit circuitry 113. In at least one example, the system 100 according to the present disclosure also includes eight kilobytes of data RAM 114 and 64 kilobytes of shared RAM 115. AUX _ PRU 112 and transmit circuit 113 both interact with PRU 116. The task manager circuit 121 inputs real-time tasks for reception and transmission processing based on the FIFO watermark. The PRU116 is also coupled to a 16 kilobyte BS-RAM filter database 117. The output from PRU116 goes to FIFO transmit circuit 118. The output from the FIFO transmission circuit 118 then goes to the real-time interface circuit 119. PRU116 also interacts with CRC 120, which computes checksums inside ethernet packets. In at least one example, the system 100 includes an IEP/timer/EDIO/WD circuit 122. As described, the system 100 may also include an interrupt controller (INTC)123 and eCAP circuitry 124.

Fig. 2A-2C illustrate an exemplary industrial communication subsystem (ICSS) (hereinafter referred to simply as subsystem 200). Fig. 2A-2C illustrate many of the same components as shown in fig. 1, but in different detail. The description set forth with respect to fig. 1 is germane to fig. 2A-2C, and vice versa. Slice _0201 on the left side of internal bus 248 and external bus 247 is symmetric to slice _ 1261 on the right side. (Note that similar letter designations indicate similar components.) the description of the components in slice _0201 applies to their counterparts in slice _ 1261. As illustrated in fig. 2, subsystem 200 includes a processing hardware element containing one or more hardware processors, such as an auxiliary programmable real-time unit (AUX _ PRU _0)205 and PRU _0219, where each hardware processor may have one or more processor cores. In at least one example, a processor (e.g., AUX _ PRU _ 0205, PRU _ 0219) can include at least one shared cache that stores data (e.g., computing instructions) utilized by one or more other components of the processor (AUX _ PRU _ 0205, PRU _ 0219). For example, the shared cache memory may be locally cached data stored in memory for access by components of the processing elements that make up the processor (AUX _ PRU _ 0205, PRU _ 0219). In some cases, the shared cache may include one or more mid-level caches, such as a level 2 cache, a level 3 cache, a level 4 cache, or other levels of cache, a last level cache, or a combination thereof. Examples of processors include, but are not limited to, CPU microprocessors. Although not explicitly illustrated in fig. 2, the processing elements making up processors AUX _ PRU _ 0205 and PRU _0219 may also include one or more other types of hardware processing components, such as graphics processing units, ASICs, FPGAs, and/or DSPs. Another accelerator for PRU _1 is BSWAP circuitry 224 (294). BSWAP circuitry 224(294) may swap words depending on the size, little endian, and/or big endian of the packet in question. BSWAP circuitry 224(294) may reorder bytes in the packet depending on word size.

Subsystem 200 contains slice _0201 mirrored by slice _1 in fig. 2C. As can be seen in fig. 2A, slice _0201 has multiple components. The primary components are the secondary PRU (AUX _ PRU _0)205, PRU _0219, and MII 228. AUX _ PRU _ 0205 has several accelerators (a/k/a gadgets). AUX _ PRU _ 0205 serves as the control processor for slice _ 0201. Throughout this disclosure, the terms 'control processor', 'AUX _ PRU', and 'RTU _ PRU' are synonymous and interchangeable, unless otherwise indicated or dictated by the context in which they appear, but may differ in function and configuration.

Fig. 2A illustrates that a memory (e.g., 204(264)) may be operatively and communicatively coupled to AUX _ PRU _ 0205. Memory 204(264) may be a non-transitory medium configured to store various types of data. For example, memory 204(264) may include one or more storage devices, including volatile memory. Volatile memory, such as Random Access Memory (RAM), can be any suitable volatile storage device. In a particular example, a non-volatile storage device (not shown) may be used to store overflow data if the allocated RAM is not large enough to hold all working data. Such non-volatile storage may also be used to store programs that are loaded into RAM when such programs are selected for execution.

Software programs may be developed, encoded, and compiled in a variety of computing languages for a variety of software platforms and/or operating systems and then loaded and executed by AUX _ PRU _ 0205. In at least one example, the compilation process of the software program may transform the program code written in the programming language into another computer language, such that AUX _ PRU _ 0205 is capable of executing the programming code. For example, a compilation process of a software program may produce an executable program that provides encoded instructions (e.g., machine code instructions) to cause AUX PRU 0205 to implement specific non-generic computing functions.

Following the compilation process, the encoded instructions may then be loaded from storage 220(290), from memory 210 into AUX _ PRU _ 0205, and/or embedded within AUX _ PRU _ 0205 (e.g., via cache or on-board ROM) as computer-executable instructions or process steps. In at least one example, AUX _ PRU _ 0205 is configured to execute stored instructions or process steps to perform instructions or process steps to transform the subsystem 200 into a non-generic and specifically programmed machine or apparatus. Stored data (e.g., data stored by storage 220(290)) may be accessed by AUX _ PRU _ 0205 during execution of computer-executable instructions or process steps to indicate one or more components within subsystem 200.

Fig. 2B illustrates components and resources shared by slice _0 of fig. 2A and slice _1 of fig. 2C. Fig. 2C includes the same hardware as fig. 2A. slice _0201 and slice _ 1261 are symmetric about fig. 2B. The description of the invention relating to fig. 2A applies mutatis mutandis to fig. 2C. Subsystem 200 includes subsystem 200 also includes a corresponding port 276 at slice _0201 and on slice _ 1261. There is a third port (see fig. 2B), a host port 245, the host port 245 connecting the subsystem 200 to a host 246, which the subsystem 200 may be a component of. Both port 253 and port 276 may be connected to ethernet. The subsystem 200 may thus function as a three-port switch. The host 246 may be a local source/sync or SoC (130). Although the subsystem 200 option may itself be a SoC (130), in some implementations, the subsystem 200 will be a sub-component of a larger SoC (130). In some examples, host 246 will be a CPU from ARM Holdings PLC, Cambridge, England, UK, England. In at least one example, host 246 includes several CPUs. There are various types of CPUs. An example of a small CPU is Arm Cortex-R5-CPU. An example of a large CPU is Arm Cortex-A57-CPU. In at least one example, subsystem 200 may be controlled by another such CPU.

As shown, the subsystem 200 includes an XFR2TR circuit 202 (fig. 2A) that interacts with an internal configurable bus array subsystem (CBASS)248 (fig. 2B). The 'XFR' in XFR2TR circuit 202(280) represents a transfer. The XFR2TR circuit 202(280) has a broadside interface. The XFR2TR circuit 202(280) is interfaced to AUX _ PRU _ 0205 via the broadside interface of the XFR2TR circuit 202 (280). The internal register set of AUX _ PRU _ 0205 is disclosed to accelerator MAC 206, CRC 207(267), SUM32 circuit 208(268), byte-switched (BSWAP) circuit 203(263), and BS-RAM 204 (264). In at least one exemplary subsystem 200 of the present invention, the set of internal registers of AUX _ PRU _ 0205 is directly disclosed to an accelerator such as mentioned above, which is different from the architecture of conventional systems. In conventional systems, load-store operations would need to be performed on the fabric to have AUX _ PRU _ 0205 access to the accelerator. However, in the example shown in fig. 2, the accelerator is actually part of the data path of AUX _ PRU _ 0205. AUX _ PRU _ 0205 may import and export its register file to a given accelerator (a/k/a 'gadget') based on the broadside ID of the given register. For example, the XFR2TR circuit 202(280), which is part of a DMA, may execute a transfer request. A Transfer Request (TR) may start with a start address to start data movement, specifying the amount of data to be moved (e.g., 200 bytes). XFR2TR circuitry 202(280) may perform simple DMA memory copies of SMEM235 that contain a list of scheduled Transfer Requests (TRs). Software running on AUX _ PRU _ 0205 is aware of the list of pre-existing TRs of SMEM 235. In operation, AUX _ PRU _ 0205 sends an instruction to the DMA engine to move data. Since the transfer instructions may be extremely complex and/or complex, the predefined instructions reside within a 'work order pool' stored in SMEM 235. Based on the type of packet in question, AUX _ PRU _ 0205 determines which 'work orders' should be used and in what sequence to cause the packet to be sent to the correct destination. XFR2TR circuitry 202(280) may create a list of work orders as directed by AUX _ PRU _ 0205, and once the list of work orders is created, XFR2TR circuitry 202(280) will notify a DMA engine (not shown). The DMA engine will then pull the specified work command from SMEM235 and execute the pulled work command. Therefore, XFR2TR 202(280) minimizes the computational overhead and transfers necessary to construct DMA lists (like link lists) to perform data movement. TR stands for transfer request.

Another accelerator for AUX _ PRU _0 is BSWAP circuitry 203 (263). BSWAP circuitry 203(263) may exchange words depending on the size, little endian, and/or big endian of the packet in question. BSWAP circuitry 203(263) may reorder bytes in a packet depending on word size. The BSWAP circuitry 203(263) is thus an accelerator that will automatically perform such exchanges. BS-RAM 204(264) corresponds to BS-RAM101 discussed with respect to FIG. 1. BS-RAM 204(264) is tightly coupled to AUX _ PRU _ 0205. When AUX _ PRU _ 0205 pushes a data element to BS-RAM 204(264), the CRC for that element may be computed simultaneously by CRC 207(267) or the checksum for that data element may be computed simultaneously by checksum circuitry 208. Based on the ID of the packet, AUX _ PRU _ 0205 will snoop the necessary transactions simultaneously (e.g., checksum, multiply, accumulate, etc.), which means pushing data elements to BS-RAM 204(264) and performing acceleration constitutes a single transaction rather than a double transaction. This operational concurrency is achieved by BS-RAM 204(264) because BS-RAM 204(264) can enable and/or disable the functionality of the gadgets while data is being transferred to physical RAM (e.g., data RAM 114 and shared RAM 115 shown in fig. 1).

Although the peripheral devices BSWAP 203(263), XFR2TR circuit 202(280), MAC 206(266), CRC 207(267), and SUM 32208 are illustrated as being external to BS-RAM 204(264) for purposes of explanation, they will be embedded within BS-RAM 204(264) under most operating conditions. Multiplier-accumulator (MAC)206(266) is a simple accelerator comprising a 32-bit by 32-bit multiplier and a 64-bit accumulator. The Cyclic Redundancy Check (CRC) circuit 207(267) cyclically performs redundancy check. CRC circuits 207(267) support different polynomials. Checksum circuit 208 is like CRC circuit 207(267), except checksum circuit 208 uses a hash operation to determine the integrity of the payload at AUX _ PRU _ 0205 before performing a checksum on the payload.

The task manager circuit 209 is a critical part of AUX _ PRU _ 0205. The task manager circuit may prompt AUX _ PRU _ 0205 to perform a given function based on which of the 196 events was detected.

There are two ways in which data can be moved into and out of the subsystem 200, as well as to the SoC 130 memory and from the SoC memory and/or to an external device. One approach is through a Packet Streaming Interface (PSI)211(281) that provides the ability to push data to a host (e.g., 246) and pull data from a host (e.g., 246). This action of PSI 211(281) is different from a read request. Instead, the main (writer) component of PSI 211(281) is attached to AUX _ PRU _ 0205. There is a mapping of the received packets to the destination. Under normal operating conditions, the destination will be ready to receive the packet. For that reason, PSI 211(281) does not read the data, but rather transfers the data to the destination endpoint. PSI 211(281) receives data from and sends data to a navigation subsystem (NAVSS) 210. The NAVSS 210 implements complex data movement. The NAVSS 210 has a DMA engine and a high level TR called a reingine. NAVSS 210 supports PSI 211(281) and may map PSI 211(281) to other devices (e.g., via peripheral component interconnect express). Using PSI 211(281), data may go directly from the ICSS to the peripheral component interconnect express while bypassing the host and/or primary DMA engine, enabling data to be streamed from one ethernet interface (e.g., interface circuitry 225(295)) to another interface, such as a universal serial bus or peripheral component interconnect express.

AUX _ PRU _ 0205 communicates with an inter-processor communication scratchpad (IPC SPAD)212(282), which in turn communicates with PRU _ 0219. The IPC SPADs 212(282) are not temporary SPADs owned by a single CPU. For at least purposes, the IPC SPAD 212(282) is capable of transferring data or full controller state across AUX _ PRU _ 0205 and PRU _ 0219. The transfer to virtual bus circuit (XFR2VBUS) circuit 213 (or simply 'transfer circuit 213') corresponds to the transfer circuit 113 shown in fig. 1 and operates in the same manner as the transfer circuit 113. The transmission circuit 213(283) is attached to the BS-RAM 214 (284). The pass circuitry 213(283) has a broadside interface with external CBASS247, internal CBASS 248, and spin lock circuitry 249. The transfer circuit 213 can request reads and writes from memory (e.g., 204, 214) to the broadside and from the broadside to the memory. This read/write function is different from, for example, read/write operations at private memory (DMEM0) 233. Conventional DMA copy operations move information in SoC (130) memory to DMEM 0233 or to shared memory SMEM 235. The internal CBASS 248 is a network-on-chip (network-on-chip) of the subsystem 200.

The internal CBASS 248 is 4 bytes wide. In at least one example, to access the internal CBASS 248, load and store operations must be performed, which are high latency, low throughput operations. However, the use of tightly coupled and more direct transfer circuits 213(283) reduces latency and overhead while also providing greater bandwidth due to the broadside width of transfer circuits 213 (283). Thus, transfer circuitry 213(283) may act as a direct mapping from the register file to subsystem 200 memory (e.g., 233). Intermediate memory locations are bypassed and transfer circuitry 213(283) goes directly to the register file, which reduces latency.

As mentioned, PRU _0219 also has an accelerator, as does AUX _ PRU _ 0205. PRU _0219 corresponds to PRU116 of fig. 1. Like PRU116, PRU _0219 has a task manager circuit 223. The primary difference between AUX _ PRU _ 0205 and PRU _0219 is that PRU _0219 interacts with interface circuitry 104, receive circuitry 105, transmit circuitry 118, and interface circuitry 119 (see fig. 1), which are shown collectively in fig. 2A-2C as interface circuitry 225 (295). Interface circuitry 225(295) includes receive circuitry 270 including level one FIFO transport layer (TX _ L1)226(296) and level two transport layer (TX _ L2)262(256) (see fig. 1, 118). The transmission circuit 271 includes a level one receive layer (RX _ L1) and a level two receive layer (RX _ L2)272(257) (see 105, fig. 1).

BS-RAM 214(284) of PRU _0219 of AUX _ PRU 205 is the same as BS-RAM 204 (264). General purpose input/output (GPIO) circuitry 215(285) enables the subsystem 200 to access additional hardwires of the SoC (e.g., 130, 246). Sigma-delta circuits 216(286) are analog-to-digital converters that interact with one or more external sensors (not shown). The sigma-delta circuit 216(286) converts the analog data stream from the sensor to a digital data stream. The sigma-delta circuit 216(286) is a filter. The data stream from the sensor corresponds to the voltage or temperature at the external device (e.g., motor). Sigma-delta circuitry 216(286) informs PRU _0219 of a particular event (e.g., if there is a current spike, a voltage spike, or a temperature spike). PRU _0219 determines what action, if any, needs to be taken due to the spike.

Peripheral interface 217(287) is used to detect the position or orientation of the device under control of subsystem 200 (e.g., a motor or robotic joint). For example, the peripheral interface 217(287) uses a protocol to determine the precise radial position of the arm. The sigma-delta circuits 216(286) and the peripheral interfaces 217(287) are thus used for device control, such as robot control. Sigma-delta circuitry 216(286) and peripheral interface 217(287) are tightly coupled to PRU _0219, which enables subsystem 200 to be useful in industrial contexts.

The packet streaming interface PSI218 (288) of 219 is like PSI 211(281) of 205 PSI. 211(281) and PSI218 (288) interact with the navigation subsystem (NAVSS) PSI 210. However, while PSI 211(281) has four Receive (RX) inputs and one Transmit (TX) output, PSI218 (288) has a single Transmit (TX) output. As described, PRU _0219 can move the register file of PRU _0219 directly to ethernet line (port) 253. Thus, the data packet enters through the level one receiving layer (RX _ L1)227 of the receiving circuit 271 and the level two receiving layer (RX _ L2)272(257) of the receiving circuit 271; without reading the memory or by DMA. Alternatively, the data packet may be immediately popped (pushed) to PRU _0219 in a single data cycle. If desired, the data packet may be pushed to the level one transport layer (TX _ L1)226(296) or the level two transport layer (TX _ L2)262(256) in the next clock cycle, which may be referred to as a 'bridge-to-layer-cut-through' operation. In at least one example, the cross-layer bridging operation is faster than the store and forward operation. The cross-layer bridging operation may be performed while pushing data packets to host 246 (e.g., SoC 130) or slice _ 1261 (as appropriate) via PRU _0219 and port 245.

PRU _0219 is a RISC CPU whose register file can access the ethernet buffer without requiring access or through other memory. Interface 228(298), interface 229(299), and interface 230(258) are physical media interfaces and include at least one RGMII. Real-time media independent interface 228(298) is a 4-bit interface. Interface 229(299) is gigabits wide. Interface 229(299) is a reduced gigabit media interface (RGMII). Interface 230(258) is a Serial Gigabit Media Independent Interface (SGMII). In one or more instances, these identified interfaces are executed in real-time.

The ethernet interface circuitry 225(295) includes Receive (RX) classifier circuitry 232(108) that takes rate data (107) and filter data (106) as well as other data, and based on a predefined mapping function (e.g., a time function), the classifier circuitry 232(108) classifies packets according to this mapping function. The classification of a packet will determine the priority of the packet, which will specify which queue (high priority queue, low priority queue, etc.) to place the packet into. 225(295) is essentially a line dedicated to ethernet interface circuitry 225 (295). Port 253 is at level zero of the OSI model. Interface 252(255) is an interface between PRU _0219 and ethernet interface circuitry 225 (295). 270, (273) and 271(274) are circuits in FIFO configuration, as described. The FIFO transmit circuit 270(273) corresponds to the transmit circuit 118 of fig. 1, and the FIFO receive circuit 271(274) corresponds to the circuit 105 of fig. 1. While pushing data into FIFO circuits 270(273), sorter circuit 232 operates on the data.

Slice _0201 shares a number of resources 301 with Slice _ 1261, such as illustrated in fig. 2B. Slice _0201 and Slice _ 1261 are coupled to each other via internal CBASS 248. The internal CBASS 248 is coupled to the interrupt controller 236. The interrupt controller 236 is an aggregator that aggregates several event instances (recall that there are 196 possible events). Some of the events may come from the host (130)246, but most of the events are internal to the subsystem 200. Because there are a large number of possible events, the events must be aggregated or consolidated into a smaller number of superpackets for sharing with a large amount of data from the hosts (e.g., 246). Software running on PRU _0219 determines the source to output destination mapping.

As depicted, the subsystem 200 includes an internal configurable bus array subsystem (CBASS)248 as a shared resource. The internal CBASS 248 receives data from the external CBASS247 via the 32-bit slave port. The internal CBASS 248 communicates with private memory _ 0233, private memory _ 1234, and shared memory (SMEM)235 (115). SMEM235 is a general purpose memory. SMEM235 may be used to perform Direct Memory Access (DMA) operations with respect to a DMA instruction set, among other functions. The DMA is like registers (126, 127) and may contain control and status information. The internal CBASS 248 also communicates with an enhanced capture module (eCAP)237, which also communicates with an external configurable bus array subsystem (CBASS) 247. Enhanced capture module 237 is a timer for time management of external devices, such as motors.

In at least one example, the subsystem 200 has different modes of operation. AUX _ PRU _ 0205 and PRU _0219 each have a memory-mapped register. The host 246 writes information to the configuration manager circuit 238. For example, if the host 246 needs to enable RGMII mode, the configuration manager 238 will enable RGMII 229(299), which is an instance of a configuration register.

A universal asynchronous receiver-transmitter (UART)239 is a hardware device for asynchronous serial communication in which a data format and a transmission speed are configurable. The electrical signaling levels and methods are handled by driver circuitry external to the UART 239. The UART must operate at a specific baud-rate, which requires a fixed clock rate. The asynchronous bridge (AVBUSP2P)240 communicates with the internal CBASS 248 and the UART 239. The UART 239 in turn communicates with the external CBASS 247. AVBUSP2P 240 is a bridge that allows independent clocking of UART 239. External CBASS247 is coupled to industrial ethernet peripheral _0(IEP0)241A and industrial ethernet peripheral _1 (IEP1) 241B. IEP 0241 and IEP 1273 each include a timer, EDIO, and WD (122). IEP 0241A and IEP 1241B collectively enable two time domain management to run simultaneously. Similar AP 237 timer searches for timers of IEP0 and IIP2 must operate on a given frequency (e.g., 200 megahertz), but PRUs may be decoupled from these. Also, avbus p2P 240, avbus p2P 242, and avbus p2P 243 are couplers that allow UART 239, IEP 0241A, and IEP 1241B to operate at different frequencies, if desired.

As shown in fig. 2B, there is a second avbus p2P circuit 242 communicatively interposed between IEP 0241A and internal configurable bus array subsystem (CBASS) 248. There is also a third AVBUSP2P 243 communicatively interposed between IEP 1241B and internal CBASS 248. The subsystem 200 also includes a Pulse Width Modulator (PWM)244 communicatively interposed between the internal CBASS 248 and the external components.

Components 236, 237, 238, 239, 241A, 241B, and 244 are each connected to a particular SoC line. That is, each communicates with an IO of host 246.

FIG. 2B also shows that the subsystem 200 may include a spin lock 249, AUX _ SPAD 275, and PRU _ SPAD 250. Spin lock 249 is a hardware mechanism that provides synchronization between the various cores (e.g., 205, 219) of subsystem 200 and host 246. Conventionally, a spin lock is a lock that causes a thread attempting to acquire it atomically to simply wait in a loop ("spin") while repeatedly checking whether the lock is available. Using this lock is a busy green wait, since the thread remains active but does not perform useful tasks. Once acquired, a spinlock will typically be held until it is explicitly released, but in some implementations, the spinlock may be automatically released if the waiting thread (the thread holding the lock) blocks or "goes to sleep. Locks are synchronization mechanisms used to enforce restrictions on access to resources in an environment where there are many threads of execution. Locks enforce mutual exclusion concurrency control policies. For this reason, spin lock 249 provides automation of the operation of the components of subsystem 200. For example, the spin lock 249 enables each of the cores of the subsystem (e.g., AUX _ PRU _ 0205) to access a shared data structure (such as the data structure stored in SMEM 235), which ensures that the various cores are updated simultaneously. Accesses to the various cores are serialized through spin lock 249.

As shown in the exemplary subsystem 200, the auxiliary registers (PRU SPAD)250 and AUX SPAD 275 each hold three sets of thirty 32-bit registers. Subsystem 200 also includes a Filter Database (FDB)251(109), which includes two 8 kilobytes sets, and filter database control circuitry. FDB251 is a broadside RAM accessed by AUX _ PRU _ 0205 and PRU _ 0219. FDB251 may also be accessed by hardware engine sigma-delta 216(286) and peripheral interface 217 (287). The receive circuitry 271, which includes level one receive layer (RX _ L1)227(297) and level two receive layer (RX _ L2)272(257), may also access the FDB 251. FDB251 is a broadside RAM with respect to AUX _ PRU _ 0205 and PRU _0219 to read and write entries, but the hardware also uses FDB251 to provide an accelerated compressed view of packets arriving through port 253. The hardware will use a hashing mechanism to consult the memory of the FDB251 and deliver the result to PRU _0219 along with the packet. It is the routing function that determines where the packet will go next. AUX _ PRU _ 0205 and PRU _0219 access FDB251 via the broadside interface of FDB251 to add information and delete information. The receiving hardware 225(295) may also access the FDB 251.

Subsystem 200 may also include a communication interface 225(295) that may be communicatively coupled to processor 205, such as network communication circuitry that may include wired and/or wireless communication components. The network communication circuitry 225 may utilize any of a variety of proprietary or standardized network protocols, such as ethernet, TCP/IP, to name just a few of many protocols, to enable communication between devices. The network communication circuit may also include one or more transceivers that utilize ethernet, power line communication Wi-Fi, cellular, and/or other communication methods.

As mentioned, in the examples of the invention, packets are processed in a real-time deterministic manner, unlike conventional ethernet or IEEE ethernet processing, which more defines a 'best effort' traffic system in which packet loss occurs depending on the load of a given network. While conventional ethernet management is acceptable for many applications, such as video streaming, in an industrial environment (e.g., a robotic assembly line), the sent data packets are delivered accurately and according to a predetermined schedule (under ideal conditions). In the industry, packets must arrive according to strict scheduling. Of course, packet loss can occur in an industrial environment, but there are different methods in the various layers (above level 0, level 1, and level 2 to which embodiments of the present invention relate) to take care of packet loss.

When a packet is received from the physical layer (not shown) at level one receive layer (RX _ L1)227 and/or level two receive layer (RX _ L2)272(257), the packet classifier 232(108) analyzes the packet and identifies which portion of the packet is the content (a/k/a 'payload'). The packet classifier (a/k/a 'packet classification engine') 232 then makes an immediate decision as to what to do with the packet. The ethernet bridge 225(295) makes forwarding and receiving decisions with respect to each packet received (via the receive circuitry 271 and/or the ingress 253). In conventional IEEE ethernet bridging, such forwarding and receiving operations are performed in a 'store and forward manner', where an incoming data packet is received in a first step, and once the data packet has been received, the content is then reviewed in a second step. In conventional IEEE ethernet bridges, once the packet is completely received and the content is reviewed, a third step forwarding and receiving determination is made. After the forwarding and receiving determinations are made, the data packet is then provided to a mechanical transport layer (e.g., via transport element 226 (296)). In at least one example of the invention, these steps are simplified in a manner that minimizes latency and jitter. In at least one example, classification engine 232(260) is configured to perform the routine of a conventional IEEE ethernet bridge in an overlapping manner, whereby by the time a packet has been completely received at 271(272), classification engine 232(260) has determined what the packet needs to do, to what destination the packet needs to be sent, and by how.

In an example of the present invention, the bridging delay is the amount of time between when a packet arrives at port 253 and leaves on another port 276. During the time between data packet ingress and data packet egress, the subsystem 200 makes a handoff decision (determination) and then performs the transmit function, as described. In the standard ethernet IEEE community, store and forward architecture is used to perform the switching function, which necessarily has variable latency. Under variable latency conditions, there is no guarantee that when a packet is received at time zero on an incoming port 253(104, 105), it will leave at a fixed (a priori known) time on a different port (e.g., 276, 245). At least one benefit of the subsystem 200 is that the classification engine 232 makes it known that if a data packet is received at time zero, the packet will be sent out through another port (e.g., 245) within a predetermined (deterministic) period. In at least one example, this period is 1 microsecond. In at least one example, when a component (e.g., slice _ 0201) has such a short switching time, the component is considered a real-time component, capable of performing its assigned function 'in real-time'. In the examples of this disclosure, a real-time computing (RTC) describes a hardware and software system subject to "real-time constraints" (e.g., from events to system responses). For example, a real-time program must guarantee that the response is made within a specified time constraint (a/k/a 'deadline'). In some examples within the invention, the real-time response is on the order of a few milliseconds. In some examples within the invention, the real-time response is on the order of microseconds.

Examples of the present invention relate to a communication bridge operating in a real-time system. The communication bridge is a real-time control system in which input data and output data are exchanged in a deterministic manner. Examples of the present disclosure include control devices (e.g., 217(287), 244) and a plurality of slave devices (not shown) or devices (not shown) that consume input/output data from the control devices 217(287), 244 in real time. The real- time system 100, 200 has a communication bridge 255 real-time capability. Thus, the amount of time to forward a packet is deterministic, with minimal jitter and latency. In at least one example, jitter and latency are minimized (to the range of a few nanoseconds) by a hardware timer (not shown) that defines the time when a packet leaves the physical port 253, 252 (255). The real-time operability of the subsystem 200 is different from standard ethernet, where jitter of at least tens of microseconds is common. In such conventional systems, the amount of time it takes to make forwarding/routing determinations varies depending on when a packet arrives, the rate at which data packets are received, and the content of the packet. In the real-time system (e.g., 200) of the present invention, there is a cyclic execution of the switching function. For example, new data may be exchanged every 31 microseconds in the subsystem 200. A predetermined exchange rate (e.g., 31 microseconds) is used as a time reference. Depending on when a packet enters (e.g., via port 253), the packet is forwarded with a deterministic latency (31 microseconds in this example), or alternatively the data packet is handled according to a store and forward approach, as described above for conventional systems. Thus, the packet arrival time may be an authenticator for how a given data packet is to be processed by the subsystem 200. Another factor considered by the Receive (RX) classifier 232 in determining what to do with an incoming packet is the data (transmission) rate typically associated with the type of packet in question. For example, if the average data rate of received packets exceeds a particular data rate threshold, the system may drop (less important) data packets to help ensure that there is sufficient bandwidth for higher priority packets. In at least one example, classifier 232 determines the importance of a given data packet based at least in part on the payload of the packet.

In at least one example, the classifier 232 reviews the packet content by first accessing a location in the packet, such as the ethernet Media Access Control (MAC) address of the packet. The MAC address of a device is a unique identifier assigned to a Network Interface Controller (NIC) for communication at the data link layer of a network segment. The MAC address is used as a network address for most IEEE802 network technologies, including Ethernet, Wi-Fi, and Bluetooth. In at least one example, the MAC address is used in the medium access control protocol sublayer of subsystem 200. According to the present invention, a MAC address may be recognized as six sets of two hexadecimal digits separated by hyphens, colons, or using other symbologies.

The data packets may be filtered by the filter 106 based on their designated delivery address (not shown). The data packet includes six bytes of source and destination addresses. In at least one example, the interface circuitry 225(295) filters (106) packets based on the information. For example, interface circuitry 225(295) may read the network address of a packet and determine whether to accept the packet, forward the packet, or drop the packet. In at least one example, the accept-forward-discard decision can be based on a MAC header of the packet. In at least one example, when making the accept-forward-drop determination, the interface circuit may proceed further into the packet, reach the payload, and make the filter 106 determination based on the name in the payload. In some implementations of SoC 200, the device name is concatenated in the payload, and then content filter 106 looks at the payload.

In embodiments of the invention, a packet will typically contain multiple datagrams. This datagram multiplexing requires that a packet or a portion thereof be delivered to multiple addresses. In other words, there may be multiple sub-packets in the ethernet packet. Since the sub-packets may each have their own address, the address must be parsed. In the case where there are multiple addresses in one packet, the subsystem 200 will reinitiate the profiling whenever a sub-address is detected. Thus, interface circuitry 225(295) will have a variable starting offset for filter 106 to enable interface circuitry 225(295) to place multiple subpackets into a single ethernet packet. In at least one example, this means that sub-packets derived from a single data packet are sent to different devices (e.g., through peripheral interface 217 (287)); in an example of the present disclosure, a single ethernet packet may contain sub-packets, one or more of which are intended for (addressed to) different devices. The communications (packet switching) of the present invention are not point-to-point communications unless indicated otherwise. The communication of the present invention is based on a master-to-slave architecture. In an implementation of the present invention, a single master device (e.g., master 246) controls tens, hundreds, or even thousands of slave devices.

Because of this asymmetric relationship between master and slave devices (1-N, where N may be a very large number) and the requirement that communication occur in real time, an interface circuit 225(295) is provided that includes ingress filter hardware 106. The ingress filter 106 (and its accompanying logic) in conjunction with the ingress classifier 232 implement hardware decisions for real-time forwarding and processing. In the present example, all information that must be read in order for forwarding and receiving decisions regarding a packet to occur is located in the first 32 bytes in the packet. Once the first 32 bytes of the packet are read, PRU _0219 can look for a header and an extra header depending on the protocol to which the packet conforms. The header may be looked up in real time (e.g., in filter database 251). Thus, once the first 32 bytes of the packet have been received by interface circuitry 225(295), interface circuitry 225(295) has sufficient information to determine whether to forward the packet or whether to receive the packet, as described above. It should be noted that the 32-byte header size described is an example header size. The systems 100, 200 of the present invention may be configured to work with packets having other header sizes.

As described, the (packet) reception process is completed in real time. In an implementation of the present invention, AUX _ PRU _ 0205, PRU _0219, and interface circuitry 225(295) are programmable and configured such that all packet processing is fully deterministic. Receiving 32 bytes of header information is done in interface circuitry 225(295) at 64 gigabits/second, which enables interface circuitry 225(295) to send 32 bytes of information forward or receive 32 bytes of information. The filter 106 of the present invention is very flexible as long as the filter can be moved to filter a particular portion of a packet. If there are multiple subpackets, filter 106 may be reloaded as needed through interface circuitry 225 (295). Additionally, the interface circuitry 225(295) may apply a mask to set a packet range or address in a packet and/or sub-packet. By grouping packets using greater and lesser operations, interface circuitry 225(295) may determine, for example, that a packet will be received when the packet has an address number from 15 to 29. In some examples, a binary mask may be applied such that subpackets having addresses starting with even numbers (e.g., 8-7) are forwarded and subpackets having addresses starting with odd numbers are not forwarded (at least not immediately). Therefore, it may be advantageous to have more/less operations for sub-packet address classification. In some examples, different filters (e.g., 106 and 107) may be operatively combined with other components (e.g., MAC 206(266), 220(290)) to further process packets by their MAC addresses.

As noted, multiple filters may be combined to cause the interface circuitry 225(295) to make the switching determination. Additional logic may also be applied. For example, the classifier 232 may classify packets and apply classification dependent logic, such as 'for packet type a, if conditions one, two, and three are true, the packet will be received'. As another example, where a packet is classified as type B, if condition one is true and condition two is false, the packet will be discarded. The subsystem 200 may be configured such that the condition may also include a time window in which the packet is received. For example, interface circuitry 225(295) may determine that at a particular point in time, interface circuitry 225(295) will only allow forwarding of very important (higher priority) input/output data. The interface circuitry 225(295) may be configured such that a set of filter combinations will be applied during designated periods (e.g., after predetermined events have occurred), while during other times all types of data traffic may be allowed. This described programmability is advantageous in an industrial environment because industrial communications operate based on hard time windows (as opposed to, for example, teleconferencing).

In an example of the present invention, multiple hardware filters may be combined with the rate filter 107 so that data packets may also be classified according to rate. The filter 106, 107 and hardware 220(290) operations used may be performed incrementally. Packets may be filtered using any combination of content, time, and rate (all in real time). A given filter 106 may be restarted multiple times for a packet. The filter 106 may have a starting address whose value is determined based at least in part on the content and/or content type of a given packet/subpacket.

In at least one example of the invention, the interface circuitry 225(295) is configured to automatically detect whether a packet contains a Virtual Local Area Network (VLAN) tag. Some ethernet packets have a tag for a tag byte in the middle of the packet or at the trailing MAC address. It may happen that: if a filter is applied to data trailing a MAC address, the MAC address will be undesirably shifted by four bytes. The exemplary interface circuit 225(295) of the present invention solves this problem by: automatically detects whether a packet has a VLAN tag and, if the packet does contain a VLAN tag, re-initiates the associated filter 106 using the location of the VLAN tag as the starting address. Thereafter, the interface circuit 225(295) makes the determination (e.g., whether to receive OR discard the packet) using combinational logic, which may involve any suitable combination of AND, OR, AND filter flags. In one or more examples of this disclosure, rate counter 107, which may be a hardware rate counter, determines the rate depending on the type of traffic in question and the predetermined window of time for the type of packet. Thus, there may be a particular time for high priority packets and a different time for non-real time packets, and different filters may be applied depending on the situation. In some examples, the filter 106 that produces an immediate result during receive time (immediate) processing will forward the packet in question regardless of the length of the packet. This operational capability is in sharp contrast to conventional ethernet, where packets are first received, one or more look-up tables are consulted, and then finally a handover decision is made. In some examples of the invention, the packet size is predetermined and communication occurs at a fixed rate per packet. In other examples, information about the packet length is contained within the header of the packet. In either case, the packet length is determined in real-time, hard-to-real-time.

At least one technical benefit of the architecture described in this disclosure is that the architecture enables handover/forwarding determinations to be completed within a single microsecond, even for packets having a length of up to twelve microseconds. The time and data rate based combinatorial logic of the interface circuitry 225(295) enables the classification engine 232 to perform in a robust manner. The ability of the subsystem 200 to reinitiate the filter 106 to apply the filter 106 multiple times in a packet enhances the ability of the subsystem 200 to make packet switching decisions in real time. In an exemplary embodiment, the length of the filter 106 is limited. If the packet is longer than the filter, then the filter 106 will need to be reloaded. If the Ethernet packet contains sub-packets, the filter 106 may be reused for multiple locations with a single packet. In some examples, the subpackets will each have their own address. For example, if three subpackets are included, the address filter 106 may be loaded three times to apply the same address filter 106 to each subpacket. PRU _0219 writes the data to TX _ L2 via interface 252(255), and the data then exits slice _0201 along communication path 253. The described real-time processing supports the resource availability and allocation management described below.

As noted, aspects of the present invention and components of the ICSS 200 relate to motor control. Application site communication may be used to communicate motor control signals. In an industrial environment, devices and components may communicate input/output data between each other according to one or more ethernet protocols. In the case of motor driving and motor control, there is always an application side of this input/output data. The motor may be driven by a plurality of pulse width modulated signals. Pulse width modulation is used to control motor applications in the context of robots, machine tools, and conveyor belts, for example. Proper pulse width modulation of mechanical devices like these is an important factor in maintaining safe operation in places such as factories and work sites. One aspect of security is device error mitigation. Another aspect of security is device error minimization. One way to mitigate and minimize device errors is to understand the causes and effects of past errors. One or more examples of the present disclosure are directed to identifying and tracking the source of errors (sometimes referred to as 'glitches') and tracking when glitches occur. Examples of the invention include systems and methods for safely controlling a pulse width modulation drive (such as a motor) in the presence of transient fluctuations, thereby mitigating any damage that may be caused by such transient fluctuations.

As noted, a pulse width modulator (e.g., PWM244 in fig. 2B) controls the motor. In an example of the present invention, PWM drives a motor at a particular speed and a particular torque by controlling the motor using a pulse width modulated signal. In industrial applications, there are typically six pulse width modulated signals used to drive a three-phase electric machine (e.g., a three-phase motor). In addition, there is a signal, called a trip signal, that is sent to the PWM to cause the PWM to shut down the motor power stage. As explained previously, the pulse width modulated signal is converted to a high power signal to drive the high power motor. A trip signal may arrive from the control unit to the power unit, e.g. PWM.

One way to enhance safety in environments involving industrial applications, such as robots, server drives, Computer Numerical Control (CNC), is to be able to quickly (and safely) shut down the power levels of such applications. Examples of power stages within the present invention are metal oxide field effect transformers (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs), and other electronic devices that drive motors.

A duty cycle or power cycle is the portion of a period (T) in which a signal or system is active. The period is the time it takes for the signal to complete a turn-on/off cycle. The duty cycle (D) is the ratio of the Pulse Width (PW) (pulse active time) to the period (T). The duty cycle (D) may be defined according to the following formula: d equals PW/T. The nature of the duty cycle of PWM means that for a three-phase motor, up to six of those pulse width modulated signals are necessary for control. Within the present invention, the trip signal is a signal sent by the pulse width modulator 244 to cut off the power stage in the event of an error condition.

There are many situations in which it may be necessary to stop the power generation hardware. The trip signal indicates that this condition exists. For example, a fault condition, such as a short circuit, may exist in the power stage itself. A trip signal may be issued because the temperature in the assembly is too high or there is too much current flowing. A trip signal may be issued because one or more of the motors are in an incorrect position, or because the motors are running at the wrong speed.

In some industrial environments, there may be a significant amount of electromagnetic interference that may affect the signal output of an electronic device. The alteration of the signal output may be interpreted as indicating the presence of glitches and errors in the component from which the signal output is derived. Sometimes, this can cause false positives in error detection. Furthermore, not all false detections may require power stage shutdown. As will be described in greater detail below, examples of the present invention include systems and methods for filtering a glitch indication signal. In some embodiments, glitch filtering is performed by one or more logic blocks configured to distinguish between a PTOS that requires power stage shutdown and a PTOS that does not require power stage shutdown. In some instances, combining multiple PTOS into a single PTOS is an aspect of glitch filtering.

Aspects of the present invention relate to capturing data for diagnostic purposes. For example, if a fault condition (glitch) is detected once for a component, it may be appropriate to ignore the fault condition, while if the same fault condition is detected immediately three times, it may be appropriate to investigate the cause of the glitch. In one or more examples of the invention, the PTOS is recorded and summarized. The PTOS data from the different information sources is fed to the glitch filter (which may be a state machine) in this manner in order to improve the operating accuracy of the glitch filter over time. In some examples, the filter logic may be reprogrammed based on the described glitch analysis. In some examples, the glitch data is analyzed and fed back to the glitch filter in real-time.

The signal between the PWM and the motor driven by the PWM is motor side communication. The motor side communication is done according to a motor side communication protocol that is not an ethernet protocol. The motor side communication is serial based, but it is a real time communication of position data to the control unit and then the motor current, these are bit streams typically from an analog/digital computer using a delta-sigma method 216, with data about the current value contained within the bit stream. Some motor-side communications are protocol-based communications (like position feedback signals), while other motor-side communications (like motor currents) are sent in a bit stream. The pulse width modulated signal is an example of a digital control signal.

In at least one example of the present disclosure, a filter state machine receives a signal indicating that one or more events have occurred. The filter state machine may have a static trip configuration or a dynamic trip configuration. A filter operating in a static configuration (or mode) will issue a trip signal when a particular event (e.g., a glitch) is detected. A filter state machine operating in a dynamic mode may detect a pattern of events. For example, if the same error is detected multiple times (depending on the severity of the error) in a particular cycle, the dynamically configured filter may issue a trip signal.

In at least one example of the present disclosure, a transient surge filter may be programmed to issue a Trip Event Indication Signal (TEIS) depending on what event signal the filter receives. Signals (412A, 422) input to the glitch filter (412, 417) through logic block (414) or amplifier (417A) or other component may be subject to impulse noise, where the signals briefly switch from one state to another and then return. For example, from inactive to active, and then quickly return to inactive. The glitch filter (412, 417) will remove short term state changes in the inactive input signal (e.g., low) and ensure that the output signal from the filter remains inactive (does not switch to the incoming state), assuming the active input signal is within a predefined glitch width.

In one or more examples, the transient fluctuation filter has an active state and a reset state. When the ICSS 200 is powered on, the components of the ICSS need to be brought into a defined reset state. After the reset state, the component (e.g., motor application) may enter an active state. The timing of the reset state is controlled by the state machine. The state machine 421 may be programmed for a single detection. When programmed for a single detection, once the state machine (421) determines that an event or combination of events worth the trip signal has occurred (as long as the state machine receives a valid and unmasked (active) trip input (411-420)), and as a result outputs the trip signal (becomes a predefined value, becomes active), the output signal (408) will remain active (also referred to as 'latched') even though the input trip signal returns to the inactive state.

The state machine may be programmed such that the detection and trip output settings are reset with the cycle time of the period of the motor control cycle. In this cycle-by-cycle mode, when the inputs (411-420) disappear, the trip signal (408) will end and the PWM (244) will resume normal operation. A single test helps to ensure that the power stage is completely turned off and the motor current goes to zero (until reset externally, though manually). Single detection is better suited to critical fault conditions like short circuit detection or positional error faults. Note that in some examples, state machine (421) may be configured to handle some trip inputs in a single pass, while for other trip inputs, the state machine will stop issuing trip signals (408) when these other inputs become inactive in the next cycle. Thus, the ICSS may be tailored to the needs of the user. In some embodiments, the state machine may scan for a glitch within one or more times 31.25 microseconds. In at least one embodiment, the glitch filter scans the glitch signal at a rate of 60 kilohertz. In at least one embodiment, the glitch filter scans the glitch signal at a rate of 80 kilohertz.

Unlike in conventional systems, the ICSS 200 manages the protection source and all aspects of pulse width modulated power control. In one or more embodiments, the transient fluctuation filter assembly of the ICSS 200 is highly customizable in that it is programmable and configurable to operate in varying environments. The transient surge filter also has low latency, despite its versatility and programmability. In one or more examples, information is moved through the ICSS 200 at five nanosecond intervals. In some examples, the location information (regarding external devices, such as motors) is communicated through one or more communication interfaces (e.g., 270, 271, and 272 in fig. 2B). This location information may be real-time information. In some examples, because the location information is received in real-time, if the location information indicates that an error exists, information regarding the positioning error is transmitted to a hardware state machine. If the hardware state machine is configured, for example, to trigger a position error, the hardware state machine will immediately output a trip signal. In at least one example of the ICSS 200, there is a combination of hardware state machines and computational logic that resides in the real-time processing and communications domain of the ICSS 200. This arrangement differs from conventional solutions in which communication regarding control functions is controlled by an external ASIC or SPGA and information regarding the control functions is passed to the control PRU through an interface.

In at least one example of the present invention, low latency in the ICSS 200 is enhanced by integrating all trip inputs into one hardware device. Management of all trip inputs occurs in a single hardware state machine (421).

Fig. 3 illustrates aspects of pulse width generation 301 according to an example of the invention. In the example shown in fig. 3, nine complementary pulse width modulated outputs are matched with three motors 311. The pulse width modulated signal 308 and the pulse width modulated signal 309 are generated by a Pulse Width Modulator (PWM) 244. For example, the 'x' suffix in the 'PWMx' indicator (308) and the '/PWMx' indicator (309) reflects the fact that: more than one pair of pulse width modulated signals (272) are used to drive the three-phase motor. The control signal 305 and the comparator signal 306 are generated by the IEP 0241. The control signal 305 and the comparator signal 306 go to the PWM 244. Also shown is a trip output signal 307(425) that goes to the PWM244 when a particular type of event occurs, as will be explained in more detail in the discussion of fig. 4A and 4B. The control signal 305 and the PWM signal 308 and the PWM signal 309 are generated by the PWM 244. The location event indicator 302 is an indication that an error event has occurred. The location event indicator 303 is an indication that another error event has occurred. The PRU 219 and peripheral interface 217 form a feedback system that tracks the position data of the motor and generates a trip event five indication signal (420) when a position error is detected. The sawtooth signal 305 is output from the match 0 register (402). Also shown in fig. 3 is period 304 of signal 305. The trip event indicator 307 indicates that the external output pin 432 has sent a signal (TEIS-2) indicating that a trip event-2 has occurred. Pin 432 is connected to PWM 244. The delta-sigma current measurement 312 is generated by sigma-delta 216 and the PRU of fig. 2.

Fig. 4A illustrates a logic configuration 400 of a pulse width modulation monitor and controller of an exemplary ICSS (200). Fig. 4B illustrates a trip signal logic circuit 421 of the ICSS (200) interacting with the logic configuration 400. As shown in fig. 4B and as discussed above, each trip signal logic circuit 421 may generate a single trip output signal 425. The value of the selector signal 426 specifies whether the trip signal logic circuit 421 operates in a single-shot mode or, alternatively, in a cycle-by-cycle mode, as explained above. In the example illustrated in fig. 4B, the trip signal logic circuit 421 is configured to track five trip input signals each corresponding to a trip event.

Gate 414 shown in fig. 4A monitors PWM output signal 308 of PWM terminal 430 and PWM output signal 309 of PWM terminal 431. If both signals 308 and 309 are active (high), then gate 414 outputs an event indication signal (EIS-1)412A to the glitch filter 412. Depending on how the transient fluctuation filter is configured, when the transient fluctuation filter 412 receives the EIS-1412A, the transient fluctuation filter 412 sends a trip event indication signal (TEIS-1)411 to the trip signal logic circuit 421. As depicted, the PWM (244) produces nine complementary pulse width modulated outputs for each group of three motors. Based on the EIS 412A from gate 414, TEIS-1411 monitors the pulse width modulated signal generated by PWM (244) to ensure that the pulse width modulated signals 308, 309 are complementary to each other (are the same phase, do not activate both transistors simultaneously, etc.). The glitch filter 412 may be configured using a configuration memory mapped register 413 to filter or block EIS-1412A from gate 414 (which does not meet a particular threshold, such as when the trip signal is too short for a while). Transient fluctuations such as these are reflected in small peaks of 1 or 0, which are typically caused by external electromagnetic interference.

Event indication signal two (EIS-2)432A (shown in fig. 4A) corresponds to a signal from an external source 432. For example, an external power pad may be configured to send an EIS-2432A if the temperature of the power pad exceeds a particular threshold. As was the case for TEIS-1411, a glitch filter 417 is interposed between the external source 432 and the input 415A of TEIS-2415 (corresponding to a trip event-2), which may be configured 416 to filter error signals (e.g., EIS-2432A) indicative of false positives. The glitch filter 417 sends only the trip event indication signal (TEIS-2)415 to the trip signal logic circuit 421 if the EIS-2432A from the external source 432 meets certain customizable criteria. In practice, filters 412 and 417 would be programmed based on the needs of the environment in which ICSS (200) operates. For example, if a signal error such as a jitter or ringing occurs while the robotic arm is being used to paint, such a signal error is more likely to indicate a real fault than if it occurred in a welding environment (where electromagnetic interference is not uncommon). The programmability of the filters 412, 417 allows fine tuning of the sensitivity of error detection in the ICSS. Trip event three indication signal 418 indicates that sigma delta (216) has detected a short circuit. Trip event indication signal number four 419 indicates that an overcurrent has been detected in one or more motors controlled by ICSS (200), for example. Trip event indication signal five (TEIS-5)420 is based on feedback received by PRU 219 (using a serial-based protocol). If the PRU determines that the external component controlled by ICSS (200) is in an incorrect position, PRU 219 sends TEIS-5420 to trip signal logic circuit 421. The trip signal logic circuit 421 may be configured 427 to mask one or more trip input signals, which means the trip signal logic circuit 421 may be configured to send a trip output signal 425, e.g., that will cause the motor to shut down (only for the desired trip event combination).

The trip capture block 401, comparator 0403, counter 403, drift compensation input 404, comparator 1405 and comparator 2409 illustrated in fig. 4A are components of IEP0 (241). Hit signal 405A is sent from comparator 405 of IEP 0241 to input PWM1 of PWM 244. Output buffer 407 is interposed between IEP0 and PWM 244. Buffer flip-flop 406, output buffer 407, buffer 410, glitch filter 412, configuration input 413, gate 414, trip event two input 415A, glitch filter configuration input 416, buffer 417, and trip signal logic circuit 421 are components of PWM 244. Output pins 430 and 431 are output pins of PWM 244. Signal 308 emanates from output pin 430 and signal 309 emanates from output pin 431. The comparator 1405 compares its programmed value (cmp _1) with the value in the counter 403 (IEP _ counter). If the value in comparator 1405 equals the value in counter 403, comparator 1 will issue hit signal 405A.

In at least one embodiment, when comparator 1405 sends hit signal 405A (see 306 of fig. 3) to PWM244, the hit signal forms a rising edge in signal 308. Similarly, when comparator 2409 sends hit signal 409A to PWM244, the hit signal forms a rising edge in signal 309. The IEP counter 403 counts the errors and the number of errors detected is represented by the rising edge of the sawtooth waveform 305. Like comparator 1405, comparator 2409 compares its programmed cycle value (cmp _0) with the value in IEP counter 403 (IEP _ counter). When the number of errors in the IEP counter 403 reaches the value in the comparator 402, the IEP counter 403 is reset to zero. (if the values in comparator 2409 and IEP counter 403 are the same, then the value of IEP counter 403 is reset to zero.)

In at least one example of the present disclosure, it may be beneficial to synchronize the pulse width modulated signal from the PWM244 with other periods, such as communication cycles. As shown in fig. 4A, the drift compensation 404 is used to shift the output signals 308, 309 from the PWM244 to keep the output signals in phase with other components, such as an external clock. The PWM244 has an active mode 406A and an initialization mode 406B; the input 406 selects the operating mode 406A, 406B of the PWM 244. During the initialization mode 406B, the pulse width modulated output signal 272 is set to either a high impedance H or a low impedance L. If the PWM244 receives a hit signal 405A at the input buffer 407 when the PWM244 is in the active mode 406A, the PWM244 will output 272 either a high impedance signal H or a low impedance signal L or toggle the output 430(272) from one (current) output signal (H or L) to the other, depending on how the input buffer 407 is programmed. In one or more examples, the input buffer 407 may be easily reprogrammed as needed by the user and/or the environment in which the ICSS 200 operates. The trip signal 408 is transmitted by the trip signal logic circuit 421 (when a trip condition is determined by the trip signal logic circuit 421) and enters the input buffer 407, as shown. When the PWM244 is in the active mode 406A, the trip signal 408 will cause the output 430 of the PWM244 to be high impedance (Z), high (H), or low (L), depending on how the buffer 407 is configured. The trip signal 408 will negate the hit signal 405A. Comparator-2409 has the same function as comparator-1, but for the negated pulse width modulated signal 309. Comparator-2409 of IEP 0241 sends hit signal 409A to filter 410 when approved, and filter 410 outputs hit signal 409A to output 431 of PWM244 via signal 410A, depending on the filter's settings. Signal 410A also goes to gate 414. If both signals 410A and 407A are active, then gate 414 will generate an EIS at 412 that will trigger a TEIS 411 at the glitch filter 412 that will cause the trip logic 421 to issue the trip signal 408 that will in turn cause the PWM (244) to enter the inactive state. The condition that both (complementary) PWM signals PWM1 and/PWM 1 are active is catastrophic because this will turn on both the high-side and low-side switches in the power stage and create a short circuit therein. This condition is called shoot-through, which should be avoided because of possible damage or injury that may result from a short circuit in the power stage.

The filter 410 is controlled by a state machine (421), as will be explained in more detail below. During a first state (initialization) of the filter 410, the signal 410A is an initialization signal, during a second (active) state, the signal 410A corresponds to the hit signal 409A, and during a third (error) state, the signal 410A is set according to the trip signal 408.

TEIS-1411 corresponds to an error condition in which both output signal 308 from PWM244 terminal 430 and output signal 309 from PWM244 are active (high). If both the output signal 308 from the terminal 430 of the PWM244 and the output signal 309 from the PWM244 are in an active state (e.g., both high), the power level of the motor being driven by the PWM244 may be damaged (due to a short circuit). Gate 414 monitors PWM output terminal 430 and PWM output terminal 431. If gate 414 determines that PWM output terminal 430 and PWM output terminal 431 have the same high output, which means that a trip event has occurred, in this case, gate 414 sends EIS-1412A to glitch filter 412. (not an error condition when both signal 308 and signal 309 are low.) if the transient fluctuation filter 412 determines that the EIS-1412A corresponds to a true error or fault condition rather than a transient fluctuation, the transient fluctuation filter 412 of fig. 4A sends TEIS-1411 to the trip signal logic circuit 421 of fig. 4B.

The filter 412 may be configured, for example, to ignore the EIS-1412A when the EIS-1412A falls below a threshold. For example, in robot and machine environments, if there is a minor trip, it may be due to electromagnetic interference (glitches) in the environment, rather than a real error condition that warrants shutting off the power stage of the device being driven by PWM 244. Again, the sensitivity of the PWM244 to glitches can be adjusted by configuring the glitch filter 412 (and glitch filter 417). The transient fluctuation filter 412 may be configured 413 to mask (or mask) EIS-1412A shorter than a threshold period; the threshold period may be set to 10 nanoseconds or 100 nanoseconds, and any period between 10 nanoseconds and 100 nanoseconds. The configuration memory mapped register stores a threshold value for the glitch filter 412. The glitch filter 417 may be configured using the configuration memory mapped register 416 to mask out (or mask) event indication signals (e.g., EIS-2432A) that are shorter than a threshold period; the threshold period may be set to 10 nanoseconds or 100 nanoseconds, and any period between 10 nanoseconds and 100 nanoseconds. The configuration memory map register 416 stores a threshold value for the glitch filter 417.

In at least one example, the trip signal logic circuit 421 can receive five trip signals. TEIS-1411 is from the transient fluctuation filter 412 and indicates that the output terminals 430, 431 of the PWM244 are high at the same time. The trip event-1 input 411a carries the designation '[ 2..0 ]', since the three-phase motor is driven by three pairs of pulse width modulated signals 308, 309, 430, 431. Trip event indication signal No. two 415 indicates that there is a fault in the external component 432. Trip event # three indicates that signal 418 is from PRU 219 and sigma delta accelerator 216 and indicates that there is a short circuit in SoC 246, of which ICSS 200 is a component. The trip event # four indication signal 419 is from the PRU 219 and the sigma delta accelerator 216 and indicates that there is an over current in the SoC 246, of which the ICSS 200 is a component. The trip event indication signal five 420 comes from the PRU 219 and the peripheral interface 217 and may indicate that the device being controlled by the ICSS 200 is in an incorrect position. The mask input 427 and compare-0 input 426 are used to configure the trip signal logic circuit 421.

FIG. 5 illustrates a system 500 in accordance with an example of the invention. Block 501 highlights aspects of fig. 2A-2C. Controlling PRU-1502 corresponds to PRU 215 of fig. 2A. Interface PRU-1503 corresponds to PRU 219 of fig. 2A. Control PRU-2504 corresponds to PRU 265 of fig. 2C. Interface PRU-2503 corresponds to PRU 289 of fig. 2C. IEP timer-1506 corresponds to IEP 0241 of fig. 2B. IEP timer-2 corresponds to IEP 1273 of fig. 2B. The system 500(200) includes four multiplication units 508. The system 500 includes a combination 509 of broadside random access memory and triangular lookup tables. The task manager 510 corresponds to the task managers 209 and 223 of FIG. 2A and the task managers 269 and 293 of FIG. 2C. The interrupt controller 511 corresponds to the interrupt controller 236 of fig. 2B. PWM block-1512 and PWM block-2513 illustrate the following facts: ICSS 200 includes a plurality of pulse width modulators like PWM244 of fig. 2B. The delta-sigma block 514 illustrates the following: the PRU 219 and accelerator 216 are capable of generating nine sigma-delta signals (418, 419). The delta-sigma block 513 illustrates the following: the PRU 219 and accelerator 216 of fig. 2A are each capable of generating nine sigma-delta error signals (418, 419). The delta-sigma block 514 illustrates the fact that: PRU 265 and accelerator 286 of fig. 2C are also each capable of generating nine sigma-delta error signals (418, 419). Encoder block 516 illustrates peripheral interface 217 utilizing three encoders for motor position measurement. Likewise, encoder block 517 illustrates that peripheral interface 287 utilizes three encoders for motor position measurement.

FIG. 6 is a state diagram 600 showing the relationship of possible states of buffer 407 of FIG. 4A. Upon power up, buffer 407 enters into initialization state 601. When buffer 407 is in initialization state 601, output 407A of buffer 407 may be high impedance (Z), high (H), or low (L). After initialization 601 of buffer 407 is complete, buffer 407 may enter an active (operating) state 602. When buffer 407 is in active state 602, if buffer 407 receives hit signal 405A, then hit signal 405A will cause output 407A of buffer 407 to be high (H), low (L), or hit signal 405A will cause the value of output signal 407A to be toggled (if output 407A is high, output 407A will switch to low; if output 407A is low, output 407A will switch to high). Whether buffer 407 is in the initialization state 601 or in the active state 602, when buffer 407 receives the trip signal 408, the buffer will be placed in the safe mode 603. In the safe mode, the value of output signal 407A will be high impedance (Z), high (H), or low (L), depending on how buffer 407 is programmed. Note again that buffer 407 may be reconfigured based on the needs of the user.

Fig. 7 is a block diagram of a state machine 700(421) according to an example of the invention. In fig. 7, block 701 represents the inputs (411-420) of the state machine (421), the trip input being analyzed by the state machine 700 and causing the state machine 700 to send the trip signal 703 to the input-output port 702, which includes the buffer 407 and the output terminal 430 of the PWM 244. Block 704 illustrates the configurable logic of the state machine 700 that determines how the state machine 700 will process the existing trip signal 703 depending on whether the state machine 700 is in single-shot mode or loop-by-loop mode, as previously described.

Although SoC is primarily used throughout the disclosure as an example type of chip, it will be appreciated that the techniques described herein may be applied to design other types of IC chips. For example, such IC chips may include general purpose or Application Specific (ASIC) processors, Field Programmable Gate Arrays (FPGAs), Graphics Processors (GPUs), Digital Signal Processors (DSPs), system-on-a-chip (SoC) processors, microcontrollers, and/or related chipsets based on x86, RISC, or other architecture.

Certain terms are used throughout the description and claims to refer to particular system components. As one skilled in the art will appreciate, different parts may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the present disclosure and claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to …". Also, the term "coupled" is intended to mean either indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. The recitation "based on" is intended to mean "based, at least in part, on". Thus, if X is based on Y, X may be in terms of Y and any number of other factors.

The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims (20)

1. A control system, comprising:

a power stage;

a pulse width modulator coupled to the power stage, the pulse width modulator configured to cut off the power stage when the pulse width modulator receives a trip signal;

a processor coupled to the pulse width modulator;

a logic circuit coupled to the pulse width modulator and the processor, the logic circuit comprising:

a first interface comprising a plurality of inputs, wherein the plurality of inputs comprises:

a first input configured to receive a first trip event indication signal originating at the pulse width modulator;

a second input configurable to receive a second trip event indication signal originating at an electronic device releasably coupled to the second input at a connection port; and

a third input configured to receive a third trip event indication signal from the processor; and

a second interface, comprising:

a first selection input configured to receive a first selection; and

a second selection input configured to receive a second selection,

wherein the logic circuit is configured to send the trip signal to the pulse width modulator when the logic circuit receives at least one of the three trip event indication signals.

2. The control system of claim 1, wherein the plurality of inputs further comprises:

a fourth input configured to receive a fourth trip event indication signal from the processor; and

a fifth input configured to receive a fifth trip event indication signal from the processor.

3. The control system of claim 2, wherein:

the third trip event indication signal corresponds to a short circuit condition determined by the processor; and is

The fourth trip event indication signal corresponds to an overcurrent condition determined by the processor.

4. The control system of claim 3, wherein the fifth trip event indication signal corresponds to a position error condition determined by the processor indicating that the power stage is in an incorrect position.

5. The control system of claim 1, further comprising a first filter coupled between the pulse width modulator and the first input, wherein the first filter is configured to:

receiving a first error signal from the pulse width modulator, the first error signal having a duration;

determining that the duration of the first trip event indication signal exceeds a first threshold;

sending the first trip event indication signal to the logic circuit in response to the determination that the duration of the first trip event indication signal exceeds the first threshold.

6. The control system of claim 5, wherein the pulse width modulator drives the power stage using three pairs of pulse width modulation terminals, and the first error signal indicates an error condition in which both terminals of at least one of the three pairs of pulse width modulation terminals transmit high signals simultaneously.

7. The control system of claim 6, further comprising a second filter coupled between the connection port and the second input, wherein the second filter is configured to:

receiving a second error signal from a connection port, the second error signal having a duration;

determining that the duration of the second trip event indication signal exceeds a second threshold;

sending the second trip event indication signal to the logic circuit in response to the determination that the second trip event indication signal exceeds the second threshold.

8. The control system of claim 7, wherein the first threshold is a first length of time greater than or equal to 10 nanoseconds and less than or equal to 100 nanoseconds and the second threshold is a second length of time greater than or equal to 10 nanoseconds and less than or equal to 100 nanoseconds.

9. The control system of claim 1, wherein the control system is a component of a system-on-a-chip.

10. A logic circuit coupled to a pulse width modulator, the logic circuit configured to receive a plurality of inputs, the plurality of inputs comprising:

a first input corresponding to a first signal originating at the pulse width modulator;

a second input corresponding to a second signal originating at the electronic device; and

a third input corresponding to a third signal originating at the one or more processors;

wherein the logic circuit is configured to controllably select which of the plurality of inputs to output to a pulse width modulator as a trip signal to cause the pulse width modulator to shut down a power stage driven by the pulse width modulator.

11. The logic circuit of claim 10, wherein the plurality of inputs further comprises:

a fourth input corresponding to a fourth signal originating at the processor; and

a fifth input corresponding to a fifth signal originating at the processor.

12. The logic circuit of claim 11, wherein:

the third signal corresponds to a short circuit condition determined by the processor; and is

The fourth signal corresponds to an over-current condition determined by the processor.

13. The logic circuit of claim 12, wherein the fifth signal corresponds to a position error condition determined by the processor, the position error condition indicating that the power stage is in an incorrect position.

14. A method for managing a trip signal for a pulse width modulator, the method comprising:

driving the power stage using a pulse width modulator;

receiving a first input at a logic circuit, the first input corresponding to a first trip event indication signal originating at the pulse width modulator;

receiving a second input at the logic circuit, the second input corresponding to a second trip event indication signal originating at an electronic device releasably coupled to the logic circuit at a port;

receiving a third input corresponding to a third trip event indication signal from the processor;

selecting, by the logic circuit, which input to output to the pulse width modulator as a trip signal to cause the pulse width modulator to shut down a power stage driven by the pulse width modulator, wherein selecting comprises selecting from a plurality of inputs including the first input, the second input, and the third input; and

outputting the selected input from the logic circuit.

15. The method of claim 14, the method further comprising:

receiving a fourth input at the logic circuit, the fourth input corresponding to a fourth trip event indication signal from the processor; and

receiving a fifth input at the logic circuit, the fifth input configured to receive a fifth trip event indication signal from the processor,

wherein selecting which input to output to the pulse width modulator at the logic circuit as a trip signal to cause the pulse width modulator to shut down a power stage driven by the pulse width modulator further comprises selecting from a plurality of inputs, wherein the plurality of inputs comprises the first input, the second input, the third input, and the fourth input.

16. The method of claim 15, further comprising:

determining, using the processor, that a short circuit condition exists; and

determining, using the processor, that an over-current condition exists,

wherein the third input corresponds to the short circuit condition determined by the processor; and is

The fourth input corresponds to the over-current condition determined by the processor.

17. The method of claim 16, further comprising:

determining a location error condition using the processor, an

Wherein the fifth trip event indication signal corresponds to the position error condition determined by the processor indicating that the power stage is in an incorrect position.

18. The method of claim 14, further comprising:

receiving, at a first filter, a first error signal from the pulse width modulator, the first error signal having a duration;

determining, at the filter, that the duration of the first error signal exceeds a first threshold;

sending the first error signal from the first filter to the logic circuit in response to the determination that the duration of the first trip event indication signal exceeds the first threshold.

19. The method of claim 18, wherein driving the power stage further comprises driving the power stage using three pairs of pulse width modulation terminals, and wherein the first error signal indicates an error condition in which both terminals of at least one of the three pairs of pulse width modulation terminals transmit high signals simultaneously.

20. The method of claim 17, further comprising:

receiving, at a second filter, a second trip event indication signal from the port, the second trip event indication signal having a duration;

determining, at the second filter, that the duration of the second trip event indication signal exceeds a second threshold; and

sending the second trip event indication signal from a logic circuit to the pulse width modulator to the logic circuit in response to the determination that the second trip event indication signal exceeds the second threshold.

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