CN111538472B

CN111538472B - Positt floating point number arithmetic processor and arithmetic processing system

Info

Publication number: CN111538472B
Application number: CN202010346033.7A
Authority: CN
Inventors: 梁峰; 吴斌; 张国和; 孙齐伟
Original assignee: Xian Jiaotong University
Current assignee: Xian Jiaotong University
Priority date: 2020-04-27
Filing date: 2020-04-27
Publication date: 2022-11-04
Anticipated expiration: 2040-04-27
Also published as: CN111538472A

Abstract

The application provides an operation processor and an operation processing system of Posit floating point numbers, and relates to the technical field of computers. The intermediate data in the complementary form obtained by the decoding circuit is directly subjected to addition, subtraction, multiplication and FMA operation to obtain an operation result represented by the intermediate data in the complementary form, and the operation result represented by the intermediate data in the complementary form is directly input into the encoding circuit, so that the encoding circuit directly converts the intermediate data in the complementary form into Posit floating point numbers. The mutual conversion of the original code and the complement code in the operation circuit is avoided, the logic of the operation circuit is simplified, and the area and the power consumption of the operation circuit are reduced.

Description

Positt floating point number operation processor and operation processing system

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to an arithmetic processor and an arithmetic processing system for a Posit floating-point number.

Background

Floating point number is a commonly used data representation method in the fields of scientific computing and high-performance computing, and particularly, in the field of high precision requirements on the computed results, a large number of floating point numbers are used for data processing, such as the fields of automatic driving, aerospace and mechanical computing.

Compared with the floating point number of the IEEE 754 standard, the floating point number of the Posit standard has higher flexibility, the sampling distribution of the Posit floating point number on real numbers is related to a sigmoid function, and the sigmoid function is an activation function commonly used in machine learning, so that the Posit floating point number is used for machine learning, and the data processing efficiency of a computer is higher.

At present, a decoding circuit is generally used for converting Posit floating point numbers participating in operation into original codes, the original codes are input into an operation circuit for operation, the operation circuit judges whether the Posit floating point numbers are negative numbers or not according to the original codes for convenient operation, then the original codes of the negative Posit floating point numbers are unified into a complementary code form, after an operation result in the complementary code form is obtained, the operation result in the complementary code form is converted into the original codes, the whole operation process needs to repeatedly perform conversion from the original codes to the complementary codes and conversion from the complementary codes to the original codes, and each operation node needs to judge whether the Posit floating point numbers are positive or negative, so that the whole operation logic on the Posit floating point numbers is very complex and tedious, and the circuit area of the operation circuit is too large.

Disclosure of Invention

The embodiment of the application provides an operation processor and an operation processing system for Posit floating point numbers, wherein the operation processor and the operation processing system directly perform addition, subtraction and multiplication operations on intermediate data in a complementary code form acquired from a decoding circuit to obtain an operation result represented by the intermediate data in the complementary code form, and directly input the operation result represented by the intermediate data in the complementary code form into an encoding circuit, so that the encoding circuit directly converts the intermediate data in the complementary code form into Posit floating point numbers. The mutual conversion of the original code and the complement code in the operation circuit is avoided, the logic of the operation circuit is simplified, and the area and the power consumption of the operation circuit are reduced.

A first aspect of the embodiments of the present application provides an arithmetic processor for a Posit floating-point number, the arithmetic processor including: the acquisition module is used for acquiring a plurality of complementary intermediate data which are output by the decoding circuit and participate in target operation; the intermediate data is obtained by decoding Posit floating point numbers participating in operation by the decoding circuit according to a calculation instruction of a CPU; the intermediate data comprises at least the following fields: a sign field, an exponent field, and a mantissa field;

a mantissa field processing module, configured to obtain a plurality of mantissa fields corresponding to the plurality of intermediate data, respectively, and a plurality of symbol fields corresponding to the plurality of intermediate data, and supplement hidden bits to the plurality of mantissa fields, respectively, according to the plurality of symbol fields, to obtain a plurality of complete mantissa fields participating in the target operation;

the complete mantissa field calculating module is used for respectively corresponding the complete mantissa fields to operation positions in the target operation and performing operation according to the target operation to obtain a mantissa field of an operation result and a sign field of the operation result;

the index field calculation module is used for obtaining a plurality of index fields respectively corresponding to the plurality of intermediate data, corresponding the plurality of index fields to operation positions in the target operation, and performing operation according to the target operation to obtain the index field of an operation result;

and the operation result determining module is used for outputting the mantissa field of the operation result, the exponent field of the operation result and the sign field of the operation result as the operation result data of the target operation to an encoding circuit, so that the operation result data is converted into Posite floating point numbers in the specified format through the encoding circuit according to the specified format in the calculation instruction.

Optionally, the intermediate data further comprises: an infinity field and a zero value field; the arithmetic processor further includes:

an infinite number field processing module, configured to set an infinite number field of an operation result to be true when an infinite number field of any one of the plurality of intermediate data is true, and output the infinite number field set to be true to the encoding circuit as operation result data of the target operation, so that the encoding circuit directly outputs a special code representing an infinite number;

a first zero-value field processing module, configured to set a zero-value field of an operation result to true when the target operation is an addition and zero-value fields in the multiple pieces of intermediate data involved in the target operation are all true;

a second zero-value field processing module, configured to set a zero-value field of the operation result to true when the target operation is a multiplication operation and a zero-value field of any one of the plurality of intermediate data participating in the target operation is true;

and the zero value field output module is used for outputting the zero value field which is set to be true as operation result data of the target operation to the coding circuit so that the coding circuit directly outputs special codes which represent zero.

Optionally, the mantissa field processing module includes: a tiled device and the following sub-modules:

the positive number splicing submodule is used for splicing 01 to the hidden bit of the mantissa field of the intermediate data corresponding to the symbol field by the splicing device when the symbol field is 0, so as to obtain a complete mantissa field of the intermediate data corresponding to the symbol field;

and the negative number splicing submodule is used for splicing 10 to the hidden bit of the mantissa field of the intermediate data corresponding to the sign field by the splicing device when the sign field is 1, so as to obtain the complete mantissa field of the intermediate data corresponding to the sign field.

Optionally, the mantissa field processing module further includes a shift device and the following sub-modules:

a difference calculation submodule, configured to obtain a difference between an exponent field of a larger number and an exponent field of a smaller number when the target operation is an addition operation; the larger number is the intermediate data having the largest exponent field among the plurality of intermediate data; the smaller number is the intermediate data of the plurality of intermediate data having the smallest exponent field;

and the mantissa shifting submodule is used for shifting the mantissa field of the smaller number to the right by the shifting device according to the difference when the target operation is addition operation, so that the positive number splicing submodule or the negative number splicing submodule supplements sign bits to the shifted mantissa field to obtain a complete mantissa field of the smaller number.

Optionally, the intermediate data further comprises a protection bit field; the complete mantissa field calculation module includes:

the range determination submodule is used for determining the value range of the mantissa field of the operation result according to the value range of the mantissa field when the target operation is multiplication;

the exponent field calculation module includes:

the first exponent correcting submodule is used for correcting the exponent field of the operation result according to the value interval where the mantissa field of the operation result is located when the target operation is multiplication, so that the corrected exponent field of the operation result is obtained;

the complete mantissa field calculation module includes: intercepting a device and the following sub-modules:

a mantissa field selecting module, configured to, when the target operation is multiplication, intercept, by the intercepting device, a decimal place with a fixed bit width from a high place to a low place in a mantissa field product result as a mantissa field of the operation result according to an exponent field of the corrected operation result; wherein the fixed bit width is a bit width of a mantissa field in the intermediate data.

Optionally, the arithmetic processor further comprises:

and the first protection bit result determining module is used for forming a protection bit field of an operation result by the highest three bits of the rest decimal places in the mantissa field product result obtained after intercepting the decimal places with the fixed bit width when the target operation is multiplication, and outputting the protection bit field of the operation result.

Optionally, the complete mantissa field calculation module includes: an exclusive-or device and the following sub-modules:

a sign calculation submodule, configured to, when the target operation is addition, obtain a plurality of extension bits in a plurality of mantissa fields corresponding to a plurality of intermediate data, perform, by using the xor device, a first xor operation on the plurality of extension bits, and then perform, by using the xor device, a second xor operation on a result of the first xor operation and a carry generated after the target operation is performed on the plurality of complete mantissa fields, to obtain a sign field of the operation result;

and the sign determining submodule is used for taking the highest bit after the target operation is executed by the plurality of complete mantissa fields as the sign field of the operation result when the target operation is the multiplication operation.

Optionally, the intermediate data further includes a protection bit field, and the mantissa field processing module further includes:

a protection bit retaining sub-module, configured to, when the target operation is an addition operation, add, as an operation protection bit, three bits with a value of 0 at the end of the mantissa field of the smaller number in a process of shifting the mantissa field of the smaller number to the right;

the complete mantissa field calculating module comprises the splicing device, an inverse code type leading zero detecting circuit device and the following sub-modules;

the splicing submodule is used for splicing the symbol field of the operation result, the mantissa field of the operation result and the operation protection bit to obtain a spliced field when the target operation is addition operation;

a mantissa field determining submodule, configured to detect, by the inverse-code-type leading zero detection circuit device, an invalid bit in the concatenated field when the target operation is an addition operation, to discard a decimal place of the concatenated field after the invalid bit, as a mantissa field of the operation result;

the exponent field calculation module includes:

an exponent field determination submodule, configured to modify the exponent field of the larger number by the number of bits of the invalid bit, to obtain an exponent field of the operation result;

the arithmetic processor further includes:

and the second protection bit result determining module is used for discarding the lowest three bits of the decimal place of the spliced field after the invalid bit as the protection bit field of the operation result when the target operation is addition operation.

Optionally, the arithmetic processor further includes:

and a divisor conversion module for converting intermediate data corresponding to a divisor participating in the target operation into a complement of an inverse of the divisor when the target operation is subtraction.

A second aspect of the embodiments of the present application provides an arithmetic processing system for a Posit floating point number, where the arithmetic processing system for a Posit floating point number includes a CPU, a decoding circuit, an encoding circuit, and an arithmetic processor for a Posit floating point number provided in the first aspect;

the CPU is a central processing unit of a computer, is connected with the decoding circuit and is used for generating a calculation instruction according to the input of a user and sending the calculation instruction to the decoding circuit; the calculation instruction comprises a target operation, posit floating point numbers participating in the target operation and a specified format of output Posit floating point numbers;

the decoding circuit is connected with the operation processor of the Posit floating point number and is used for converting the Posit floating point number participating in the target operation into intermediate data in a complementary code form and sending the intermediate data in the complementary code form to the operation processor of the Posit floating point number;

the Posit floating-point number operation processor is connected with the coding circuit and used for performing the target operation on the intermediate data in the complementary code form to obtain an operation result represented by the intermediate data in the complementary code form and sending the operation result represented by the intermediate data in the complementary code form to the coding circuit;

the coding circuit is used for coding the operation result expressed by the intermediate data in the complementary code form to obtain the Posit floating point number in the specified format, and sending the Posit floating point number in the specified format to a display device of a computer to display the Posit floating point number in the specified format.

The Posit floating point number operation processor provided by the embodiment of the application expands hidden bits and sign bits for the mantissa field of intermediate data obtained by a decoding circuit by a mantissa field processing module, so that a complete mantissa field calculation module can directly perform complement addition operation and complement multiplication operation on the mantissa field of the intermediate data in a complement form to obtain the mantissa field of an operation result and the sign field of the operation result, and then combines an exponent field calculation module to directly perform operation on the exponent field of the intermediate data, adjusts or corrects a larger exponent field in the addition operation and a product of two intermediate data by using the mantissa field of the operation result to obtain the exponent field of the operation result.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of an arithmetic processing system for a Posit floating-point number according to an embodiment of the present application;

FIG. 2 is a schematic structural diagram of an arithmetic processor for Posit floating-point numbers according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a mantissa processing module according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a complete mantissa field calculation module according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Posit floating point number is a new floating point number standard (also called un floating point standard, posit is third edition un standard) proposed by professor John l. By real number Mx 2 ^e For example, M is mantissa, 2 is radix, and e is exponent. The data of computer involved in operation are all represented by binary, so the base number of Posit floating point is 2.

The Posit floating point number needs to be defined in advance in a specific format, that is, the Posit floating point number needs to be defined in advance in total bit width and exponent bit width. For example, "Posit <8,1>" may represent a Posit encoding with a total bit width of 8 bits and an exponent bit width of 1 bit.

The standard for Posit floating point numbers specifies that Posit floating point numbers are complementary forms of encoding, and specifies that Posit floating point numbers include the following fields:

firstly, the following steps: a symbol field. The sign field is typically the most significant bit of a Posit floating point number.

2. And a regime field located after the sign field, the regime field being composed of a string of consecutive 1's from the most significant bit to the next least significant bit and the lowest significant bit of 0's, the lowest significant bit of 0's being a toggle bit, or being composed of a string of consecutive 0's from the most significant bit to the next least significant bit and the lowest significant bit of 1's. When the number of the fields is positive, the number of the fields is 1 minus 1, and when the fields are negative, the number of the fields is 0 minus negative. The width of the region field may be arbitrary. For example: when the region field is 1110, the value is 3-1=2; when the region field is 0001, it takes the value-3.

3. And if the region field does not use up the total bit width agreed in advance, the region field is followed by the coding index field, and the coding index field width is the bit width agreed in advance. The coding exponent field is an unsigned integer whose value must be greater than zero. The encoding exponent field is actually a field representing the exponent in Posit floating point number encoding.

4. And if the encoding exponent field and the region field do not use up the total bit width agreed in advance, the residual total bit width is the bit width of the mantissa field. It is understood that, in the decimal system, since the mantissa is a decimal number equal to or greater than 1.0 and less than 10, the integer part thereof takes any one of 1 to 9. In binary, the integer part of the mantissa may only be 1, and to reduce unnecessary encoding, the Posit floating point number standard takes the integer bit as a hidden bit and records only the decimal bit in the mantissa field of the Posit floating point number. For example: if the mantissa field is 1001, it plus the hidden bits is 11001, and the corresponding decimal value is 1 × 2 ⁰ +1×2 ^-1 +0×2 ^-2 +0×2 ^-3 +1×2 ^-4 ＝1.5625。

In the Posit floating point number standard, the concept of use is also defined, which is used to numerically unify the region field and the encoding exponent field. The value of useed is related to the bit width of the coded exponent field of the previously agreed Posit floating point number, and for any fixed-format Posit floating point number,the value of use is also fixed. Assuming that the bit width of the encoding exponent field is es, the value of useed is

For example, when es =1,

when the es =2, the power is supplied,

assuming that the sign of a Posit floating point number is s, the value of a register is r, the value of an exponent is e, and the mantissa value containing hidden bits is m, then the decimal real number corresponding to the Posit floating point number is:

(-1) ^s ×useed ^r ×2 ^e ×m

at present, posit floating point number is calculated by using original codes obtained by decoding Posit floating point number, specifically, an operation circuit judges whether the original codes are positive or negative, converts negative original codes into complementary codes, performs complementary code operation to obtain complementary code operation results, and then converts the operation results into original codes. The operation circuit for carrying out the whole operation process needs a plurality of logic circuits for positive and negative judgment and a plurality of circuits for mutual conversion of the original code and the complementary code, so that the logic of the operation circuit is complex, and the area and the power consumption are overlarge.

The Posit floating point number operation processing system has an instruction decoding function, generates a calculation instruction according to input information, and a decoding circuit can decode Posit floating point numbers acquired according to the calculation instruction into intermediate data in a complementary code form: the encoding circuit can encode the intermediate data in the complementary code form to obtain Posite floating point numbers in a specified format, and the Posite floating point number operation processor can perform target operation on the intermediate data in the complementary code form to obtain an operation result expressed by the intermediate data in the complementary code form, so that the whole operation processor does not need to be added with a logic circuit for conversion between the complementary code and the original code.

The Posit floating point number operation processing system comprises a CPU101, a decoding circuit 102, an encoding circuit 104 and an Posit floating point number operation processor 103 provided by all embodiments of the application;

referring to fig. 1, fig. 1 is a schematic structural diagram of an arithmetic processing system for floating point numbers of Posit according to an embodiment of the present application.

the specified format is a prescribed specific format of a Posit floating point number, and usually, "Posit < Total bit Width, exponent bit Width >" is used as the specified format. The target operation is an addition operation, a multiplication operation, or an FMA operation. FMA (Fused Multiplication and Addition) is an operation in which a Multiplication is performed, and then the resulting product is added to a third input. And finally, generating an intermediate data type according to the addition result. Since the bit width of the product is twice the mantissa bit width, all FMAs add higher precision than normal multiplication first plus.

Assuming the calculation of user input 3+0, the calculation instruction generated by CUP includes: the addition operation, posit floating point number 0 equals 1, count number 10 equals 1, count number 0 equals 0, count number 0 equals 0000, the specified format Posit <8,1>. The non-zero count circuit comprises a Posit floating point number code 0, a non-zero count circuit 10, a sign field of the Posit floating point number code 0, a register field of the Posit floating point number code 10, a code word digital field of the Posit floating point number code 1 and a mantissa field of the Posit floating point number code 1000.

the Posit floating-point number operation processor is connected with the coding circuit and used for performing the target operation on the intermediate data in the complementary code form to obtain an operation result expressed by the intermediate data in the complementary code form and sending the operation result expressed by the intermediate data in the complementary code form to the coding circuit;

the encoding circuit is used for encoding the operation result expressed by the intermediate data in the complementary code form to obtain the Posit floating point number in the specified format, and sending the Posit floating point number in the specified format to a display device of a computer so as to display the Posit floating point number in the specified format.

The complementary form of the intermediate data includes: an infinity field, a zero value field, a sign field, an exponent field, a mantissa field, and a guard bit field. After the infinite number codes (the codes with the highest bit being 1 and the rest bits being 0) and the zero value codes (the codes with all the bits being 0) are identified by the decoding circuit, the infinite number field and the zero value field are respectively set to be true and input into the operation processor, so that the infinite number field processing module, the first zero value field processing module, the second zero value field processing module and the zero value field output module of the operation processor can directly obtain zero or infinite number operation results, the operation results obtained by the modules such as the mantissa field processing module according to the symbol field, the exponent field and the mantissa field of the intermediate data do not need to be waited, and the efficiency of the operation processor for obtaining the operation results is improved.

Referring to fig. 2, fig. 2 is a schematic structural diagram of an arithmetic processor for floating point numbers of Posit according to an embodiment of the present application.

An infinite number segment processing module 201, configured to set an infinite number segment of an operation result to be true when the infinite number segment of any one of the plurality of intermediate data is true, and output the infinite number segment set to be true to the encoding circuit as operation result data of the target operation, so that the encoding circuit directly outputs a special code representing an infinite number;

the intermediate data are obtained by decoding a plurality of Posit floating point numbers after the decoding circuit obtains the Posit floating point numbers participating in target operation. The intermediate data corresponding to each Posit floating point number comprises six fields of an infinity field, a zero value field, a sign field, an exponent field, a mantissa field and a protection bit field. The infinity number field processing module reads the intermediate data corresponding to each Posit floating point number, when the infinity number field is read to be true, the infinity number field of the operation result is set to be true, the input coding circuit inputs the infinity number field of the operation result set to be true, and the coding circuit receives the infinity number field of the operation result set to be true and outputs an infinite number code: the most significant bit is 1 and the remaining bits are all 0 codes (assuming the specified format is Posit <8,1>, then an infinite number of codes is 10000000).

The exponent field obtained by the decoding circuit is a field obtained by splicing the coded exponent field and the register field of the Posit floating point number, and the operation processor of the Posit floating point number operates by the exponent field, so that the defect that the bit width of the register field is uncertain is avoided.

A first zero-value field processing module 202, configured to set a zero-value field of an operation result to be true when the target operation is addition and zero-value fields in the plurality of intermediate data participating in the target operation are all true;

a second zero-value field processing module 203, configured to set a zero-value field of the operation result to be true when the target operation is a multiplication operation and a zero-value field of any one of the plurality of intermediate data participating in the target operation is true;

a zero value field output module 204, configured to output the zero value field set to be true as operation result data of the target operation to the encoding circuit, so that the encoding circuit directly outputs a special code representing zero.

The infinite number field processing module and the first zero value field processing module are connected with the second zero value field processing module in parallel, the first zero value field processing module is used for processing intermediate data of a plurality of Posit floating point numbers participating in operation during addition operation and determining whether a zero value field of the operation result is true, the second zero value field processing module is used for processing the intermediate data of the plurality of Posit floating point numbers participating in operation during multiplication operation and determining whether the zero value field of the operation result is true, the zero value field output module is connected with the first zero value field processing module and the second zero value field and is used for outputting the true zero value field to the encoding circuit, so that the encoding circuit receives the true zero value field of the operation result and outputs a zero value code, and if the specified format is Posit <8,1>, the zero value code is 0000.

The acquiring module 205 of the operation processor for the Posit floating point number is connected to the decoding circuit, and the acquiring module decodes all fields of the intermediate data obtained by decoding the Posit floating point numbers participating in the operation by the decoding circuit: an infinity field, a zero value field, a sign field, an exponent field, a mantissa field, and a protection bit field. The obtaining module 205 inputs all six obtained fields into the infinity field processing module, the first null field processing module, the second null field processing module and the null field output module to quickly obtain the null field of the true operation result and the infinity field of the true operation result, and also inputs all six fields into modules (the mantissa field processing module and the like) connected in parallel with the infinity field processing module and the like to directly perform target operation on a plurality of mantissa fields, perform target operation on a plurality of exponent fields, and perform operation on a plurality of sign fields to obtain the mantissa fields of the operation result, the exponent fields of the operation result and the sign fields of the operation result, so that the encoding circuit encodes to obtain the Posit floating point number in the specified format directly according to the mantissa fields of the operation result, the exponent fields of the operation result and the sign fields of the operation result.

An obtaining module 205, configured to obtain intermediate data in multiple complementary forms participating in target operation output by the decoding circuit; the intermediate data is obtained by decoding Posit floating point numbers participating in operation by the decoding circuit according to a calculation instruction of a CPU; the intermediate data comprises at least the following fields: a sign field, an exponent field, and a mantissa field;

the acquisition module will acquire all fields of the intermediate data: an infinity field, a zero value field, a sign field, a mantissa field, an exponent field, a guard bit field.

A mantissa field processing module 206, configured to obtain a plurality of mantissa fields respectively corresponding to the plurality of intermediate data and a plurality of symbol fields respectively corresponding to the plurality of intermediate data, and supplement hidden bits to the plurality of mantissa fields according to the plurality of symbol fields, so as to obtain a plurality of complete mantissa fields participating in the target operation;

and the mantissa field processing module obtains the mantissa field and the sign field of the intermediate data of the Posit floating point number participating in the operation from the acquisition module. Suppose that a calculation instruction sent by the CPU performs addition 1 on a Posit floating point number 1 and a Posit floating point number 2, the decoding circuit decodes the Posit floating point number 1 to obtain intermediate data 1, decodes the Posit floating point number 2 to obtain intermediate data 2, the acquisition module acquires the intermediate data 1 and the intermediate data 2 participating in the addition 1, and the mantissa field processing module receives the mantissa field 1 and the sign field 1 in the intermediate data 1, and the mantissa field 2 and the sign field 2 in the intermediate data 2. Mantissa field 1, symbol field 1, and intermediate data 1 correspond.

The operation processor directly splices the sign field to the mantissa field to participate in target operation, and the circuit is simple, so that a redundant logic circuit for judging positive and negative caused by judging the positive and negative of a Posit floating point number for many times is avoided. For example: the existing floating-point number operation processor is used for addition operation, assuming that two Posit floating-point numbers involved in operation are respectively a positive number and a negative number, and the absolute value of the negative Posit floating-point number is large, the floating-point number operation processor needs to be provided with a logic circuit which judges the positive and negative of the two Posit floating-point numbers through an original code, and then is provided with a circuit which converts the original code of the negative Posit floating-point number into a complement code, after the addition operation is finished, the logic circuit which judges the positive and negative of an operation result needs to be arranged, and the logic circuit which converts the operation result of the negative number into the complement code according to the positive and negative of the operation result is arranged.

And the mantissa field of the intermediate data is obtained by directly filling zero in Posit floating point number codes after the decoding circuit analyzes the region field and the encoding exponent field. Positt floating point numbers are binary data, and Positt floating point number standards specify that the hidden bit is 1, so the mantissa field in Positt floating point number encoding is a scientific count method: mx 2 ^e The fractional part of M.

The sign field of the intermediate data is the sign field of the intermediate data directly using the highest bit of the Posit floating point number after the decoding circuit analyzes the Posit floating point number code, namely using the sign field of the Posit floating point number as the sign field of the intermediate data.

Therefore, the mantissa field processing module not only splices the sign field but also splices the mantissa field with the integer part to complete the mantissa field of the intermediate data with only the fractional part, wherein the complete mantissa field is obtained by supplementing the hidden bits to the mantissa field of the intermediate data.

When the hidden bits are supplemented, the mantissa field processing module uses a positive number splicing submodule and a negative number splicing submodule to supplement the hidden bits to the mantissa field of the intermediate data when the sign field is 0 and the sign field is 1 respectively. Referring to fig. 3, fig. 3 is a schematic structural diagram of a mantissa processing module according to an embodiment of the present application.

The mantissa field processing module includes: a tiled device and the following sub-modules:

the positive number splicing submodule 206-1 is configured to splice 01 to the hidden bit of the mantissa field of the intermediate data corresponding to the symbol field by using the splicing device when the symbol field is 0, so as to obtain a complete mantissa field of the intermediate data corresponding to the symbol field;

when the sign field is 0, the Posit floating point number corresponding to the intermediate data participating in the operation is a positive number, the mantissa field is also necessarily a positive number, the hidden bit of the mantissa field is 1,0 is used as the sign bit and is placed at the highest bit, and 1 is used as an integer bit, so 01 is spliced to the upper bit of the mantissa field.

And the negative number splicing submodule 206-2 is configured to splice 10 to the hidden bit of the mantissa field of the intermediate data corresponding to the sign field by using the splicing device when the sign field is 1, so as to obtain a complete mantissa field of the intermediate data corresponding to the sign field.

For a special case of intermediate data participating in addition operation, the positive number splicing submodule is provided with a zero value splicing subunit, and for mantissa fields with all zero bits, 00 is spliced at the highest bits of the mantissa fields to be used as hidden bits of the mantissa field extension with zero bits.

When the sign field is 1, the Posit floating point number corresponding to the intermediate data participating in the operation is a negative number, the mantissa field is a complement, because the complement algorithm can cause carry, originally 1 should be added to the exponent of the Posit floating point number, when the hidden bit is supplemented, 1 is taken as the sign bit and is placed at the highest bit, 1 is taken as the integer bit and is supplemented by 11, but 10 is actually supplemented, 10 is supplemented to the hidden bit of the mantissa field, and 2 is taken as the integer bit of the mantissa field, so that the exponent increase of the mantissa field of the Posit floating point number of the negative number caused by the complement algorithm is cancelled.

A complete mantissa field calculating module 207, configured to respectively correspond the multiple complete mantissa fields to operation positions in the target operation, and perform operation according to the target operation to obtain a mantissa field of an operation result and a symbol field of the operation result;

when the target operation is addition, a circuit for setting a zero value field to be zero is arranged in the complete mantissa field calculating module, and the intermediate data of the operation processor for inputting Posit floating point number comprises six fields: the operation result output by the operation processor of the Posit floating point number still comprises six fields: the field of infinite number of the operation result, the field of zero value of the operation result, the sign field of the operation result, the exponent field of the operation result, the mantissa field of the operation result and the protection bit field of the operation result, and the circuit built in the complete mantissa field calculating module sets the field of zero value of the operation result to be true when each bit of the mantissa field of the operation result obtained by the complete mantissa field calculating module is zero. The circuit which is arranged in the complete mantissa field calculation module and used for setting the zero value field of the operation result to be zero can multiplex the circuit structure of the first zero value field processing module.

An index field calculation module 208, configured to obtain a plurality of index fields corresponding to the plurality of intermediate data, respectively, correspond the plurality of index fields to operation positions in the target operation, and perform an operation according to the target operation to obtain an index field of an operation result;

when the target operation is addition, the operation position in the target operation is an addend, when the target operation is multiplication, the operation position in the target operation is a multiplier, when the target operation is subtraction, the operation position in the target operation is a subtrahend and a subtrahend, and when the target operation is FMA, the operation position in the target operation is an addend and a multiplier.

And respectively corresponding the plurality of complete mantissa fields and the plurality of exponent fields to operation positions in the target operation of the plurality of complete mantissa fields and the plurality of exponent fields, wherein the essence is that the target operation corresponding to the complete mantissa fields and the exponent fields is determined to be any one of addition, subtraction and multiplication, the size characteristics of intermediate data belonging to the complete mantissa fields and the exponent fields are determined, and the received plurality of complete mantissa fields and the plurality of exponent fields are distinguished. The complete mantissa field is further operated upon by the intermediate data to its respective associated circuit. And respectively corresponding the plurality of index fields to operation positions in the target operation of the index fields, so that the respective related circuits of the index fields further process the index fields and further perform related operation on the index fields. Thus, the meaning of respectively corresponding the plurality of full mantissa fields and the plurality of exponent fields to operation positions each in its target operation is that the exponent field and the full mantissa field obtained are processed with a multiplication correlation circuit when the target operation is multiplication, and the exponent field and the full mantissa field obtained are processed with an addition correlation circuit when the target operation is addition.

Before the multiplication related circuit multiplies the multiple exponent fields and the multiple complete mantissa fields, circuit modules such as a range determining module and the like are further used for processing the multiple exponent fields and the multiple complete mantissa fields according to a multiplier format required by multiplication. Before the addition correlation circuit performs addition operation on the multiple exponent fields and the multiple complete mantissa fields, circuit modules such as a difference value calculation module and the like are further used for processing the multiple exponent fields and the multiple complete mantissa fields according to an addend format required by addition. With continued reference to FIG. 3, the circuit device logic in a particular mantissa processing module is as follows:

one embodiment of the present application provides the composition and circuit logic of the relevant circuits when performing the addition operation.

The mantissa field processing module includes: a shift device and the following sub-modules;

a difference calculation sub-module 206-3, configured to obtain a difference between the exponent field of the larger number and the exponent field of the smaller number when the target operation is an addition operation; the larger number is the intermediate data having the largest exponent field among the plurality of intermediate data; the smaller number is an intermediate data having a smallest exponent field among the plurality of intermediate data;

and the mantissa shifting submodule 206-4 is configured to, when the target operation is an addition operation, shift the mantissa field of the smaller mantissa to the right by using the shifting device according to the difference, so that the positive number splicing submodule or the negative number splicing submodule supplements sign bits to the shifted mantissa field to obtain a complete mantissa field of the smaller mantissa.

The supplemental sign bit may also be an arithmetic right shift.

A protection bit holding sub-module 206-5, configured to add three bits with a value of 0 at the end of the mantissa field of the smaller number as operation protection bits in the process of shifting the mantissa field of the smaller number to the right when the target operation is an addition operation;

the operation protection bit is used as a protection bit in addition operation to protect the accuracy degree of a smaller number.

When the target operation is addition, the difference calculation submodule of the mantissa field processing module 206 compares the sizes of the plurality of intermediate data with the obtained plurality of exponent fields, takes the intermediate data with the minimum exponent field as a smaller number, takes the intermediate data with the maximum exponent field as a larger number, obtains the difference between the maximum exponent field and the minimum exponent field, and inputs the difference, and the judgment results of the larger number and the smaller number into the mantissa shift submodule and the protection bit retention submodule;

and the protection bit reservation submodule adds a protection bit to the tail of the mantissa field of the smaller number so as to round the mantissa field of the smaller number which is shifted to the right, and ensure the accuracy of the mantissa field of the smaller number. And the mantissa shift submodule shifts the mantissa field corresponding to the smaller number by a corresponding digit to the right according to the difference value so as to align the positions of the decimal points of the mantissa fields of the larger number and the smaller number, supplements the hidden bits to the mantissa field of the larger number after aligning the decimal points to obtain the complete mantissa field of the larger number, and supplements the hidden bits to the mantissa field of the smaller number after aligning the decimal points to obtain the complete mantissa field of the smaller number. It will be appreciated that the lowest three bits of the complete mantissa field of the smaller number are guard bits and that the operation guard bits do not participate in the operation.

The three-bit Guard bits GRS are specified in the Posit floating-point number standard and are called Guard, round, sticky, respectively.

Illustratively, the two Posit floating point numbers that participate in the addition operation in the format Posit <8,1> are: 1 no 1 and 0 no 10 qi, wherein the index of 0 no 1 is more than the index of 0 no 10 zero 1 is greater than the index of 0 no 10 zero 1,0 no 10 zero 1 is more than the index of 0 no 1 zero 1011, 0 no 1 zero 1 is more than the index, 0 no 10 zero 0 zero 0 zero 1011 is less than the index, 0 zero 10 zero 1 zero 1000 is a field formed by splicing the value-taking fields of the encoding index field 1 and the region field 10, the value of the region field 10 is 0, therefore, the splicing field of the encoding index fields 1 and 0 which are zero 0 and 10 and zero 1 is 1, the index field which is zero 0 and 10 and zero 0 and 1011 in the same way is 0, the difference calculation module obtains that the difference between the index fields which are 0 and 10 and zero 1 and 0 and zero 10 and zero 1011 is 1, the difference calculation module inputs the difference 1 into the mantissa shifting sub-module and the protection bit preserving sub-module to continue the following processing: the operation protection bit 000 is spliced by a smaller number 1011, the operation protection bit 000 is shifted to the right by one 0101 and one 1011 is shifted to the right by 100,1, and the operation protection bit becomes 100. 100 do not participate in the operation. Supplementing 1000 with the hidden bit results in 01 the Y cells 1000, supplementing 0101 the Y cells 100 with the hidden bit results in 01 the Y cells 0101 the Y cells 100. 01Y 1000 and 01Y 0101Y 100 are full mantissa fields of larger and smaller numbers, respectively.

After the mantissa field processing module obtains the complete mantissa field, the mantissa field is input to the complete mantissa field calculating module, and the complete mantissa field calculating module 207 adds the complete mantissa field of the smaller number and the complete mantissa field of the larger number according to the addition operation. The complete mantissa field calculation module provided by the application further comprises a symbol calculation submodule 207-1, so that the symbols of Posit floating point numbers participating in addition operation are subjected to addition operation, a complementary symbol result is directly obtained and is used as a symbol field of an operation result, and repeated positive and negative symbol judgment in the calculation process is further avoided.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a complete mantissa field calculation module according to an embodiment of the present application.

The complete mantissa field calculation module comprises: an exclusive-or device and the following sub-modules:

the sign calculation sub-module 207-1 is configured to, when the target operation is addition, obtain a plurality of extension bits in a plurality of mantissa fields corresponding to a plurality of intermediate data, perform a first exclusive or operation on the plurality of extension bits by using the exclusive or device, and perform an exclusive or operation on a result of the first exclusive or operation and a carry bit generated after the target operation is performed on the plurality of complete mantissa fields by using the exclusive or device to obtain a sign field of the operation result;

the extension bits comprise complementary hidden bits and a sign bit, and the sign computation submodule performs only addition operations on the signs, so performing a first exclusive-or operation on the plurality of extension bits refers to performing an exclusive-or operation on the sign bit, that is, performing an exclusive-or operation on the sign field of the intermediate data. The essence of the exclusive-or operation is that when both inputs are 0 or both are 1, the output is 0; when one of the two inputs is 1 and the other input is 0, the output is 1,0 plus 0 and still is 0,1 plus 1 carry, the current bit is still 0,1 plus 0 and the current bit is 1, and the carry can be regarded as binary addition operation, so that the sign bit of the extension bit in the complete mantissa field can be independently taken out for addition operation. After the complete mantissa field is subjected to addition operation, the complementary extension bit needs to have the situation of carry, but the carry does not exist in the sign addition, so the highest bit of the carry after the complete mantissa field is subjected to the exclusive OR according to the result of the sign exclusive OR to obtain the sign field of the operation result.

The first exclusive-or operation is an exclusive-or operation on the sign field and the second exclusive-or operation is an exclusive-or operation on the added highest bit of the result of the first exclusive-or operation and the full mantissa field.

Illustratively, the two complete mantissa fields that perform the addition operation are 01 n 1100 and 10 n 1000, the sign bit is xored to obtain 1, the 01 n 1100 and 10 n 1000 are added to obtain 100 n 0100, a carry is generated, 1 is xored to 1, the sign field is 0, i.e., the sign field of the operation result after the addition of 01 n 1100 and 10 n 1000 is 0, and in the case of the same exponent fields, the result of the addition of 01 n 1100 and 10 n 1000 is a positive number.

The complete mantissa field calculation module 207 comprises the splicing device, an inverse code type leading zero detection circuit device and the following sub-modules; a splicing submodule 207-2, configured to splice a sign field of the operation result, a mantissa field of the operation result, and the operation protection bit to obtain a spliced field when the target operation is an addition operation;

a mantissa field determining sub-module 207-3, configured to detect, by the inverse code type leading zero detecting circuit device, an invalid bit in the concatenated field when the target operation is an addition operation, so as to discard a decimal place of the concatenated field after the invalid bit as a mantissa field of the operation result;

the operation protection bit rounds a spliced field formed by splicing a sign field of the operation result and a mantissa field of the operation result. If the values of all bits of the concatenation field are 0, the complete mantissa field calculation module may determine that the mantissa field of the operation result is 0, and the encoding circuit outputs a zero-valued code when receiving the operation result expressed by the intermediate data in the complementary code form, in which the mantissa field of the operation result is 0. If the values of all the bits in the spliced field are not 0, detecting invalid bits of the spliced circuit through a code-inversed leading zero detection circuit device, wherein the invalid bits are all the bits before the first non-zero bit after the most significant bit. For scientific and technical methods, mantissas do not include invalid bits. Accordingly, the exponent field of the operation result needs to be corrected by the number of bits of the invalid bit.

For example, if the concatenation field is 1Y 011, where 1 is the sign field of the operation result and the invalid bit is 1 bit.

The reverse leading zero detection circuit device obtains a plurality of input fields with the bit width of 2 by utilizing a binary circuit and by carrying out multiple halving on the spliced fields, and obtains the 1 st bits of the output fields by carrying out OR operation on the 0 th bits of the input fields with the bit width of 2 and the 1 st bits of the input fields with the bit width of 2 by using an XOR device; and respectively carrying out negation operation on the 0 th bits of the input fields with the bit width of 2 by using a negation device, and respectively carrying out OR operation on the plurality of negation results and the 1 st bits of the input fields with the bit width of 2 by using the OR device to obtain the 0 th bits of the plurality of output fields.

For example, assuming that the concatenation field is 000001, the plurality of input fields having a bit width of 2 obtained by the binary circuit are (00), and (01). And detecting each input field with the bit width of 2 by using the sub-circuit to obtain the inverse code of the number of 0 in each input field with the bit width of 2.

In the description of (01) in the input fields having a bit width of 2, "1" is the 0 th bit of the input field (01), "0" is the 1 st bit of the input field (01), "0" is obtained by inverting "1", and "0" is ored with "0" to obtain 0 as the 0 th bit of the corresponding output field of (01). Similarly, the 1 st bit of the output field is 1, (01) the corresponding output field is '10', similarly, the corresponding output field of (00) is 01 by calculating the sub-circuit pair (00), and then the inverse code [ (01) (01) (10) ] of the value of the splicing field is output.

And (3) obtaining the inversed codes [ (01) (01) (10) ] of the spliced values, and inversing the '10' to obtain '01', wherein the 01 is the number of 0 in the (01), and represents that 10 in the (01) exists. Negating 01, the number of 0 s in (00) is 10, which means 20 s in (00). Further, as a result of detecting a plurality of input fields [ (00) (00) (01) ] each having a bit width of 2, [ (2) + (2) + (1) ], i.e., 5 in total of 0 s out of 000001, are obtained. The sign bit of the most significant bit is removed and the number of bits of the invalid bit of the concatenated field is 4.

And (4) performing addition exponential calculation, namely taking a larger number of exponential fields, and correcting the larger number of exponential fields by using invalid bits to obtain the exponential fields of the operation result. Therefore, after determining the invalid bit of the submodule by the mantissa field of the complete mantissa field calculation module, the invalid bit is input into the exponent field calculation module, and after receiving a plurality of exponent fields, the exponent field calculation module 208 correspondingly adds the exponent fields, distinguishes the exponent fields to obtain a smaller number and a larger number, obtains the exponent field of the larger number, and subtracts the digits of the invalid bit from the exponent field of the larger number to obtain the exponent field of the operation result.

The exponent field calculation module 208 includes:

an exponent field determination submodule 208-1, configured to modify the exponent field of the larger number by the number of bits of the invalid bit, so as to obtain an exponent field of the operation result;

and an operation result determining module 209, configured to output, as operation result data of the target operation, the mantissa field of the operation result, the exponent field of the operation result, and the sign field of the operation result to an encoding circuit, so that the encoding circuit converts, according to a specified format in the computation instruction, the operation result data into a Posit floating point number in the specified format.

The arithmetic processor further includes:

a second protection bit result determining module 210, configured to discard, when the target operation is an addition operation, the least three bits of the decimal place of the concatenation field after the invalid bit as a protection bit field of the operation result.

The operation result determining module also outputs the protection bit field of the operation result to the encoding circuit.

If the mantissa field of the Posit floating point number code to be decoded is a special case that all bits are 0, because the Posit floating point number is a code in a complementary form, when the Posit floating point number is a positive number, the hidden bit of the mantissa field is processed according to 1; when Positt floating point numbers are negative, the hidden bits of the mantissa field encoded by Positt floating point numbers are treated as-2 (10.000 8230;). Assuming that the Posit floating point number is a negative number, the mantissa field (00000) with all bits of 0 is actually (1111), and a carry bit is necessarily generated in the process of obtaining the complement of (1111), and the hidden bit is reduced by 1, and the exponent field needs to be reduced by 1 because the hidden bit is-2, so that when the Posit floating point number is a negative number, the hidden bit of the mantissa field of the intermediate data is processed as 2 (10.000 \8230;).

As can be seen from the above analysis, the mantissa field obtained by the decoding circuit 102 has a value range of [ -2, -1) — u [1, 2). Since the range of the mantissa field of the intermediate data is [ -2, -1) < u > 1, 2), it is necessary to guarantee that the discarded mantissa is 1.xxx, -1.xxx, or-2.000 when the discarded invalid bit is left-shifted.

With continued reference to fig. 2 and fig. 1, the operation result determining module 209 inputs the mantissa field of the operation result, the exponent field of the operation result, and the sign field of the operation result, which are obtained by the exponent field calculating module and the complete mantissa field calculating module, into the encoding circuit 104, and the encoding circuit encodes the intermediate data to obtain a process of encoding a Posit floating point number, which is an inverse process of encoding and decoding the Posit floating point number by the decoding circuit 102 to obtain the intermediate data. And taking out an encoding exponent field and a region field from the exponent field of the operation result, sequentially splicing the sign field, the region field and the mantissa field of the operation result in an arithmetic right shift and filling mode, rounding the spliced fields, and finally obtaining the Posit floating point number code.

Another embodiment of the present application provides the composition and circuit logic of the correlation circuit when performing the multiplication operation.

The intermediate data further comprises a protection bit field; the complete mantissa field calculation module includes:

the range determination submodule 207-4 is configured to determine a value range of the mantissa field of the operation result according to the value range of the mantissa field when the target operation is multiplication;

continuing to refer to fig. 4, when the target operation is multiplication, the complete mantissa field calculating module performs multiplication on the mantissa field of the intermediate data corresponding to the Posit floating point number participating in the operation, and specifically performs multiplication on the complete mantissa field output by the mantissa field processing module. And determining the value range of the mantissa field of the operation result.

The mantissa field of the intermediate data decoded by the decoding circuit 102 has a value range of: the range of values is [ -2, -1) < 1, 2), the range of values obtained by multiplying the mantissa fields of the two intermediate data is (-4, -1) < 1,4], if the mantissa field of the operation result is located in a sub-range (-4, -2) < 2, 4) of (-4, -1) < 1,4], a first exponent modification submodule is required to add 1 to the exponent field of the operation result; if the mantissa field of the operation result is 4, the first exponent modification submodule is required to add 2 to the exponent field of the operation result. Note that when the mantissa field of the operation result is-2, it is not necessary to modify the exponent field of the operation result by the first exponent modification submodule. Therefore, the range determining submodule needs to determine an interval where the mantissa field of the operation result is located, so that the first exponent correcting submodule corrects the exponent operation result correspondingly according to the interval where the mantissa field of the operation result is located.

The exponent field calculation module includes:

the first exponent modification submodule 208-2 is configured to, when the target operation is multiplication, modify an exponent field of the operation result according to a value interval where a mantissa field of the operation result is located, to obtain a modified exponent field of the operation result;

when the target operation is a multiplication operation, the exponent field calculation module adds exponent fields of the intermediate data, and the full mantissa field calculation module multiplies mantissa fields of the intermediate data.

a mantissa field selecting module 207-5, configured to intercept, according to an exponent field of the corrected operation result, a decimal digit with a fixed bit width from a high bit to a low bit in a mantissa field product result by the intercepting device as a mantissa field of the operation result when the target operation is multiplication; wherein the fixed bit width is a bit width of a mantissa field in the intermediate data.

And the sign determining submodule 207-6 is used for taking the highest bit after the target operation is executed by the plurality of complete mantissa fields as the sign field of the operation result when the target operation is a multiplication operation.

Because the multiplication of the embodiment of the application is complement multiplication, the highest bit of the operation result obtained by multiplying the complete mantissa field by the complete mantissa field calculation module is the sign field of the operation result.

The bit width of the product of two complete data fields is twice the mantissa bit width of the intermediate data plus 4, where the highest 4 bits are integer bits and the remainder are decimal bits before exponent correction. And intercepting all small digits behind the hidden digit according to the exponent field of the obtained operation result after the product of the exponent field is corrected by the first exponent correcting submodule, and selecting a plurality of first digits as mantissas, wherein the bit width is the bit width for processing the mantissas specified by an operation processor of Posit floating point numbers. The remaining fraction bits constitute the GRS bits used for rounding operations in encoding.

For example, assuming that the product of two complete data fields in the complete mantissa field calculation module is 0001 calcualted 0100,0001 is an integer bit, if 1 is added to the exponent field of the corrected operation result, the corresponding truncated decimal bit is 10100.

The arithmetic processor further includes:

a first protection bit result determining module 211, configured to, when the target operation is multiplication, form a protection bit field of an operation result from mantissa field product results obtained by intercepting the fixed-bit-width decimal places, where the highest three bits of the remaining decimal places form the protection bit field of the operation result, and output the protection bit field of the operation result.

When the target operation is subtraction, the subtraction in the plurality of intermediate data is processed by a subtraction conversion module and converted into a complementary code, and then the addition operation is respectively carried out on each field of the plurality of intermediate data by modules such as a mantissa field processing module, a complete mantissa field and a calculation module exponent field calculation module.

And the reduction number conversion module is used for converting the intermediate data corresponding to the reduction number participating in the target operation into a complement of the opposite number of the reduction number when the target operation is the subtraction.

Specifically, the negation of the subtrahend can be added by 1 by an negation logic circuit to obtain the complement of the inverse of the subtrahend.

When the Posit floating point number operation processor processes FMA, the correlation circuit of addition operation and the correlation of multiplication operation can be integrated, two intermediate data are multiplied, and then the obtained product is added with the third intermediate data. Since the bit width of the product is twice the mantissa bit width, all FMAs add higher precision than normal multiplication-first plus-second.

The Posit floating point number operation processor provided by the embodiment of the application expands hidden bits and sign bits for the mantissa field of intermediate data obtained by a decoding circuit by a mantissa field processing module, so that a complete mantissa field calculation module can directly perform complement addition operation on the mantissa field of the intermediate data in a complement form and complement multiplication operation to obtain the mantissa field of an operation result and the sign field of the operation result, and then directly operates the exponent field of the intermediate data by combining an exponent field calculation module.

The Posit floating point number arithmetic processor can decode a decoding circuit of a Posit floating point number arithmetic processing system to obtain the intermediate data of a complement type to carry out addition, subtraction, multiplication and FMA operation, namely the Posit floating point number arithmetic processor can independently carry out complement addition operation, complement multiplication operation and complement subtraction operation.

While preferred embodiments of the present application have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the true scope of the embodiments of the application.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or terminal device that comprises the element.

The above detailed description is given to the operation processor and the operation processing system of the Posit floating point number provided by the present application, and the description of the above embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. An arithmetic processor for Posit floating point numbers, the arithmetic processor comprising:

the acquisition module is used for acquiring a plurality of complementary intermediate data which are output by the decoding circuit and participate in target operation; the intermediate data is obtained by decoding Posit floating point numbers participating in operation by the decoding circuit according to a calculation instruction of a CPU; the intermediate data comprises at least the following fields: a sign field, an exponent field, and a mantissa field;

the mantissa field processing module is used for obtaining a plurality of mantissa fields respectively corresponding to the plurality of intermediate data and a plurality of symbol fields respectively corresponding to the plurality of intermediate data, and supplementing hidden bits to the plurality of mantissa fields respectively according to the plurality of symbol fields to obtain a plurality of complete mantissa fields participating in the target operation;

and the operation result determining module is used for outputting the mantissa field of the operation result, the exponent field of the operation result and the sign field of the operation result as operation result data of the target operation to an encoding circuit, so that the operation result data is converted into Posite floating point numbers in a specified format through the encoding circuit according to the specified format in the calculation instruction.

2. The Posit floating point number arithmetic processor of claim 1, wherein the intermediate data further comprises: an infinity field and a zero value field; the arithmetic processor further includes:

a first zero-value field processing module, configured to set a zero-value field of an operation result to true when the target operation is an addition and zero-value fields in the plurality of intermediate data participating in the target operation are all true;

3. The Posit floating point number arithmetic processor of claim 1, wherein the mantissa field processing module comprises: a stitching device and the following sub-modules:

the positive number splicing submodule is used for splicing 01 to the hidden bit of the mantissa field of the intermediate data corresponding to the symbol field by the splicing device when the symbol field is 0 to obtain a complete mantissa field of the intermediate data corresponding to the symbol field;

4. The Posit floating point number arithmetic processor of claim 3, wherein the mantissa field processing module further comprises a shift device and the following sub-modules:

and the mantissa shifting submodule is used for shifting the mantissa field of the smaller mantissa to the right by the shifting device according to the difference when the target operation is addition operation, so that the positive number splicing submodule or the negative number splicing submodule supplements sign bits to the shifted mantissa field to obtain a complete mantissa field of the smaller mantissa.

5. The Posit floating point number arithmetic processor of claim 3, wherein the intermediate data further comprises a protection bit field; the complete mantissa field calculation module includes:

the exponent field calculation module includes:

6. The Posit floating point number arithmetic processor of claim 5, further comprising:

and the first protection bit result determining module is used for forming a protection bit field of an operation result by the highest three bits of the rest decimal digits in a mantissa field product result obtained after intercepting the decimal digits with the fixed bit width when the target operation is multiplication, and outputting the protection bit field of the operation result.

7. The Posit floating point number arithmetic processor of claim 3, wherein the full mantissa field calculation module comprises: an exclusive-or device and the following sub-modules:

a sign calculation sub-module, configured to, when the target operation is addition, obtain a plurality of extension bits in a plurality of mantissa fields corresponding to a plurality of intermediate data, perform, by using the xor device, a first xor operation on the plurality of extension bits, and then perform, by using the xor device, a second xor operation on a result of the first xor operation and a carry generated after the target operation is performed on the plurality of complete mantissa fields, to obtain a sign field of the operation result;

8. The Posit floating point number arithmetic processor of claim 4, wherein the intermediate data further includes a protection bit field, the mantissa field processing module further comprising:

a mantissa field determining submodule configured to detect, by the inverse code type leading zero detecting circuit device, an invalid bit in the concatenated field when the target operation is an addition operation, to discard a decimal place of the concatenated field after the invalid bit as a mantissa field of the operation result;

the exponent field calculation module includes:

the arithmetic processor further includes:

and a second protection bit result determining module, configured to discard, when the target operation is an addition operation, the least three bits of the decimal place of the concatenation field after the invalid bit, as a protection bit field of the operation result.

9. The Posit floating point number arithmetic processor of claim 1, further comprising:

10. An operation processing system for Posit floating point numbers, which is characterized by comprising a CPU, a decoding circuit, an encoding circuit and an operation processor for Posit floating point numbers according to any one of claims 1 to 9;