CN111526091B

CN111526091B - Method for executing write operation by memory and memory

Info

Publication number: CN111526091B
Application number: CN201910108882.6A
Authority: CN
Inventors: 赵岩; 李楠
Original assignee: Huawei Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2019-02-03
Filing date: 2019-02-03
Publication date: 2021-09-03
Anticipated expiration: 2039-02-03
Also published as: CN111526091A

Abstract

The application provides a method for a memory to execute write operation and a memory, wherein the memory comprises a controller and a first bank, the first bank comprises a first bank unit, the first bank unit comprises a plurality of storage units, the controller is used for receiving a read request, and the read request carries a storage address of a first message segment to be read; the controller is used for determining a storage unit for storing the first message segment according to the storage address; the controller is used for reading the first message segment from the storage unit so as to improve the utilization rate of the storage space in the memory.

Description

Method for executing write operation by memory and memory

Technical Field

The present application relates to the field of information technology, and more particularly, to a method of performing a write operation by a memory and a memory.

Background

A network device (e.g., a router) may receive and forward a message. After the network device receives the message, the message can be cached before being forwarded. The message caching technology can improve the utilization rate of the bandwidth of the output port of the network equipment.

Based on the above packet caching technology, the network device may cache the received packet in a Packet Buffer (PB) of the network device. Currently, a message buffer includes a plurality of banks, and each bank includes a plurality of equal-capacity bank units (bank cells) for providing a storage space for a message. After the message buffer receives the message, the message is segmented based on the capacity of the bank unit to obtain a plurality of message fragments, and the message fragments are respectively stored in one bank unit, and each bank unit only stores one message fragment.

However, the size of the packet is usually not an integer multiple of the capacity of the bank unit, that is, the size of the last generated packet fragment is usually much smaller than the capacity of the bank unit among the plurality of packet fragments obtained by performing segmentation processing on the packet according to the capacity of the bank unit, which causes the storage space in the bank unit to be wasted and reduces the utilization rate of the storage space. For example, the size of one packet is 129 bytes (B), the capacity of a bank unit in a bank is 128B, and two packet fragments can be obtained by performing segmentation processing on the packet according to the capacity of the bank unit, where the size of the first packet fragment is 128B and the size of the second packet fragment is 1B. The two message fragments are stored in two bank units respectively, and for the bank unit storing the second message fragment, 127B of storage space is wasted.

Disclosure of Invention

The application provides a method for writing messages into a memory and the memory, so as to improve the utilization rate of a storage space in the memory.

In a first aspect, a memory is provided, where the memory includes a controller and a first bank, where the first bank includes a first bank unit, the first bank unit includes a plurality of storage units, and the controller is configured to receive a write request, where the write request is used to request to write a first packet fragment; the controller is configured to select a first memory cell from a plurality of memory cells of the first bank cell; the controller is configured to write the first packet segment into the selected first storage unit, where a capacity of the first storage unit is greater than or equal to a size of the first packet segment.

In the embodiment of the application, one bank unit is divided into a plurality of storage units to store the message fragments, so that the utilization rate of the storage space is favorably improved, and the problem that each bank unit only stores one message unit in the prior art and the waste of the storage space of the bank unit is large when the size of the message unit is small is avoided.

In a possible implementation manner, the first bank includes a plurality of sub-banks, each sub-bank includes at least one storage unit, the plurality of sub-banks respectively include a plurality of storage units included in the first bank unit, and the plurality of sub-banks correspond to the plurality of storage units included in the first bank unit one to one; the controller for selecting a first memory cell from a plurality of memory cells of the first bank cell includes: the controller is used for selecting a first sub-bank from the plurality of sub-banks; and selecting the first memory cell from at least one memory cell included in the selected first sub-bank.

In the embodiment of the application, the plurality of storage units are divided in the form of sub-bank and bank units, so that the storage units can be quickly positioned.

In a possible implementation manner, the controller includes a plurality of idle address pool controllers FAPC, the plurality of FAPCs correspond to the plurality of sub-banks one by one, and each FAPC records an address of a storage unit in an idle state in a corresponding sub-bank; the controller is configured to select the first memory cell from at least one memory cell included in the selected first sub-bank, and the controller is configured to: the controller is configured to select an address of a first storage unit from addresses of storage units recorded by a first FAPC among the multiple FAPCs, where the first FAPC corresponds to the first sub-bank.

In the embodiment of the application, the storage unit in the idle state is managed by the FAPC corresponding to each sub-bank, so that when a plurality of message fragments need to be stored, the storage units can be allocated to the message fragments in parallel, which is beneficial to reducing the time delay of storing the message.

In a possible implementation manner, the first message segment is a segment in a first message, the first message further includes a second message segment, and the memory includes a second storage unit; the controller is further configured to write the second message segment into the second storage unit, and the controller records information indicating that the message segment stored in the first storage unit and the message segment stored in the second storage unit are adjacent message segments in a message.

In the embodiment of the application, the first storage unit and the second storage unit are associated through information, the message segment stored in the first storage unit and the message segment stored in the second storage unit are indicated to be adjacent message segments in a message, and the information is stored in the controller, so that the controller can restore the message according to the information.

Optionally, the information further indicates that the message segment stored in the first storage unit is located before the message segment stored in the second storage unit in the message.

In the embodiment of the application, the first storage unit and the second storage unit indicate the sequence of the message segments in the first storage unit and the message segments in the second storage unit in the message, which is beneficial for the controller to restore the message segments into the message according to the sequence.

In a possible implementation manner, the information is represented by an array, an element number of an xth element in the array corresponds to the first storage unit, a value of the xth element indicates the second storage unit, and x is a positive integer.

In the embodiment of the application, the message segments stored in the first storage unit and the message segments stored in the second storage unit are associated in an array mode, so that the mode of recording the information is simplified.

In a second aspect, a memory is provided, where the memory includes a controller and a first bank, where the first bank includes a first bank unit, the first bank unit includes a plurality of storage units, and the controller is configured to receive a read request, where the read request carries a storage address of a first packet fragment to be read; the controller is used for determining a storage unit for storing the first message segment according to the storage address; the controller is configured to read the first packet fragment from the storage unit.

In a possible implementation manner, the first bank includes a plurality of sub-banks, each sub-bank includes at least one storage unit, the plurality of sub-banks respectively include a plurality of storage units included in the first bank unit, and the plurality of sub-banks correspond to the plurality of storage units included in the first bank unit one to one; the controller of the bank is configured to determine a storage unit for storing the first packet fragment according to the storage address, and includes: the controller is used for selecting a first sub-bank from the plurality of sub-banks according to the storage address; and selecting the first memory cell from at least one memory cell included in the first sub-bank according to the memory address.

In a possible implementation manner, the controller includes a plurality of idle address pool controllers FAPC, the plurality of FAPCs correspond to the plurality of sub-banks one by one, and each FAPC records an address of a storage unit in an idle state in a corresponding sub-bank.

In a possible implementation manner, the first packet segment is a segment in a first packet unit, the first packet unit further includes a second packet segment, and the controller obtains information indicating that the packet segment stored in the first storage unit and the packet segment stored in the second storage unit are adjacent packet segments in a packet.

In a possible implementation manner, the information is represented by an array, an element sequence number of an xth element in the array corresponds to the first storage unit, a value of the xth element indicates the second storage unit, and x is a positive integer.

In a third aspect, a memory is provided, where the memory includes a controller and a first bank, where the first bank includes a first bank unit, the first bank unit includes a plurality of storage units, and the controller is configured to receive a release request, where the release request carries a storage address of a first storage unit that is requested to be released; the controller is used for determining the first storage unit according to the storage address; the controller is used for recording that the first storage unit is in an idle state.

In a possible implementation manner, the first bank includes a plurality of sub-banks, each sub-bank includes at least one storage unit, the plurality of sub-banks respectively include a plurality of storage units included in the first bank unit, and the plurality of sub-banks correspond to the plurality of storage units included in the first bank unit one to one; the controller is configured to determine the first storage unit according to the storage address, and includes: the controller is used for selecting a first sub-bank from the plurality of sub-banks according to the storage address; and selecting the first memory cell from at least one memory cell included in the first sub-bank according to the memory address.

In a possible implementation manner, the controller includes a plurality of free address pool controllers FAPCs, the plurality of FAPCs are in one-to-one correspondence with the plurality of sub-banks, each FAPC records an address of a storage unit in an idle state in a corresponding sub-bank, and the controller is configured to record that the first storage unit is in an idle state, and includes: the controller adds the address of the first storage unit to the FAPC corresponding to the first sub-bank.

In a possible implementation manner, the first packet segment is a segment in a first packet unit, the first packet unit further includes a second packet segment, the controller is configured to determine to store a second storage unit according to the first storage unit and information, and the information indicates that the packet segment stored in the first storage unit and the packet segment stored in the second storage unit are adjacent packet segments in a packet; the controller is used for recording that the second storage unit is in an idle state.

In the embodiment of the application, the first storage unit and the second storage unit are associated through information, the message segment stored in the first storage unit and the message segment stored in the second storage unit are indicated to be adjacent message segments in a message, and the information is stored in the controller, so that the controller can release a plurality of storage units corresponding to the message according to the information when the storage units are released, and the efficiency of releasing the storage units is improved.

In a possible implementation manner, the information is represented by an array, an element sequence number of an xth element in the array indicates the first storage unit, a value of the xth element indicates the second storage unit, and x is a positive integer.

In a fourth aspect, a method of performing a write operation by a memory is provided, comprising one or more method steps of the first aspect.

In a fifth aspect, a method of performing a read operation of a memory is provided, comprising one or more of the method steps of the second aspect.

In a sixth aspect, there is provided a method of performing a release operation for a memory, comprising one or more method steps of the third aspect.

In a seventh aspect, a memory is provided, in which a controller includes an input/output port processor and a memory. The processor is used for controlling the input and output ports to send and receive signals, the memory is used for storing a computer program, and the processor is used for calling and running the computer program from the memory so as to enable the memory to carry out the method in the aspects.

In an eighth aspect, there is provided a computer program product comprising: computer program code which, when run on a computer, causes the computer to perform the method of the above-mentioned aspects.

It should be noted that, all or part of the computer program code may be stored in the first storage medium, where the first storage medium may be packaged together with the processor or may be packaged separately from the processor, and this is not specifically limited in this embodiment of the present application.

In a ninth aspect, a computer-readable medium is provided, which stores program code, which, when run on a computer, causes the computer to perform the method in the above aspects.

Drawings

Fig. 1 is a schematic architecture diagram of a network switching apparatus.

Fig. 2 is a diagram of the architecture of a message buffer 200.

Fig. 3 shows a schematic block diagram of the architecture of a bank.

FIG. 4 is a schematic flow chart diagram of a method for performing a write operation by a memory according to an embodiment of the present application.

FIG. 5 is a schematic diagram illustrating a division of memory cells.

Fig. 6 is a schematic diagram of a controller according to an embodiment of the present application.

Fig. 7 is a schematic diagram of a position of a message segment in a message according to an embodiment of the present application.

Fig. 8 shows a schematic diagram of a storage manner of the index relationship in the embodiment of the present application.

Fig. 9 is a schematic diagram illustrating a storage manner of the index relationship in the embodiment of the present application.

FIG. 10 is a flowchart of a method for performing a read operation of a memory according to an embodiment of the present application.

FIG. 11 is a flowchart of a method for performing a release operation of a memory according to an embodiment of the present application.

Fig. 12 is a schematic block diagram of a controller of another embodiment of the present application.

Detailed Description

The technical solution in the present application will be described below with reference to the accompanying drawings.

For ease of understanding, the architecture of a network device to which the embodiments of the present application are applicable will be described with reference to fig. 1. Fig. 1 is a schematic architecture diagram of a network switching apparatus. The network switching device 100 shown in fig. 1 includes an ingress Media Access Control (MAC) 110, an upstream packet processor (IPP) 120, a switch buffer (SWB) 130, an downstream packet processor (EPP) 140, and an egress MAC 150. The SWB130 includes an Admission Control (AC) module 131, a Queue Management (QM) module 132, a Scheduler (SC) 133, and a packet buffer PB 134.

After a packet (packet) enters the network switching device 100, the ingress MAC110 segments the packet into a plurality of packet segments. IPP 120 forwards the plurality of packet fragments, which are forwarded to SWB 130. The AC 131 in the SWB130 is responsible for checking whether the packet unit satisfies the admission condition, and if the admission condition is satisfied, the packet unit is allowed to be cached in the PB 134. Accordingly, the QM module 132 is responsible for maintaining control information of multiple message fragments of a message, so that the message fragments can be subsequently forwarded according to the control information. If the admission condition is not satisfied, the message fragment can be discarded.

If the message fragment needs to be read from the message buffer, the SC 133 is responsible for scheduling a read request for requesting reading of the message fragment from the QM module 132 to dequeue and send the dequeue to the PB134, and after receiving the read request, the PB134 sends the message fragment to the EPP 140 according to the read request, and then the message fragment read in the egress MAC module 150 is reassembled into a complete message and continues to be forwarded.

The PB134 of fig. 1 is described in detail below in conjunction with fig. 2. Fig. 2 is a diagram of the architecture of a message buffer 200. It should be understood that although PB134 uses a different number than PB200, it may refer to the same device. PB200 shown in fig. 2 includes an Input crossbar (IXB) 210, an Output crossbar (OXB) 220, and a bank 230. Wherein IXB is used from W₁To W_PAnd forwarding the message fragments received by the p write input ports to the target bank so as to cache the message fragments by the target bank. The OXB is used for transmitting the message fragments read from the target bank to the R₁To R_qAnd q output ports are totally q, wherein p and q are positive integers. The bank230 is used for providing a buffer space for the message fragment.

The specific structure of the bank230 can be seen in fig. 3. Fig. 3 shows a schematic block diagram of the architecture of a bank. The bank230 shown in fig. 3 includes a controller 231 and a bank memory 232.

And a bank memory 232 for providing a storage space for the messages. The bank memory 232 is divided into one or more bank units 233 of the same bit width, e.g. bank unit 1 to bank unit b, each for storing one message fragment.

The controller 231 is configured to allocate a bank unit to the to-be-written message segment and determine the bank unit where the to-be-read message segment is located.

It should be noted that the controller 231 may be integrated with the bank memory 232 into a bank, which is also called a bank controller. Or may be two separate devices from the bank memory 232, which are used to control and manage the storage resources in the memory, and this embodiment of the present application is not limited to this.

Optionally, the controller 231 may include a Free Address Pool Controller (FAPC), where the FAPC records a bank unit in an idle state in a memory in a stack, and the bank unit in the idle state refers to a bank unit capable of storing a message fragment, and specifically includes two cases: in the first case, the packet fragments stored in the bank unit have already been forwarded to the target node, and the bank unit is in an idle state at this time. Or, in the second case, the bank unit does not originally store the message fragment, and the bank unit is in an idle state at this time.

For example, if the bank cells in the memory in the idle state are bank cell 1, bank cell 3, and bank cell b, the addresses recorded in the FAPC are the address (or "offset") offset1 of bank cell 1, the address offset3 of bank cell 3, and the address offset b of bank cell b, respectively. If a message fragment is to be written, the FAPC may pop up (pop) an address of a bank unit for storing the message fragment.

As can be seen in the bank shown in fig. 3, the memory 232 is divided into one or more bank units having the same bit width, and the address of the bank unit in an idle state is recorded in the FAPC. Due to the data structure of the FAPC, each FAPC can only pop up one bank unit in an idle state and is only used for storing one message fragment. However, the size of the message is usually not an integer multiple of the capacity of the bank unit, and the bit width of the last generated message fragment is usually much smaller than the capacity of the bank unit among the multiple message fragments obtained by performing segmentation processing on the message according to the capacity of the bank unit, and at this time, the last generated message fragment still needs to occupy one whole bank unit, which causes the storage space in the bank unit to be wasted, and reduces the utilization rate of the storage space. For example, as shown in fig. 3, the size of one packet is 129B, the capacity of a bank unit in a bank is 128B, and the packet is segmented according to the capacity of the bank unit, so that two packet fragments can be obtained, where the size of a packet fragment 1 is 128B, and the size of a packet fragment 2 is 1B, the packet fragment 1 is stored in the bank unit 1, and the packet fragment 2 is stored in the bank unit 2, and then for the bank unit 2, only the storage space of 1B is used for storing the packet fragment 2 (see the shaded portion in fig. 3), and the remaining storage space of 127B is wasted.

In order to avoid the problems and improve the utilization rate of storage space in the bank, the application provides a new bank and provides a method for writing messages and reading messages and releasing storage resources based on the new bank. As will be described in detail below in conjunction with fig. 4-11.

It should be noted that the size (or bit width) of the message fragment in the embodiment of the present application may be smaller than or equal to the message fragment in the prior art, that is, the message fragment stored in the bank unit in the foregoing. For the convenience of distinction, when the technical solution of the embodiment of the present application is introduced below, a message segment in the prior art is referred to as a "packet cell", and a message segment related to the embodiment of the present application is still referred to as a message segment. That is, the "message unit" referred to hereinafter occupies the storage space of the entire bank unit, and the "message fragment" occupies the storage space of the entire bank unit.

FIG. 4 is a schematic flow chart diagram of a method for performing a write operation by a memory according to an embodiment of the present application. The memory comprises a controller and a first bank, wherein the first bank comprises a first bank unit, the first bank unit comprises a plurality of memory units, and the method comprises steps 410 to 430.

It should be understood that the memory may be the PB shown in fig. 2, or a memory for buffering messages in the PB, and may include one or more banks. The first bank may be any bank in the memory, and the specific structure thereof may be as shown in fig. 3. It should also be understood that the first bank includes one or more bank units, and the first bank unit may be any one of the bank units in the first bank.

It should also be understood that the first bank unit may be any one of the first bank units, and the first bank unit includes a plurality of memory cells, and it is understood that each bank unit in the first bank unit is divided into a plurality of memory cells in advance. Optionally, the capacities of the plurality of memory cells included in each bank unit may be the same or different, and this is not limited in this embodiment of the application.

The controller receives a write request 410 requesting to write to the first message segment.

The first message segment may be understood as obtained by dividing the valid data in the message according to the capacity of the storage unit, and the first message segment may be understood as all or part of the valid data in the message, and may also be understood as all or part of the valid data in the message unit.

The first message segment is all or part of valid data of the message unit, and it can be understood that, if the size of the message unit is smaller than or equal to the capacity of the storage unit after the message is divided into the message units, the message unit can be directly stored in the storage unit without further dividing the message unit, and at this time, the message segment may include all valid data in the message unit. If the size of the message unit is larger than the capacity of the storage unit after the message is divided into the message units, the message units need to be further divided according to the capacity of the storage unit, so that the bit width of the divided message fragments is smaller than or equal to the capacity of the storage unit.

In this embodiment of the present application, a message may be first divided into a plurality of message units in a message buffer (e.g., the ingress MAC110) according to the capacity of a bank unit, and then the message unit may be further divided into a plurality of message fragments in a controller (e.g., the controller 231) according to the capacity of a storage unit, so that it is ensured that before the message arrives at the bank, a data path from each module in an existing PB to the bank can be multiplexed according to the transmission mode of the message unit in the prior art. The method avoids the problem that the number of the message fragments is increased sharply after the message is directly divided into a plurality of message fragments, so that the existing path in the PB needs to be adjusted to match a large number of message fragments, and finally the complexity of the connection mode from each module in the PB to the data path before the bank is over-complicated.

Certainly, in order to reduce the number of times of message segmentation, the message may also be directly segmented into message segments according to the capacity of the storage unit, where the first message segment is all or part of the valid data of the message, and it can be understood that, if the size of the message is smaller than or equal to the capacity of the storage unit, the message may be directly stored in the storage unit without being segmented, and at this time, the message segment may include all the valid data in the message. If the size of the message is larger than the capacity of the storage unit, the message needs to be divided according to the capacity of the storage unit, so that the bit width of the divided message fragment is smaller than or equal to the capacity of the storage unit.

For the above reasons, in order to make the method of the embodiment of the present application better compatible with the existing SWB architecture, in the method of the embodiment of the present application described below, a plurality of message segments included in a message unit are generally described as an example, and it should be understood that the range of the message unit may be extended to a message, and the flow of the method is similar to that described below, as long as the message unit is extended to a message, and for brevity, detailed description is omitted.

The controller selects a first memory cell from the plurality of memory cells of the first bank cell 420.

Optionally, the plurality of storage units of the first bank unit correspond to a plurality of identifiers, and step 420 may include the controller selecting a first identifier from the plurality of identifiers, where the first identifier is an identifier of the first storage unit. Specifically, the identifier may be an offset of a bank unit where the memory cell is located, an address of the memory cell, or other information that can identify the memory cell. The embodiments of the present application do not limit this.

It should be noted that the controller may randomly select the first memory cell from the first bank unit, and may also select a memory cell in an idle state from the first bank unit as the first memory cell in the manner described above, which is not limited in this embodiment of the present application. The manner of recording the memory cells in the idle state will be described in detail below, and for brevity, will not be described again.

430, the controller writes the first packet segment into the selected first storage unit, and the capacity of the first storage unit is greater than or equal to the size of the first packet segment.

It should be noted that, in the case of multiplexing the existing bank connection manner, the address bus corresponding to the selected first storage unit is not matched with the position of the first packet fragment in the packet unit, and at this time, the first packet fragment needs to be copied to the port corresponding to the address bus corresponding to the first storage unit through an Input Bus Shift (IBS) in the memory, so that the first packet fragment is written into the first storage unit through the address bus corresponding to the first storage unit.

For example, one message unit has a size of 256B, where the valid data bit width is 128B, i.e., the first message fragment is 128B and corresponds to the low 128B bits of the address bus, and assuming that the first memory unit corresponds to the high 128B bits of the address bus, the IBS shifts the valid data of the first message fragment from the low 128B of the address bus to the high 128B of the address bus according to the first memory unit corresponding to the address bus, so that the valid data is aligned with the first memory unit on the address bus.

There are many ways to divide the bank unit in the first bank into a plurality of memory cells, for example, each bank unit may be divided into a different number of memory cells. For another example, each bank cell is divided into the same number of memory cells, which is not specifically limited in this embodiment of the present application.

Fig. 5 is a schematic diagram illustrating a dividing manner of a memory cell according to an embodiment of the present application. It should be understood that the bank shown in fig. 5 may be an improvement based on the way the storage resources are partitioned in the bank shown in fig. 3. The bank shown in fig. 5 includes a plurality of memory cells arranged in a matrix including b rows and n columns, where b and n are positive integers. Each row (row) in the matrix multiplexes the division mode of the existing bank, the b-row storage units correspond to b bank units, namely bank1 to bank b, and the storage unit of each row belongs to one bank unit. The n columns of memory cells correspond to n sub-banks, namely, sub-bank 1 to sub-bank n, and different memory cells in each sub-bank belong to different rows, or different memory cells in each sub-bank belong to different bank units.

Accordingly, based on the bank described in fig. 5, the memory cell can be uniquely determined by one bank cell and a sub-bank. For example, the offset of the bank unit can be multiplexed by the memory cells belonging to the same bank unit in the n sub-banks, that is, the offset (offset) of the bank unit 1 is offset1, and the offsets of the memory cells belonging to the bank unit 1 in the n sub-banks are all offset 1. If the offset of the bank unit 2 is offset2, the offsets of the memory cells belonging to the bank unit 2 in the n sub-banks are all offset2, and so on, if the offset of the bank unit b is offset b, the offsets of the memory cells belonging to the bank unit b in the n sub-banks are all offset b, so that a unique memory cell can be determined based on the offset of each bank unit and the sub-banks.

It should be understood that the above offset is only one way to indicate a bank unit, and the way to indicate a bank unit in the prior art is multiplexed, so that the compatibility with the prior art is better. The embodiment of the present application does not limit the way of representing the bank cells, and for example, a unique row ID may be configured for different bank cells.

It should also be understood that, the above-mentioned unique identification of one storage unit by combining the offset and the identifier of the sub-bank is beneficial to reducing the number of identifiers for identifying the storage unit and facilitating the quick location of the storage unit, compared with the unique identifier corresponding to each storage unit. Of course, different offsets may be configured for different memory cells, so that one memory cell can be uniquely identified by only the offset, which is beneficial to simplify the complexity of representing the memory cells in the bank although the number of offsets is increased.

Optionally, the capacity of the memory cell in each sub-bank in the bank may be the same, and the capacities of the memory cells in at least two sub-banks in the bank may be different. The embodiments of the present application do not limit this.

Based on the dividing manner of the memory cells shown in fig. 5, the foregoing step 420 may include the controller selecting a first sub-bank from the plurality of sub-banks; and selecting the first memory cell from at least one memory cell included in the selected first sub-bank.

Optionally, the controller selecting the first sub-bank from the plurality of sub-banks includes the controller selecting the first sub-bank from a plurality of sub-banks in a non-full state. A sub-bank in a non-full state includes one or more memory cells in an idle state.

It should be noted that, in the process of selecting the first storage unit, the controller may position the first storage unit according to the sub-bank (i.e., the first sub-bank) and the bank unit (i.e., the first bank unit), and the controller selects the order of the first sub-bank and the first bank.

In the process of selecting the first memory cell by the controller described above, the first memory cell can be selected from the memory cells in the idle state, and thus, the controller needs to record the memory cells in the idle state in the bank. In a possible implementation manner, the controller may include a plurality of FAPCs (including a first FAPC), each sub-bank corresponds to one FAPC, and each FAPC records a storage unit in an idle state in the corresponding sub-bank.

Fig. 6 is a schematic diagram of a controller according to an embodiment of the present application. The controller shown in fig. 6 includes n FAPC, and FAPC1 to FAPC n, where each FAPC corresponds to one sub-bank, and records a storage unit in an idle state in the corresponding sub-bank. The FAPC1 is used to record the storage unit in the idle state in the sub-bank 1, the FAPC2 is used to record the storage unit in the idle state in the sub-bank 2, and so on, the FAPC n is used to record the storage unit in the idle state in the sub-bank n.

Accordingly, step 420, comprises: the controller is configured to select an address of a first storage unit from addresses of storage units recorded in a first FAPC of the multiple FAPCs, where the first FAPC corresponds to the first sub-bank.

It should be noted that the FAPC may record the address in the idle state in the form of a stack, and may also record the address in the idle state in the form of an array, which is not limited in this embodiment of the present application.

It should be further understood that, the above-mentioned corresponding to one FAPC for each sub-bank in the bank is only one possible implementation manner of managing the storage unit in the idle state through the FAPC, and a plurality of FAPCs may be further set in the controller, where each FAPC is used to manage the storage unit in the idle state in one bank unit, or one FAPC may also be used to manage the storage units in the idle state in a plurality of sub-banks, which is not limited in this embodiment of the present application.

In this embodiment of the present application, the controller manages the storage units in the idle state in the multiple sub-banks through the multiple FAPCs, so that when there are multiple message fragments to be written in, the multiple FAPCs can correspondingly pop up the storage unit in the idle state for each of the multiple message fragments in parallel, so as to store the corresponding message fragment, which is beneficial to reducing the time delay for storing the message fragment. When the controller manages a plurality of sub-banks in the bank through one FAPC, if a plurality of message fragments to be written are provided, the plurality of message fragments need to wait for the FAPC to eject the storage units in an idle state for the message fragments one by one. Of course, the controller manages a plurality of sub-banks through one FAPC, which is beneficial to reducing the number of FAPCs in the controller, so as to reduce the cost.

After the message fragment of the message unit is written into the memory unit, the memory address of the message unit needs to be fed back to the QM module in the SWB, so that the message unit can be read through the memory address in the following. In the embodiment of the present application, since one message unit may be divided into a plurality of message segments and written into a plurality of memory units, the memory address of the message unit needs to include addresses of the plurality of memory units. However, it is common to arrange a plurality of QM modules in an SWB to manage the storage of messages in the memory, that is, the addresses of message units need to be fed back to the plurality of QM modules, and if the storage addresses of message units include the storage addresses of a plurality of storage units, the storage space of each QM module for storing the storage addresses of message units is increased. In order to reduce the storage space of the storage address of each QM module for storing the message unit, the embodiment of the present application provides a new storage address representation manner, and the storage address of the message unit may be composed of three parts, namely, a bank identifier, a sub-bank identifier, and a position relationship identifier of a message fragment.

The bank identifier is used to indicate a bank to which the packet unit is written, and may be, for example, a bank ID.

The sub-bank identifier is used to indicate the sub-bank into which the packet unit is written, and specifically may correspond to the state of each sub-bank through a plurality of identifier bits. For example, n sub-banks may correspond to n identification bits one to one, and when a value of an identification bit is 1, it indicates that a message segment is stored in the sub-bank corresponding to the identification bit, and when the value of the identification bit is 0, it indicates that the message segment is not stored in the sub-bank corresponding to the identification bit.

For example, a sub-bank is identified as

The sub-bank identifier comprises n identifier bits, the n identifier bits respectively correspond to a sub-bank 1 to a sub-bank n from left to right, when the identifier bit takes a value of 1, it indicates that the sub-bank corresponding to the identifier bit stores a message fragment, and when the identifier bit takes a value of 0, it indicates that the sub-bank corresponding to the identifier bit does not store a message fragment, and then the sub-bank identifier is the sub-bank identifier

The identifier stores message fragments in the sub-bank 1 and the sub-bank n.

It should be noted that the n sub-banks may correspond to the n flag bits one to one, may indicate that the n flag bits respectively correspond to the sub-bank 1 to the sub-bank n in a left-to-right sequence, may also indicate that the n flag bits respectively correspond to the sub-bank 1 to the sub-bank n in a right-to-left sequence, may also randomly correspond the n sub-banks and the n flag bits, and record a final corresponding relationship between the flag bits and the sub-banks, which is not limited in this embodiment of the present application.

The position relation mark of the message fragment is used for indicating the position of each message fragment in the message unit, and the position of each message fragment in the message unit can be indirectly indicated by the sequence of a plurality of storage units for storing the message fragment determined by the controller. The order of determining the storage units can be defined by the index relationship among the storage units.

The position relation of the message segments in the message unit can be refined into information of two layers, namely the message segments are adjacent in the message unit, and the message segments are in the sequence of the message unit. The two layers of information may be indicated by a position relationship of the message segments, and may also be indicated by two independent information respectively, which is not specifically limited in this embodiment of the present application.

It should be noted that, because the storage address only carries the location relationship identifier of the message segment, correspondingly, the location relationship in the message unit needs to be maintained by the controller, so that the location relationship in the message unit can be determined according to the location relationship identifier of the message segment in the storage address in the process of reading the message. In the following description, the process of determining the sequence of the storage unit will be introduced together in the process of describing the positional relationship in the message unit, so as to better understand the method of the embodiment of the present application. And the process of determining the sequence of the storage units in the actual execution of the scheme is executed in the process of reading the message according to the storage address carried in the reading request and releasing the storage resources.

The message unit is divided into a first message segment and a second message segment, and the first message segment is located before the second message segment, the controller may determine a first storage unit for storing the first message segment and then determine a second storage unit for storing the second message segment. The controller determines the sequence of the plurality of storage units and can control the sequence through the index relationship among the plurality of storage units. For example, when the controller can index the second storage unit according to the first storage unit, the controller needs to determine the first storage unit before the controller can index the second storage unit according to the first storage unit.

It should be noted that the controller determines the sequence of the plurality of storage units, and it may also be understood that the controller links the plurality of storage units according to the sequence of the plurality of storage units, so that the memory for storing the index relationship may be referred to as an Address Linker (AL). Accordingly, the index relationship between the storage units is represented using AL.

Specifically, the index relationship between the plurality of storage units storing the message unit may be represented by an index relationship between every two storage units. For convenience of distinction, when the method of the embodiment of the present application is described below, the "index relationship" indicates the association relationship between all the storage units storing the packet unit, and the "sub-index relationship" indicates the association relationship between two storage units of the plurality of storage units storing the packet unit. That is, the index relationships among the m storage units may include m-1 sub-index relationships, where m is a positive integer greater than or equal to 1.

It should be noted that, if the message unit is stored in 2 storage units, the index relationship and the sub-index relationship are the same association relationship between the storage units.

For example, the message unit includes a first message segment, a second message segment, and a third message segment, and the positional relationship among the first message segment, the second message segment, and the third message segment can be as shown in fig. 7, that is, the first message segment is adjacent to the second message segment, the second message segment is adjacent to the third message segment, and the position of the first message segment in the message unit is before the position of the second message segment, and the position of the second message segment in the message unit is before the position of the third message segment.

Assuming that a first packet segment is stored in a memory cell 1 in the first sub-bank, an offset of the memory cell 1 in the first sub-bank is offset1, a second packet segment is stored in a memory cell 2 in the second sub-bank, an offset of the memory cell 2 in the second sub-bank is offset2, a third packet segment is stored in a memory cell 3 in the third sub-bank, and an offset of the memory cell 3 is offset3, two sub-index relationships are required to associate the 3 memory cells, where the sub-index relationship is denoted by AL, the first sub-index relationship is denoted by AL1[ offset1] ═ offset2, and the second sub-index relationship is denoted by AL2[ offset2] ═ offset 3.

It should be noted that the above-mentioned manner of indicating sub-index relationships AL1[ offset1] ═ offset2 and AL2[ offset2] ═ offset3 are merely one of the manners of indicating that are used for convenience of description, and in practical applications, the above-mentioned sub-index relationships may be indicated by a data structure such as a key value pair or an array that can indicate the above-mentioned logical relationships, and the present embodiment does not limit this.

If the sub-index relationship is represented by the data structure of the key-value pair, two key-value pair data may be recorded, where the offset of the first storage unit is a key (key), the offset of the second storage unit is a value (value), the offset of the second storage unit is a key, and the offset of the third storage unit is a value.

If the sub-index relationship is expressed by an array form, two data can correspond to the first storage unit through the x-th element in the first array by the element sequence number (x) of the x-th element in the array, and the value of the x-th element indicates the second storage unit. The first memory cell and the second memory cell may be located in the same sub-bank or in different sub-banks.

Alternatively, the value of the xth element may be the address of the second memory location, or an offset of the second memory location, or other information that may indicate the identity of the second memory location.

For example, array 1 includes 3 elements, (element a)₁(element b)₂And (element c)₃. The element numbers of the 3 elements in the array can be represented by subscripts, that is, the subscript of the element a is 1, and the element number of the element a is 1; the subscript of the element b is 2, and the element number of the element b is 2; the subscript of element c is 3 and the subscript of element c is 3. Assuming that the above array represents the index relationship of the memory cells in the sub-bank 1, and the sub-bank 1 includes 3 memory cells, the offset of memory cell 1 is offset1, the offset of memory cell 2 is offset2, and the offset of memory cell 3 is offset3, the element with the subscript 1 may correspond to memory cell 1 with the offset of offset1, the element with the subscript 2 may correspond to memory cell 2 with the offset of offset2, and the element with the subscript 3 may correspond to memory cell 3 with the offset of offset 3.

Correspondingly, the value element a of the element with the subscript of 1, and the element a is offset4, it can be determined that the memory cell 1 corresponds to the memory cell with the offset of offset 4; the subscript is the value element b of the element with 2, and the element b is offset5, it can be determined that the memory cell 2 corresponds to the memory cell with offset 5; the index of the element c with index 3 is the offset6, and the memory cell 3 with offset6 can be determined.

Based on the division of the memory cells shown in fig. 5, the memory cell with the offset amount of offset4, the memory cell with the offset amount of offset5, and the memory cell with the offset amount of offset6 need to be determined by combining the sub-bank flags in the memory address. If the offset of each storage unit in the bank is different, the position of the storage unit can be directly determined.

It should be understood that, the above list only describes that each memory unit is associated by the offset of the memory unit, and the offset may be replaced by a memory address of the memory unit, such as a physical address, which is not specifically limited in the embodiment of the present application.

It should be further understood that there are many ways to indicate the index relationship among the plurality of storage units storing the message unit, and this is not limited in this embodiment of the present application. For example, an index relationship between the plurality of storage units may also be represented by a data structure of one key value pair, and based on fig. 7, an address of the first storage unit may be used as a key, an address of the second storage unit may be used as a first value, and an address of the third storage unit may be used as a second value, where a sequence of two values in the key value pair may indicate positions of the message segments stored in the second storage unit and the third storage unit in the message unit.

Alternatively, the identifier of the position relationship of the message segment may directly use an offset of a storage unit in the message unit, where the first message segment is stored.

For example, in fig. 7, offset1 may be used as the identifier of the position relationship of the message segment, and accordingly, after the offset1 of the storage unit 1 is determined, the offset2 may be determined according to offset1 and AL1[ offset1] ═ offset2, the offset3 may be determined according to offset2 and AL2[ offset2] ═ offset3, and finally, the storage unit 1, the storage unit 2, and the storage unit 3 may be determined by combining the offset and the sub-bank identifier. In the process of determining the offset of each storage unit, the precedence order of the positions of the message segments in each storage unit in the message unit may also be obtained according to the precedence relationship of the offsets of the storage units, that is, the precedence order determined by the 3 storage units is: the storage unit 1, the storage unit 2 and the storage unit 3 are respectively, and accordingly, the position relationship among the message segments is that the first message segment is adjacent to the second message segment, the second message segment is adjacent to the third message segment, the position of the first message segment in the message unit is before the position of the second message segment, and the position of the second message segment in the message unit is before the position of the third message segment.

It should be noted that, the determining the sequence of the storage unit indirectly indicates the position of the message segment in the message unit, and may include that the position of the message segment stored in the storage unit in the message unit is farther back as the time for determining the storage unit increases. Or as the time for determining the storage unit increases, the message segment stored in the storage unit is positioned farther forward in the message unit. The embodiments of the present application do not limit this.

In the embodiment of the application, the sequence of the storage units is determined according to the index relation specification of the storage units so as to indirectly indicate the positions of the message segments in the message units, thereby avoiding the situation that the controller needs to store additional information to record the positions of the message segments in the message units, and being beneficial to saving storage resources. Of course, if the recorded individual information indicates the position of the message segment in the message unit, the position of the message segment in the message unit may not be indirectly indicated through the index relationship between the storage units.

The index relationship among the storage units can be stored in two ways, which will be described below with reference to fig. 8 to 9. The controller in the memory shown in fig. 8 or fig. 9 includes a plurality of address linkers, each address linker corresponding to one sub-bank for recording the index relationship of the memory cells related to the memory cells in the sub-bank.

In a first storage mode, when the index relationships among the plurality of storage units storing the message unit include a plurality of sub-index relationships, the plurality of sub-index relationships are respectively stored in corresponding address linkers, wherein the corresponding address linkers are address linkers corresponding to sub-banks where the storage units serving as indexes in the sub-index relationships are located.

For example, fig. 8 shows a schematic diagram of a storage manner of the index relationship in the embodiment of the present application. The controller 810 shown in fig. 8 includes a first address linker to a third address linker, wherein the first address link corresponds to the sub-bank 1, the second address linker corresponds to the sub-bank 2, and the third address linker corresponds to the sub-bank 3 (not shown in the figure). Assuming that the first packet fragment in fig. 7 is stored in the memory cell 1 in the first sub-bank, the offset of the memory cell 1 in the first sub-bank is offset1, the second packet fragment is stored in the memory cell 2 in the second sub-bank, the offset of the memory cell 2 in the second sub-bank is offset2, the third packet fragment is stored in the memory cell 3 in the third sub-bank, and the offset of the memory cell 3 is offset3, the sub-index relationships associated with the 3 memory cells are: AL1[ offset1] ═ offset2, AL2[ offset2] ═ offset3, where the offset of memory cell 2 is determined in AL1 with the offset of memory cell 1 as the index, and therefore AL1 is stored into the first address linker. The offset of the memory cell 3 is determined in AL2 with the offset of the memory cell 2 as an index, and therefore AL2 is stored into the second address linker.

In the embodiment of the application, different index relationships are respectively stored in the corresponding address linkers, so that the load of each address linker is balanced, and the storage resources in the address linkers are reasonably utilized.

And a second storage mode is that the index relations among a plurality of storage units for storing the message units are stored into corresponding address linkers, wherein the corresponding address linkers are the address linkers corresponding to the sub-bank where the first storage unit serving as the index in the index relations is located.

It should be noted that the index relationship among the storage units may include one sub-index relationship or a plurality of sub-index relationships. Since the sub-index relationship may be denoted by AL, if the index relationship between the plurality of storage units includes a plurality of sub-index relationships, the plurality of sub-index relationships may be referred to as "AL group" (ALgroup).

For example, fig. 9 shows a schematic diagram of a storage manner of the index relationship in the embodiment of the present application. The controller 910 shown in fig. 9 includes a first address linker to a third address linker, where the first address linker corresponds to the sub-bank 1, the second address linker corresponds to the sub-bank 2, and the third address linker corresponds to the sub-bank 3. Assuming that the first packet fragment in fig. 7 is stored in the memory cell 1 in the first sub-bank, the offset of the memory cell 1 in the first sub-bank is offset1, the second packet fragment is stored in the memory cell 2 in the second sub-bank, the offset of the memory cell 2 in the second sub-bank is offset2, the third packet fragment is stored in the memory cell 3 in the third sub-bank, and the offset of the memory cell 3 is offset3, the sub-index relationships associated with the 3 memory cells are: AL1[ offset1] ═ offset2, AL2[ offset2] ═ offset3, where AL1 and AL2 are an AL group, and the first memory cell in the AL group as an index is memory cell 1, then the AL group is stored in the first address linker, i.e. the first address linker, corresponding to the sub-bank where the memory cell 1 is located.

In the embodiment of the present application, the index relationship belonging to an AL group is stored in an address linker, so that when the index relationship between the storage units storing the packet units is read later, the index relationship can be read in an address linker by taking the AL group as a unit, thereby simplifying the flow of reading the index relationship.

The following describes, with reference to a specific example, a method for writing a message segment into a memory based on two storage manners shown in fig. 8 and fig. 9, respectively. It should be understood that the above-mentioned "size of message fragment" and "capacity of storage unit" can be embodied by bit width.

Assume that, in the memory described based on fig. 8, among the 4 sub-banks included in banka, the bit width of each sub-bank is wB. There are 3 non-full (non-full) sub-banks and 1 full (full) sub-bank in the bank, where the sub-bank 3 is a full sub-bank, i.e., there are no memory cells in the sub-bank 3 that are in an idle state. The other 3 sub-banks that are not full are sub-bank 1, sub-bank 2, and sub-bank 4, respectively. And a message unit with a valid data bit width of 3wB needs to be written into banka.

Step 1, the controller divides the message unit with the bit width of 3wB into 3 message segments with the bit width of wB, a first message segment, a second message segment and a third message segment.

And 2, the controller selects 3 sub-banks for storing the message units, namely sub-bank 1, sub-bank 2 and sub-bank 4 according to the effective bit width 3wB of the message units.

And step 3, popping up an offset of a storage unit in an idle state respectively by the FAPC1 corresponding to the sub-bank 1, the FAPC2 corresponding to the sub-bank 2 and the FAPC4 corresponding to the sub-bank 4.

Specifically, the offset of popping one storage unit in an idle state by FAPC1 corresponding to sub-bank 1 is offset1, the offset of popping one storage unit in an idle state by FAPC2 corresponding to sub-bank 2 is offset2, the offset of popping one storage unit in an idle state by FAPC4 corresponding to sub-bank 4 is offset4, and the offset corresponds to storage unit 4.

It should be noted that, after step 3 is executed to determine the storage unit corresponding to each message fragment, the storage unit storing the message fragment needs to be fed back to the input bus shifter IBS, so that the IBS adjusts the message fragment to be transmitted on the data bus corresponding to the storage unit according to the correspondence between the message fragment and the storage unit.

And 4, writing the first message segment, the second message segment and the third message segment into the storage unit 1, the storage unit 2 and the storage unit 3 by the controller.

In step 5, the controller records the index relationship AL1[ offset1] ═ offset2 between the memory cells in the address link corresponding to the sub-bank 1, and records the index relationship AL2[ offset2] ═ offset4 between the memory cells in the address link corresponding to the sub-bank 2.

And 6, the PB where the banka is located returns the storage address of the message unit to the QM.

The storage address is a +1101+ offset1, where a is the bank ID of the banka storing the message unit. 1101 indicates that the sub-bank 1, the sub-bank 2, and the sub-bank 4 participate in storing the message segment of the message unit in the current bank, and the sub-bank 3 does not store the message segment of the message unit. offset1 represents the offset of the memory location storing the first message segment.

It should be noted that, the execution sequence among the above step 4, step 5 and step 6 is not specifically limited in the embodiment of the present application, and the step 4, step 5 and step 6 may be executed simultaneously, or the step 6 may be executed before the step 4 is executed.

Assume that in the memory described based on fig. 9, among the 4 sub-banks included in banka, the bit width of each sub-bank is wB. There are 3 non-full (non-full) sub-banks and 1 full (full) sub-bank in the bank, where the sub-bank 3 is a full sub-bank, i.e., there are no memory cells in the sub-bank 3 that are in an idle state. The other 3 sub-banks that are not full are sub-bank 1, sub-bank 2, and sub-bank 4, respectively. And a message unit with a valid data bit width of 3wB needs to be written into banka.

Step 5, the controller records an AL group corresponding to the message unit in an address linker corresponding to the sub-bank 1: AL1[ offset1] ═ offset2, and AL2[ offset2] ═ offset 4.

The method for performing the write operation by the memory according to the embodiment of the present application is described above with reference to fig. 1 to 9, and the method for performing the read operation by the memory according to the embodiment of the present application is described below with reference to fig. 10. The method shown in fig. 10 corresponds to the method shown in fig. 4, and the architecture of the memory, the manner of representing the memory address, the manner of storing the index relationship, and the manner of representing the index relationship to which the method shown in fig. 10 is applied are also as described above. For brevity, detailed descriptions are omitted below, and differences from the above-described methods are emphasized.

FIG. 10 is a flowchart of a method for performing a read operation of a memory according to an embodiment of the present application. Fig. 10 shows a controller and a first bank, the first bank includes a first bank unit, the first bank unit includes a plurality of memory cells, and the method includes steps 1010 to 1030.

1010, the controller receives a read request, where the read request carries a storage address of a first message segment to be read.

It should be understood that the first message segment may be the "first message segment" stored by the method shown in fig. 4, or may be different from the first message segment referred to in fig. 4.

And 1020, the controller determines a first storage unit for storing the first message segment according to the storage address.

1030, the controller is configured to read the first message fragment from the first storage unit.

Alternatively, based on the memory shown in fig. 5, the memory cell can be uniquely determined by the sub-bank and the bank cell, and then step 1020 includes: the controller determines a first sub-bank from the plurality of sub-banks according to the storage address; the controller determines the first memory cell from the memory cells contained in the first sub-bank according to the memory address.

It should be noted that, in the process of determining the memory cell, the sub-bank may be determined according to the memory address, and then the bank unit may be determined according to the memory address. The bank unit may be determined according to the storage address, and then the sub-bank may be determined according to the storage address, which is not limited in the embodiment of the present application.

In addition, other specific forms of the memory address can be referred to the above description, and are not described herein again.

Optionally, referring to fig. 6, the controller includes a plurality of idle address pool controllers FAPC, the plurality of FAPCs correspond to the plurality of sub-banks one by one, and each FAPC records an address of a storage unit in an idle state in a corresponding sub-bank.

Optionally, the first packet fragment is a packet fragment in a first packet unit, the first packet unit further includes a second packet fragment, the controller obtains location relationship information used for indicating a location relationship between the first packet fragment and the second packet fragment, the location relationship information indicates that the packet fragment in the first storage unit in the first packet is located before the packet fragment in the second storage unit and is adjacent to the packet fragment in the second storage unit, and the controller obtains the first packet unit according to the first packet fragment, the second packet fragment, and the location relationship information. It should be noted that the position relationship information may include information indicating that the message segment stored in the first storage unit and the message segment stored in the second storage unit are adjacent message segments in one message.

It should be noted that, the controller obtains the first packet unit according to the first packet segment, the second packet segment, and the positional relationship information, and may adjust the position of the packet segment on the address bus by an Output Bus Shifter (OBS) in the bank, so that the position of each packet segment of the packet unit on the address bus is restored to the position of the packet unit when entering the PB, and finally, the adjusted packet unit is sent to the read port through the OXB.

The following describes a method for reading a message fragment from a memory, with reference to fig. 8 and 9, respectively, in conjunction with a specific example.

Assume that in the memory described based on fig. 8, a bank ka includes 4 sub-banks and 3 bank units, and the controller records an index relationship AL1[ offset1] ═ offset2 between the memory units in the address link corresponding to the sub-bank 1, and records an index relationship AL2[ offset2] ═ offset4 between the memory units in the address link corresponding to the sub-bank 2.

Step 1, the controller receives a read request, where the read request is used to request to read a packet unit, and the read request carries a storage address of the packet unit, which is a +1101+ offset1, where a is a bank ID of a bank ka storing the packet unit. 1101 indicates that the sub-bank 1, the sub-bank 2, and the sub-bank 4 participate in storing the message segment of the message unit in the current bank, and the sub-bank 3 does not store the message segment of the message unit. offset1 represents the offset of the memory location storing the first message segment.

Step 2, the controller determines 1 the sub-bank storing the message unit and the offset of the memory unit storing the first message segment according to the memory address.

Step 3, the controller determines that the offset of the storage unit 2 storing the second message segment is offset2 according to offset1 and the index relationship AL1[ offset1] ═ offset 2; then, according to offset2 and AL2[ offset2] ═ offset4, it is determined that the offset of the memory cell 3 storing the third packet segment is offset 4.

Specifically, the controller obtains the index relationship AL1[ offset1] ═ offset2 from the address link corresponding to the sub-bank 1 according to the first offset amount offset1, and determines the second offset amount offset2 according to the obtained index relationship. Then, the controller obtains the index relationship AL2[ offset2] ═ offset4 in the address linker corresponding to the sub-bank 2 according to the second offset amount offset2, and determines that the third offset amount is offset4 according to the obtained index relationship.

And 4, the controller determines that 3 storage units for storing the message units are combined with the sub-bank for storing the message units and the offset of the storage unit determined by the index relationship: memory cell 1 with offset1 in sub-bank 1, memory cell 2 with offset2 in sub-bank 2, and memory cell 3 with offset4 in sub-bank 4.

And 5, reading the first message segment from the storage unit 1, reading the second message segment from the storage unit 2, and reading the third message segment from the storage unit 3 by the controller.

And 6, the controller determines the positions of the first message segment, the second message segment and the third message segment according to the sequence of the storage units and generates a message unit.

And 7, the controller feeds back the message unit. Specifically, the message unit is fed back to QM or EPP.

Assume that in the memory described based on fig. 9, a bank ka includes 4 sub-banks and 3 bank units, and the AL group recorded by the controller in the address link corresponding to the sub-bank 1 includes AL1[ offset1] ═ offset2, and AL2[ offset2] ═ offset 4.

In step 3, the controller obtains AL groups including AL1[ offset1] ═ offset2 and AL2[ offset2] ═ offset4 from the address link corresponding to the sub-bank 1 according to the first offset 1.

Specifically, the controller determines that the offset of the storage unit 2 storing the second packet segment is offset2 according to offset1 and the index relationship AL1[ offset1] — offset 2; then, according to offset2 and AL2[ offset2] ═ offset4, it is determined that the offset of the memory cell 3 storing the third packet segment is offset 4.

Generally, in order to improve the utilization rate of the storage unit, after the message segment stored in the bank is sent to the target device, the storage resource storing the message segment may be released, and the offset of the storage unit storing the message segment is pushed again into the FAPC of the controller to identify that the storage unit is in an idle state. The method for releasing the memory cell in the memory according to the embodiment of the present application is described below with reference to fig. 11.

The method shown in fig. 11 corresponds to the method shown in fig. 4, and the architecture of the memory, the manner of representing the memory address, the manner of storing the index relationship, and the manner of representing the index relationship to which the method shown in fig. 11 is applied are also as described above. For brevity, detailed descriptions are omitted below, and differences from the above-described methods are emphasized.

FIG. 11 is a flowchart of a method for performing a release operation of a memory according to an embodiment of the present application. The memory comprises a controller and a first bank, wherein the first bank comprises a first bank unit, the first bank unit comprises a plurality of memory cells, and the method comprises steps 1110 to 1130.

1110, the controller is configured to receive a release request, where the release request carries a storage address of a first storage unit that is requested to be released.

1120 and the controller is used for determining the first storage unit according to the storage address.

The controller is configured to record that the first memory cell is in an idle state 1130.

Optionally, referring to the memory shown in fig. 6, the first bank includes a plurality of sub-banks, each sub-bank includes at least one memory cell, the plurality of sub-banks respectively includes a plurality of memory cells included in the first bank, and the plurality of sub-banks correspond to the plurality of memory cells included in the first bank one-to-one, step 1120 includes: the controller selects a first sub-bank from the plurality of sub-banks according to the storage address; and selecting the first memory cell from at least one memory cell included in the first sub-bank according to the memory address.

Optionally, the controller includes a plurality of free address pool controllers FAPCs, the plurality of FAPCs correspond to the plurality of sub-banks one to one, and each FAPC records an address of a storage unit in an idle state in a corresponding sub-bank, step 1130 includes: the controller adds the address of the first storage unit to the FAPC corresponding to the first sub-bank.

Optionally, the first packet segment is a segment in a first packet unit, the first packet unit further includes a second packet segment, and the controller is configured to determine to store a second storage unit according to the first storage unit and information, where the information indicates that the packet segment stored in the first storage unit and the packet segment stored in the second storage unit are adjacent packet segments in a packet; the controller is used for recording that the second storage unit is in an idle state.

It should be noted that the information may be an index relationship between a plurality of storage units storing message units, which is described above, for details, see above.

Optionally, the information is represented by an array, an element sequence number (x) of an xth element in the array indicates the first storage unit, a value of the xth element indicates the second storage unit, and x is a positive integer.

In step 1, the controller receives a release request, where the storage address carried by the release request is a +1101+ offset 1.

Wherein, a is the bank ID of the banka storing the message unit. 1101 indicates that the sub-bank 1, the sub-bank 2, and the sub-bank 4 participate in storing the message segment of the message unit in the current bank, and the sub-bank 3 does not store the message segment of the message unit. offset1 represents the offset of the memory location storing the first message segment.

Step 2, the controller determines the sub-bank storing the message unit according to the storage address, and the first offset 1.

In step 3, the controller obtains the index relationship AL1[ offset1] ═ offset2 from the address link corresponding to the sub-bank 1 according to the first offset1, and determines the second offset2 according to the obtained index relationship.

Step 4, the controller obtains the index relationship AL2[ offset2] ═ offset4 in the address link corresponding to the sub-bank 2 according to the second offset2, and determines that the third offset is offset4 according to the obtained index relationship.

Step 5, the controller determines 3 memory cells to be released by combining the sub-bank indicated in the memory address and the offset determined by the index relationship as follows: memory cell 1 with offset1 in sub-bank 1, memory cell 2 with offset2 in sub-bank 2, and memory cell 3 with offset4 in sub-bank 4.

Step 6, the controller pushes the offset1 of the memory cell 1 into the FAPC corresponding to the sub-bank 1, pushes the offset2 of the memory cell 2 into the FAPC corresponding to the sub-bank 2, and pushes the offset bank4 of the memory cell 3 into the FAPC corresponding to the sub-bank 4.

Assuming that in the memory described based on fig. 9, the bank ka includes 4 sub-banks and 3 bank units, and the controller records the AL group in the address linker corresponding to the sub-bank 1 includes: AL1[ offset1] ═ offset2, and AL2[ offset2] ═ offset 4.

In step 3, the controller obtains the index relationship AL1[ offset1] ═ offset2 and AL2[ offset2] ═ offset4 from the address link corresponding to the sub-bank 1 according to the first offset 1.

Specifically, the controller determines the second offset amount offset2 from the first offset amount offset1 and AL1[ offset1] ═ offset2, and determines the third offset amount to be offset4 from the second offset amount offset2 and AL2[ offset2] ═ offset 4.

Step 4, the controller determines 3 memory cells to be released by combining the sub-bank indicated in the memory address and the offset determined by the index relationship as follows: memory cell 1 with offset1 in sub-bank 1, memory cell 2 with offset2 in sub-bank 2, and memory cell 3 with offset4 in sub-bank 4.

Step 5, the controller pushes the offset1 of the memory cell 1 into the FAPC corresponding to the sub-bank 1, pushes the offset2 of the memory cell 2 into the FAPC corresponding to the sub-bank 2, and pushes the offset bank4 of the memory cell 3 into the FAPC corresponding to the sub-bank 4.

The method of the embodiment of the present application is described in detail above with reference to fig. 1 to 11, and the structure of the controller of the embodiment of the present application is described below with reference to fig. 12. It should be noted that the controller may perform some or all of the above method steps, for example, the steps in fig. 4, fig. 10 and fig. 11, based on the hardware configuration shown below. For brevity, detailed descriptions are omitted here.

The controller 1200 may include a memory 1210, a processor 1220, and an input/output interface 1230, as shown in particular in fig. 12. Fig. 12 is a schematic block diagram of a controller of another embodiment of the present application. The controller 1200 shown in fig. 12 may include: memory 1210, processor 1220, input/output interface 1230. The memory 1210, the processor 1220 and the input/output interface 1230 are connected via an internal connection path, the memory 1210 is used for storing instructions, and the processor 1220 is used for executing the instructions stored in the memory 1220, so as to control the input/output interface 1230 to receive input data and information, output data such as operation results, and control the transceiver 1240 to transmit signals.

Alternatively, in the method shown in fig. 4, step 410 and step 430 may be performed by the controller through the input/output interface 1230, and step 420 may be performed by the controller through the processor 1220.

Alternatively, in the method shown in fig. 10, step 1010 and step 1030 may be performed by the controller through the input/output interface 1230, and step 1020 may be performed by the controller through the processor 1220.

Alternatively, in the method shown in fig. 11, step 1110 may be performed by the controller through the input/output interface 1230, and step 1020 and step 1130 may be performed by the controller through the processor 1220.

In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 1220. The method disclosed in the embodiments of the present application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in the processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 1210, and the processor 1220 reads the information in the memory 1210 and performs the steps of the above method in combination with the hardware thereof. To avoid repetition, it is not described in detail here.

It should be understood that in the embodiments of the present application, the processor may be a Central Processing Unit (CPU), and the processor may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will also be appreciated that in embodiments of the present application, the memory may comprise both read-only memory and random access memory, and may provide instructions and data to the processor. A portion of the processor may also include non-volatile random access memory. For example, the processor may also store information of the device type.

It should be understood that in the embodiment of the present application, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.

It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be read by a computer or a data storage device including one or more available media integrated servers, data centers, and the like. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a Digital Versatile Disk (DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A memory comprising a controller and a first bank, the first bank comprising a first bank cell, the first bank cell comprising a plurality of memory cells,

the controller is used for receiving a write request, and the write request is used for requesting to write in a first message segment;

the controller is configured to select a first memory cell from a plurality of memory cells of the first bank cell;

the controller is configured to write the first packet segment into the selected first storage unit, where a capacity of the first storage unit is greater than or equal to a size of the first packet segment;

the first bank comprises a plurality of sub-banks, each sub-bank comprises at least one storage unit, and the plurality of sub-banks correspond to a plurality of storage units contained in the first bank unit one by one;

the controller for selecting a first memory cell from a plurality of memory cells of the first bank cell includes:

the controller is used for selecting a first sub-bank from the plurality of sub-banks; and

selecting the first memory cell from at least one memory cell included in the selected first sub-bank.

2. The memory of claim 1, wherein the controller comprises a plurality of Free Address Pool Controllers (FAPCs), the plurality of FAPCs are in one-to-one correspondence with the plurality of sub-banks, and each FAPC records addresses of memory cells in an idle state in the corresponding sub-bank;

the controller is configured to select the first memory cell from at least one memory cell included in the selected first sub-bank, and the controller is configured to:

the controller is configured to select an address of a first storage unit from addresses of storage units recorded by a first FAPC among the multiple FAPCs, where the first FAPC corresponds to the first sub-bank.

3. The memory of claim 1 or 2, wherein the first message segment is a segment in a first message, the first message further comprising a second message segment, the memory comprising a second storage unit;

the controller is further configured to write the second message segment into the second storage unit, and the controller records information indicating that the message segment stored in the first storage unit and the message segment stored in the second storage unit are adjacent message segments in a message.

4. The memory of claim 3, wherein the information is represented as an array, an element number of an xth element in the array corresponds to the first storage location, a value of the xth element indicates the second storage location, x is a positive integer.

5. A method for performing a write operation on a memory, the memory comprising a controller and a first bank, the first bank comprising a first bank unit, the first bank unit comprising a plurality of memory cells, the method comprising:

the controller receives a write request, wherein the write request is used for requesting to write in a first message segment;

the controller selects a first memory cell from a plurality of memory cells of the first bank cell;

the controller writes the first message segment into the selected first storage unit, wherein the capacity of the first storage unit is larger than or equal to the size of the first message segment;

the controller selects a first memory cell from a plurality of memory cells of the first bank cell, including:

the controller selects a first sub-bank from the plurality of sub-banks; and

6. The method of claim 5, wherein the controller comprises a plurality of Free Address Pool Controllers (FAPCs), the plurality of FAPCs are in one-to-one correspondence with the plurality of sub-banks, and each FAPC records addresses of storage units in an idle state in the corresponding sub-bank;

the controller selects the first memory cell from at least one memory cell included in the selected first sub-bank, including:

the controller selects an address of a first storage unit from addresses of storage units recorded by a first FAPC in the FAPCs, wherein the first FAPC corresponds to the first sub-bank.

7. The method of claim 5 or 6, wherein the first message segment is a segment in a first message, the first message further comprising a second message segment, the method further comprising:

and the controller writes the second message segment into a second storage unit of the memory, and records information indicating that the message segment stored in the first storage unit and the message segment stored in the second storage unit are adjacent message segments in one message.

8. The method of claim 7, wherein the information is represented as an array, wherein an element number of an x-th element in the array corresponds to the first storage unit, a value of the x-th element indicates the second storage unit, and x is a positive integer.