CN111522753A

CN111522753A - SDRAM (synchronous dynamic random access memory) control method and system based on state machine

Info

Publication number: CN111522753A
Application number: CN201911263392.XA
Authority: CN
Inventors: 肖骁; 吕林洪; 陈新展
Original assignee: 709th Research Institute of CSIC
Current assignee: 709th Research Institute of CSIC
Priority date: 2019-12-11
Filing date: 2019-12-11
Publication date: 2020-08-11
Anticipated expiration: 2039-12-11
Also published as: CN111522753B

Abstract

The invention relates to the technical field of memory control, in particular to a Synchronous Dynamic Random Access Memory (SDRAM) control method and system based on a state machine. The method comprises the following steps: making a state machine data table; adding the state machine data table into an internal storage area; combining the state machine data table and related control signals together into a control logic of the SDRAM; after the SDRAM control logic is debugged, performing required read-write access operation by combining target data; the system comprises a state machine data table customizing module and an SDRAM controller; the SDRAM controller comprises a BUFF storage unit, a logic control unit and an interface control unit; the system of the embodiment of the invention executes the method, utilizes the internal storage resource of the FPGA to manufacture the corresponding state machine data table according to the timing sequence diagram of the SDRAM chip, and utilizes the hardware description language to call and control, thereby realizing the control operation of the SDRAM and improving the signal control efficiency.

Description

SDRAM (synchronous dynamic random access memory) control method and system based on state machine

Technical Field

The invention relates to the technical field of memory control, in particular to a Synchronous Dynamic Random Access Memory (SDRAM) control method and system based on a state machine.

Background

The SDRAM (Synchronous Dynamic Random Access Memory, SDRAM for short) has the advantages of large capacity, fast Access speed, powerful functions and low price, and is used as a preferred storage medium for data caching in many design fields such as image acquisition, real-time image processing and data analysis to cache and process large data volume. Thus, access control to the SDRAM in a sense determines the performance of the system.

With the increasing working frequency of SDRAM brings great challenge to circuit design, higher and higher requirements are also put forward for managing and controlling the read-write operation of SDRAM. At present, there are two ways to form a hardware solution by using FPGA and SDRAM. The first one is to design the SDRAM controller by using hardware programming language, and in the hardware design of high-speed circuit signals, whether the related signals can be output simultaneously or can be output in a strict sequence according to the clock frequency usually determines the success or failure of the whole hardware circuit design, and many program BUG faults occur because of signal advance or delay. Therefore, much effort and time is consumed by designers to write complex control constraint codes to ensure complete and orderly output of signals. Another way is to call the FPGA vendor paid SDRAM controller IP (Intellectual Property) interface.

The defects of the prior art are as follows:

1. the first mode can lead to complicated main program and lower control efficiency; meanwhile, the main program optimization and the transplanting difficulty are increased, and the system performance is influenced.

2. The second mode calls the IP interface of the SDRAM controller paid by the FPGA manufacturer, so that the design economic cost of the product can be improved; although the SDRAM interface has a uniform standard, different FPGA manufacturers have different IP interfaces to the SDRAM controller, even different types of FPGA chips of the same manufacturer have different IP interfaces to the SDRAM controller, which not only causes repeated payment, but also has poor compatibility and portability in specific use.

Disclosure of Invention

In view of the defects of the prior art, the embodiments of the present invention provide a method and a system for controlling an SDRAM based on a state machine, so as to implement the control operation of the SDRAM and improve the signal control efficiency.

In one aspect, an embodiment of the present invention provides a state machine-based SDRAM control method, including the following steps:

s1, making a state machine data table; the state machine data table comprises generated data table data, data table row addresses and data table column addresses;

s2, adding the state machine data table into an internal storage area; the internal storage area is divided by a storage space built in the FPGA; the address bit of the internal storage area corresponds to a row address and a column address of a data table; the data bits of the internal storage area correspond to data table data;

s3, combining the state machine data table in the storage area and the related control signals in the FPGA into SDRAM control logic;

s4, after debugging the SDRAM control logic, executing the required read-write access operation aiming at the target data; the target data is specific data for performing access operation.

In another aspect, an embodiment of the present invention provides a state machine-based SDRAM control system, including:

the state machine data table customizing module is used for manufacturing a state machine data table; the state machine data table comprises generated data table data, data table row addresses and data table column addresses;

the SDRAM controller specifically includes: the BUFF storage unit is added into the state machine data table; the BUFF storage unit is divided by a storage space built in the FPGA; the address bit of the BUFF storage unit corresponds to a data table row address and a data table column address; the data bits of the BUFF storage unit correspond to data of a data table; the logic control unit combines the state machine data table in the storage area and the related control signals in the FPGA into SDRAM control logic; the interface control unit is used for executing read-write access operation aiming at target data after debugging the SDRAM control logic; the target data is specific data for performing access operation.

The embodiment of the invention provides a SDRAM control method and a system based on a state machine; and the internal storage resource of the FPGA is utilized to manufacture a corresponding state machine data table according to the timing sequence diagram of the SDRAM chip, and the hardware description language is utilized to call and control, so that the control operation of the SDRAM is realized, and the signal control efficiency is improved.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the technical description of the present invention will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.

FIG. 1 is a flow chart of a SDRAM control method based on a state machine according to an embodiment of the present invention;

FIG. 2 is a flow chart of a method for customizing a state machine table according to an embodiment of the present invention;

FIG. 3 is a timing diagram illustrating a concurrent read operation of an SDRAM according to an embodiment of the present invention;

FIG. 4 is a diagram of reproduction timing data corresponding to each operating mode of SDRAM according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating an SDRAM work flow according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating a SDRAM control system based on a state machine according to an embodiment of the present invention;

reference numerals:

SDRAM controller-1 BUFF storage unit-101 logic control unit-102

Interface control unit-103 state machine data table customization module-2.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

FIG. 1 is a flow chart of a SDRAM control method based on a state machine according to an embodiment of the present invention; as shown in fig. 1, the method comprises the following steps:

s4, after debugging the SDRAM control logic, performing the required read-write access operation on the target data; the target data is specific data for performing access operation.

Specifically, the SDRAM chip of the embodiment of the invention adopts HY57V641620ET-H, (HY: Haishi company, 57: SDRAM chip, V: operating voltage 3.3V, 641620: chip storage capacity 64M, ET: package, H: speed grade). The interface level standard of HY57V641620ET-H is LVTTL, the package is 54Pin TSOPII, four identical BANKs are arranged inside, each BANK has a row address of 12 bits, a column address of 8 bits, a data bit width of 16 bits and a total storage capacity of 64M.

In the programming process of the controller, the main state conversion flow of the SDRAM is solidified in a storage area in the FPGA in the form of a state machine data table, and a memory peripheral interface circuit and a high-order address generating circuit are realized by using a hardware description language. Therefore, neat data can be output by using the state machine data table, the output integrity of the SDRAM control signal is ensured, and the mutual time delay characteristic is met. Further, various combinations of operations of the SDRAM may be implemented by merging or pruning the state machine data tables.

The row address and the column address of the data table are expressed by binary numbers, the column address is determined by the conversion sequence of the low-order binary numbers of the data stream in the data table, and the flow cycle number of each working mode is determined by the binary number of the column address. Each row address represents an operating mode of the SDRAM. The data of the data table is arranged into a binary number sequence according to the reproduced timing diagram: and compiling the low-order binary number of the data bits according to the column address conversion sequence requirement, and corresponding the high-order binary numbers of the rest data bits to the control signals of the SDRAM one by one according to the timing chart. Thus, each control signal of the SDRAM is compiled into a plurality of groups of binary data streams according to different working mode timing diagrams.

Dividing a storage area BUFF with M bit address bits and N bit data bits by using a storage space of the FPGA, wherein the M bit address bits correspond to a row address and a column address of a data table; the N bit data corresponds to the data output of the data table, and the data of the data table is filled into the BUFF storage area. Designing a control program associated with the BUFF storage area: the high order (row address) of the M-bit address is represented by the corresponding associated signal in the main program after the simplification of the Carnot graph; the lower bits of the M-bit address (column address) are represented by the lower bits of BUFF data; the BUFF data is connected with each control signal of the SDRAM chip in a high-order mode. According to the frequency of the FPGA working clock, the control bit of the SDRAM chip can work strictly according to the set function timing diagram and output corresponding level, thereby completing the required function operation of the SDRAM.

For example, in the embodiment of the present invention, the size of the BUFF storage area divided by the storage space built in the FPGA is 256 (addressing space 8bit) × 32 (data depth), that is, the data in the data table consists of 32-bit binary numbers; designing a logic control program associated with the BUFF storage area, the following is the data table 32-bit data mapping HY57V641620ET-H control signal definition:

data [3:0] -the lower 4 bits of the BRAM address

Data[4]——1’b0

Data[5]——SD_WR_

Data[6]——SD_CAS_

Data[7]——SD_RAS_

Data[8]——SD_CS_

Data[9]——SD_DQMA

Data[10]——BANK0

Data[11]——BANK1

Data[12]——MUX_A[0]

Data[13]——MUX_A[1]

Data[14]——MUX_A[2]

Data[15]——SD__A10

Data[16]——SD_DAT_OEN

Data[17]——FIFO_WOE

Data[18]——FIFOE_ROE

Data[19]——JPEN

Data [20] -REDY (ready for Sdram write)

Data[21]——A10MUX

Data[31:22]——10’b1111111100；(FF0)

The low four-bit data [3:0] determines the jump sequence of each operation period, and the data [4] is set to be 0 as a filling bit; seventeen high data [21:5] maps each control bit pin of the chip (note: the number of data bits is determined by the number of control bit pins of the chip), the number of control pins needed by HY57V641620ET-H is 17 bits, and finally data [31:22] + FF0 is set as a filling bit, and in conclusion, the data format in the BUFF storage area is ROM _ data ═ data [31:22] + data [21:5] + data [4] + data [3:0] + FF0+ data [21:5] +0+ data [3:0], so that the control signals of the SDRAM chip become a group of binary data streams.

It should be noted that the HY57V641620ET-H pin interface is divided into: the control signals comprise chip selection, a clock, clock enabling, row and column address selection, read-write validity and data validity, the signals form a control instruction of the chip, and the control instruction generates a series of control actions through decoding; the address signals comprise block address lines, row address lines and column address lines, the row lines and the column lines of the address signals are time-division multiplexed and can be operated to all memory cells of the chip, the block address lines are used for operating four BANKs, and the data signals are as follows: and the bidirectional pin is effectively controlled by data.

The embodiment of the invention provides a SDRAM control method based on a state machine; and the internal storage resource of the FPGA is utilized to manufacture a corresponding state machine data table according to the timing sequence diagram of the SDRAM chip, and the hardware description language is utilized to call and control, so that the control operation of the SDRAM is realized, and the signal control efficiency is improved.

Further, fig. 2 is a schematic flow chart of a method for customizing a state machine data table according to an embodiment of the present invention; as shown in fig. 2, the step S1 specifically includes:

s11, decomposing and reproducing the timing chart of each working mode of the SDRAM; specifically, the method comprises the steps of eliminating control signals with constant states and control signals with random states, and re-drawing by taking a system clock of the FPGA as a reference;

s12, generating the list address of the data list according to the reproduction sequence diagram corresponding to the working mode; the column address of the data table determines the length of a period for finishing one operation and the jump sequence of each node in one period; outputting a lower four-bit representation from the data table data;

s13, generating the row address of the data table according to the reproduction sequence diagram corresponding to the working mode; the row address of the data table is composed of related control signals of the FPGA and the SDRAM; the combination of the related control signals determines the corresponding operation on the SDRAM;

s14, generating data table data corresponding to the reproduction sequence diagram; combining the level values of the control signals in each period under each working mode into a plurality of groups of binary data streams;

and S15, dividing a plurality of groups of binary data streams into a data table matrix of the state machine according to the row address function of the data table.

Specifically, fig. 5 is a schematic diagram of an SDRAM working flow according to an embodiment of the present invention; as shown in fig. 5, the timing diagram for reproducing each desired operation mode operation is decomposed according to the SDRAM chip manual; the most basic working modes of HY57V641620ET-H are five working modes: a PRECHARGE operation (PRECHARGE), an initialize and store instruction LOAD operation (INIT _ LOAD), a REFRESH operation (REFRESH), a BURST READ operation (BURST _ READ), a BURST WRITE operation (BURST _ WRITE);

BURST READ operation (BURST _ READ) and BURST WRITE operation (BURST _ WRITE):

burst read commands allow a row in a certain BANK to be activated and then a number of data to be read out successively. The first data is presented on the data line after a specified CAS latency beat, and a new data is read out every subsequent clock beat. Burst read operations may be aborted by new burst read/write commands of the same BANK or a different BANK or by precharge and burst stop commands of the same BANK. Burst write operations and burst read operations are substantially similar.

Initialization and instruction LOAD operation (INIT _ LOAD):

initialization and instruction loading operations are set Mode registers, a Mode Register is generally used for defining an HY57V641620ET-H operation Mode, read delay, burst length and type, CAS, an operation Mode and whether the chip works in a single read-write operation or a burst operation are generally set in the registers. The Mode Register is programmed with a LOADMODE REGISTER command, and this set of information is stored in the Mode Register until lost after power down of the memory.

PRECHARGE operation (PRECHARGE):

the addressing of HY57V641620ET-H has exclusivity, so after the read and write operations are performed, if another row of the same BANK is to be addressed, the row that was originally valid (working) is closed and the row/column address is sent again. BANK closes the existing working row and the operation to prepare to open a new row is PRECHARGE. After the precharge command is sent, a period of time is allowed to pass until the RAS row active command is sent to open a new working row, the specific value depends on the clock frequency, and after the chip executes a precharge command, an idle operation command is executed, and the two operations can cause all the memory cells to be precharged once, so that the devices in all the arrays are in a standby state.

REFRESH operation (REFRESH):

because of the discharge phenomenon of dynamic memory cells, HY57V641620ET-H must guarantee that all memory cells are refreshed within 64ms in order to maintain the data correctness of each memory cell. Only one row of the memory unit can be refreshed in one automatic refresh period, and the internal refresh address counter automatically increases by 1 after each refresh operation. The automatic refresh operation can be started only when all BANKs are idle (because corresponding rows of 4 BANKs are refreshed simultaneously) and are not in the low power consumption mode, the idle operation can be input only during the execution of the refresh operation, and all BANKs enter the idle state after the execution of the refresh operation is finished. The device may execute the auto-refresh command once every 7.8us interval or may collectively refresh all cells for a certain period of time within 64 ms.

Decomposing and reproducing the time sequence diagram corresponding to each working mode; removing the control signals with constant states and the control signals with random states, for example, the control signals with constant states are represented by 1, and the control signals with constant states are represented by 0 in the embodiment of the invention; the control signals which are not relevant to the corresponding operation are removed, so that the bits of the binary data stream filled in the state machine data table are reduced; the simplified timing diagram is based on the system clock of the FPGA and is charted again; and each reproduced timing chart is used as a basis for generating corresponding data by the state machine data table. FIG. 3 is a timing diagram of the SDRAM concurrent read operation according to the embodiment of the present invention, and the timing diagram of the SDRAM concurrent read operation in other operation modes is omitted here, as shown in FIG. 3.

Generating a data list address according to all the reproduction sequence diagrams; the column addresses of the data table are used for determining the cycle length of each operation of finishing a working mode and the jump sequence of each node in one cycle, the cycle length and the jump sequence can be adjusted according to needs according to the complexity of different operations, for example, the cycle length and the jump sequence correspond to a timing diagram of an SDRAM chip, each working mode operation cycle is sixteen cycles, each cycle circulates according to the sequence of 0-F, and the lower four bits [3:0] of data output of the data table are used for representing.

Generating a data table row address according to all the reproduction sequence diagrams; for example, the HY57V641620ET-H row address consists of four-digit binary numbers which can represent 16 working modes at most, the four-digit binary numbers of the row address consist of control signals related to an HY57V641620ET-H chip in an FPGA, and the related control signal combination determines what operation is carried out by HY57V641620 ET-H; if the bit number of the related signal is larger than the bit number of the row address of the data table, simplifying the related signal by using a Karnaugh map and mapping the related signal to the row address of the data table; the bit number of the row address of the data table is 4 in the embodiment of the invention. For example, the working mode of HY57V641620ET-H is divided as follows inside FPGA:

FIG. 4 is a diagram of reproduction timing data corresponding to each operating mode of SDRAM according to an embodiment of the present invention; as shown in fig. 4, combining the level values of the control signals in each period according to the entire reproduction timing diagram, several groups of data streams of the reproduction timing diagram corresponding to different operation modes can be obtained; and dividing the obtained data stream into array matrixes according to the row address function, and filling the array matrixes into a data table to finish the state machine data table for HY57V641620ET-H control.

Adding the data table into a main program: utilizing internal storage space of FPGA to open up a 256X 32 BRAM storage area whose address bit is ADDR [7:0] and data bit is DOUT [31:0], adding data stream in data table into BRAM storage area, and mapping DOUT [3:0] by ADDR [3:0] in program; ADDR [7:4] maps SD _ A [7:4] as described previously; DOUT [21:5] maps the Data [21:5] described above, i.e. the control of SDRAM chip HY57V641620ET-H is completed according to the required function requirement.

Further, the step S2 includes adding other status signals inside the FPGA to the internal storage area; as long as the address bit number and the data bit depth of the BUFF storage area opened in the FPGA are large enough, other state signals inside the FPGA can be added into the state machine data table, and the state machine data table is not limited to control signals of SDRAM. The advantage of this is that it can bring as many status signals as possible into the management domain of the SDRAM controller of the FPGA, and output complete control signals meeting strict timing requirements.

The embodiment of the invention provides a SDRAM control method based on a state machine; the data table of the corresponding state machine is manufactured by utilizing the internal storage resource of the FPGA according to the timing sequence diagram of the SDRAM chip, and calling and controlling are carried out by utilizing a hardware description language, so that excessive energy and time are not required to be consumed to write control and constraint codes, the SDRAM control operation is realized, and the signal control efficiency is improved; the method is favorable for packaging the special logic program into a universal IP core, has low cost, greatly improves the integration level and the universality of the hardware program, and is favorable for market popularization.

Based on the above embodiments, fig. 6 is a schematic structural diagram of a state machine-based SDRAM control system according to an embodiment of the present invention; the method comprises the following steps:

the state machine data table customizing module 2 is used for manufacturing a state machine data table; the state machine data table comprises generated data table data, data table row addresses and data table column addresses;

the SDRAM controller 1 specifically includes: a BUFF storage unit 101, which is added to the state machine data table; the BUFF storage unit 101 is divided by a storage space built in the FPGA; the address bit of the BUFF storage unit 101 corresponds to a data table row address and a data table column address; the data bits of the BUFF storage unit 101 correspond to data table data; the logic control unit 102 combines the state machine data table in the BUFF storage unit 101 and the related control signals in the FPGA into SDRAM control logic; and the interface control unit 103 is used for executing required read-write access operation aiming at target data after debugging the SDRAM control logic.

The embodiment of the invention provides a SDRAM control system based on a state machine to execute the method; the data table of the corresponding state machine is manufactured by utilizing the internal storage resource of the FPGA according to the timing sequence diagram of the SDRAM chip, and calling and controlling are carried out by utilizing a hardware description language, so that excessive energy and time are not required to be consumed to write control and constraint codes, the SDRAM control operation is realized, and the signal control efficiency is improved; the method is favorable for packaging the special logic program into a universal IP core, has low cost, greatly improves the integration level and the universality of the hardware program, and is favorable for market popularization.

The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A SDRAM control method based on a state machine is characterized by comprising the following steps:

s3, combining the state machine data table and the related control signal in the storage area into SDRAM control logic;

s4, debugging the SDRAM control logic, and executing the required read-write access operation aiming at the target data; the target data is specific data for performing access operation.

2. The method according to claim 1, wherein the step S1 specifically comprises:

s11, decomposing and reproducing the timing chart of each working mode of the SDRAM; specifically, the method comprises the steps of eliminating control signals with constant states and control signals with random states, and reproducing a timing chart by taking a system clock of the FPGA as a reference;

s12, generating the list address of the data list according to the reproduction sequence diagram; the column address of the data table determines the length of a period for finishing one operation and the jump sequence of each node in one period;

s13, generating the data table row address according to the reproduction sequence diagram; the row address of the data table is composed of related control signals of the FPGA and the SDRAM; the combination of the related control signals determines the corresponding operation on the SDRAM;

and S15, dividing a plurality of groups of the binary data streams into data stream matrixes according to the row address function of the data table.

3. A state machine based SDRAM control method according to claim 1, wherein the step S2 further comprises adding other state signals internal to the FPGA to the state machine data table in the memory area.

4. A state machine based SDRAM control method as recited in claim 2, wherein the step S13 further comprises mapping to the data table row address after simplification using a carnot diagram if the number of bits of the associated control signal is greater than the number of bits of the data table row address.

5. A state machine based SDRAM control system, comprising:

the state machine data table customizing module (2) is used for manufacturing a state machine data table; the state machine data table comprises generated data table data, data table row addresses and data table column addresses;

the SDRAM controller (1) specifically comprises: a BUFF storage unit (101) added to the state machine data table; the BUFF storage unit (101) is divided by a storage space built in the FPGA; the address bit of the BUFF storage unit (101) corresponds to a data table row address and a data table column address; the data bits of the BUFF storage unit (101) correspond to data table data; the logic control unit (102) combines the state machine data table in the storage area and the related control signals in the FPGA into SDRAM control logic; the interface control unit (103) is used for executing read-write access operation aiming at the target data after debugging the SDRAM control logic; the target data is specific data for performing access operation.

6. A state machine based SDRAM control system according to claim 5, wherein the state machine table customization module (2) specifically comprises:

decomposing and reproducing the timing chart of each working mode of the SDRAM; specifically, the method comprises the steps of removing control signals with constant states and control signals with random states, and reproducing a timing chart by taking a system clock of the FPGA as a reference;

generating the list address of the data list according to the reproduction sequence diagram; the column address of the data table determines the length of a period for finishing one operation and the jump sequence of each node in one period;

generating the row address of the data table according to the reproduction sequence diagram; the row address of the data table is composed of related control signals of the FPGA and the SDRAM; the combination of the related control signals determines the corresponding operation on the SDRAM;

generating data table data corresponding to the reproduction sequence diagram; combining the level values of the control signals in each period under each working mode into a plurality of groups of binary data streams;

and dividing a plurality of groups of the binary data streams into a data stream matrix according to the row address function of the data table.

7. A state-machine based SDRAM control system according to claim 5, characterized in that the state-machine tables in the BUFF memory unit (101) can be added with other status signals inside the FPGA.

8. A state machine based SDRAM control system according to claim 6, characterized in that the state machine table customization block (2) further comprises a mapping to the table row address after simplification by using a Carnot diagram if the number of bits of the associated control signal is greater than the number of bits of the table row address.