CN111509048A - N-type fin transistor and manufacturing method thereof - Google Patents
N-type fin transistor and manufacturing method thereof Download PDFInfo
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- CN111509048A CN111509048A CN202010350224.0A CN202010350224A CN111509048A CN 111509048 A CN111509048 A CN 111509048A CN 202010350224 A CN202010350224 A CN 202010350224A CN 111509048 A CN111509048 A CN 111509048A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 61
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 61
- 239000010703 silicon Substances 0.000 claims abstract description 61
- 230000009286 beneficial effect Effects 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 24
- 239000004020 conductor Substances 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 229910006992 Si1-xCx Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005476 size effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
Abstract
The invention discloses an N-type fin transistor, which comprises: the fin body comprises an inner embedded epitaxial layer and an outer silicon epitaxial layer coated on the top surface and the side surface of the inner embedded epitaxial layer, and the inner embedded epitaxial layer enables the outer silicon epitaxial layer in all regions to generate complete strain which is beneficial to improving the electron mobility; the grid structure covers the top surface or the side surface of the selected region of the fin body, and the source region and the drain region are formed in the fin body on two sides of the grid structure; the fin body between the source drain region and the drain region is used as a channel region, and the external silicon epitaxial layer of the channel region is of a completely strained structure so that the channel region is a fully strained channel region. The invention also discloses a manufacturing method of the N-type fin transistor. The invention can improve the electron mobility of the channel to the maximum extent, thereby greatly improving the performance of the device and being beneficial to the continuous reduction of the size of the device.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to an N-type fin transistor (FinFET). The invention also relates to a manufacturing method of the N-type fin transistor.
Background
The stress channel transistor is widely researched in the integrated circuit industry, and the carrier mobility of a channel can be obviously improved by utilizing the technology of providing stress by inlaid source and drain, so that the performance of a device is improved, the size of the transistor is continuously reduced, and the larger-scale integration level is realized. With the increasingly smaller transistor technology nodes, the influence of size effect is increased sharply to cause the failure of a planar device, and the FINFET three-dimensional architecture solves the problem and becomes the mainstream of the industry.
As shown in fig. 1A, a cross-sectional view of a fin body on an X-side surface of a conventional N-type fin transistor is shown, where the fin body is generally in a stripe shape, and the X-side surface is a side surface along a width direction of the fin body; it can be seen that the fin 102 is formed by etching a semiconductor substrate, such as a silicon substrate 101, with shallow trench field oxide 103 formed on both sides of the fin 102. In the prior art, a formation region of the fin body 102 is generally defined by using a spacer hard mask layer (spacehm) process, and then the fin body 102 is formed by etching the semiconductor substrate 101 with the spacer hard mask layer as a mask, trenches formed after the semiconductor substrate 101 is removed are formed at two sides of the fin body 102, and the etching depth is greater than the required height of the fin body 102; then, the shallow trench field oxide 103 is filled in the trenches on both sides of the fin 102.
More than one gate structure can be generally arranged along the length direction of the fin body, a source region and a drain region of the N-type fin transistor are formed in the fin body on two sides of the gate structure, and in order to realize a stress channel transistor structure, an embedded epitaxial layer of tensile stress is required to be generated in an embedded channel region in a forming region of the source region and the drain region in the existing method; as shown in fig. 1B, which is a cross-sectional view of a fin body structure on a Y-side surface of a conventional N-type fin transistor, the Y-side surface is a side surface along a length direction of the fin body, and as shown in fig. 1B, a SiP epitaxial layer 104 is embedded in a formation region of the source region and the drain region, because a lattice constant of the SiP epitaxial layer 104 is different from a lattice constant of the silicon substrate 101, lattices of the fin body 102 formed by the SiP epitaxial layer 104 and the silicon substrate 101 after contacting each other may be left and right, so that the corresponding fin body 102 may be strained, and the strained fin body 102 may generate a tensile stress which is beneficial to improving electron mobility.
For the structure shown in fig. 1B, the fin body between the source region and the drain region forms a channel region, and after the SiP epitaxial layer 104 is formed in the source region and the drain region, the channel region formed by the fin body 102 between the source region and the drain region is strained and has tensile stress favorable for improving electron mobility, so as to improve the electrical performance of the N-type fin transistor.
However, as the critical dimension continues to shrink, further enhancement of channel mobility is required.
Disclosure of Invention
The invention aims to provide an N-type fin transistor which can improve the channel electron mobility so as to improve the performance of a device. Therefore, the invention also provides a manufacturing method of the N-type fin type transistor.
To solve the above technical problem, the present invention provides an N-type fin transistor including:
the fin body comprises an inner embedded epitaxial layer and outer silicon epitaxial layers wrapping the top surface and the side surfaces of the inner embedded epitaxial layer, and the inner embedded epitaxial layer enables the outer silicon epitaxial layers in all regions to generate complete strain which is beneficial to improving electron mobility.
The grid structure covers the top surface or the side surface of the selected region of the fin body, and the source region and the drain region are formed in the fin body on two sides of the grid structure.
The fin body between the source region and the drain region is used as a channel region, and the external silicon epitaxial layer of the channel region is of a completely strained structure, so that the channel region is a fully strained channel region.
In a further improvement, the semiconductor substrate is a silicon substrate.
Shallow trench field oxide is formed in the semiconductor substrate on two sides of the fin body.
In a further improvement, the material of the embedded epitaxial layer is silicon carbide.
In a further improvement, the internally embedded epitaxial layer has the formula Si1-xCxAnd x is between 0.20 and 0.45.
In a further improvement, the thickness of the embedded epitaxial layer is
In a further improvement, the gate structure comprises a gate dielectric layer and a gate conductive material layer.
The gate dielectric layer comprises a gate oxide layer or a high dielectric constant layer; the grid electrode conducting material layer is a polysilicon grid or a metal grid.
In a further improvement, the technology node of the N-type fin transistor is 14nm or below 7 nm.
In order to solve the above technical problems, the present invention provides a method for manufacturing an N-type fin transistor, including the steps of:
step one, a first epitaxial layer, a second silicon epitaxial layer and a third silicon nitride cap layer are sequentially formed on a semiconductor substrate.
And step two, forming an initial fin body protruding on the surface of the semiconductor substrate, wherein the initial fin body comprises a superposed structure of the first epitaxial layer, the second silicon epitaxial layer and the third silicon nitride capping layer.
Shallow trench field oxide is formed in the semiconductor substrate between the initial fins.
And step three, performing selective silicon epitaxial growth on the side face of the first epitaxial layer of the initial fin body to form a fourth silicon epitaxial layer.
And fourthly, removing the third silicon nitride cap layer and forming the fin body, wherein the fin body comprises an inner embedded epitaxial layer formed by the first epitaxial layer and an outer silicon epitaxial layer formed by the second silicon epitaxial layer and the fourth silicon epitaxial layer, the outer silicon epitaxial layer is coated on the top surface and the side surface of the inner embedded epitaxial layer, and the inner embedded epitaxial layer enables the outer silicon epitaxial layer in all regions to generate complete strain which is beneficial to improving the electron mobility.
And step five, forming a grid structure, wherein the grid structure covers the top surface or the side surface of the selected region of the fin body.
Sixthly, performing source-drain injection to form a source region and a drain region in a self-alignment manner in the fin bodies on two sides of the grid structure; the fin body between the source region and the drain region is used as a channel region, and the external silicon epitaxial layer of the channel region is of a completely strained structure, so that the channel region is a fully strained channel region.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the material of the embedded epitaxial layer is silicon carbide.
In a further improvement, the internally embedded epitaxial layer has the formula Si1-xCxAnd x is between 0.20 and 0.45.
In a further improvement, the thickness of the embedded epitaxial layer is
In a further improvement, the gate structure comprises a gate dielectric layer and a gate conductive material layer.
The gate dielectric layer comprises a gate oxide layer or a high dielectric constant layer; the grid electrode conducting material layer is a polysilicon grid or a metal grid.
In a further improvement, the technology node of the N-type fin transistor is 14nm or below 7 nm.
In a further improvement, the third silicon nitride cap layer has a thickness of
The fin body is directly arranged into a structure that an external silicon epitaxial layer coats an internal embedded epitaxial layer, and the structure is a three-dimensional coating structure, so that the external silicon epitaxial layer in each region can be completely strained under the action of the internal embedded epitaxial layer, and finally the external silicon epitaxial layer in the channel region can be completely strained to form a fully strained channel region.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1A is a cross-sectional view of a fin on the X-side of a conventional N-type fin transistor;
FIG. 1B is a cross-sectional view of a conventional fin on the Y-side of an N-type fin transistor;
FIG. 2 is a cross-sectional view of a fin of an N-type fin transistor according to an embodiment of the present invention;
fig. 3A-3E are cross-sectional views of the device structure at various steps in a method of fabricating an N-type fin transistor in accordance with an embodiment of the present invention.
Detailed Description
Fig. 2 is a cross-sectional view of a fin of an N-type fin transistor according to an embodiment of the present invention, wherein fig. 2 is a cross-sectional view along a width direction of the fin; the N-type fin transistor in the embodiment of the invention comprises:
a fin 4 formed on the semiconductor substrate 1.
In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate. Shallow trench field oxide is formed in the semiconductor substrate 1 on both sides of the fin 4.
The fin body 4 comprises an inner embedded epitaxial layer 2 and an outer silicon epitaxial layer 3 coated on the top surface and the side surface of the inner embedded epitaxial layer 2, and the inner embedded epitaxial layer 2 enables the outer silicon epitaxial layer 3 in all regions to generate complete strain which is beneficial to improving electron mobility.
In the embodiment of the present invention, the material of the embedded epitaxial layer 2 is silicon carbide.
Preferably, the molecular formula of the embedded epitaxial layer 2 is Si1-xCxAnd x is between 0.20 and 0.45. The thickness of the inner embedded epitaxial layer 2 is
A gate structure (not shown) covers the top surface or sides of selected regions of the fin 4, and source and drain regions are formed in the fin 4 on both sides of the gate structure.
Typically, more than one of the gate structures can be included along a length of the fin.
The grid structure comprises a grid dielectric layer and a grid conductive material layer.
In the embodiment of the invention, the gate dielectric layer is a gate oxide layer, and the gate conductive material layer is a polysilicon gate; in other embodiments can also be: the gate dielectric layer is a high dielectric constant layer; the grid conductive material layer is a metal grid.
The fin 4 between the source region (not shown) and the drain region (not shown) serves as a channel region, and the outer silicon epitaxial layer 3 of the channel region is of a fully strained structure so that the channel region is a fully strained channel region. In the embodiment of the invention, because the channel region is the fully strained channel region, an epitaxial layer is not embedded in the source region or the drain region.
The full strain channel region structure can be suitable for the requirement that the critical dimension of the device is continuously reduced.
The technology node of the N-type fin transistor is 14nm or below 7 nm.
In the embodiment of the invention, the internal embedded epitaxial layer 2 does not directly contact with the gate dielectric layer, the external silicon epitaxial layer 3 is arranged between the internal embedded epitaxial layer 2 and the gate dielectric layer as a buffer layer, and compared with a structure that the material of the internal embedded epitaxial layer directly contacts with the gate dielectric layer, the interface state density between the whole channel region and the gate dielectric layer can be reduced by adopting the external silicon epitaxial layer 3 as the buffer layer, so that the performance of the device is improved.
The embodiment of the invention directly sets the fin body 4 to be a structure that the external silicon epitaxial layer 3 covers the internal embedded epitaxial layer 2, namely the structure is a three-dimensional coating structure, so that the external silicon epitaxial layer 3 in each region can be completely strained under the action of the internal embedded epitaxial layer 2, and finally the external silicon epitaxial layer 3 in the channel region can be completely strained to form a fully strained channel region, when the device is conducted, a conduction channel formed by an inversion layer can be formed on the surface of the external silicon epitaxial layer 3 in the channel region, and after the external silicon epitaxial layer 3 is completely strained, the electron mobility of the channel can be furthest improved, so that the performance of the device can be greatly improved.
Fig. 3A to 3E are cross-sectional views of the device structure in the steps of the method for fabricating an N-type fin transistor according to the embodiment of the present invention; the manufacturing method of the N-type fin transistor comprises the following steps:
step one, as shown in fig. 3A, the semiconductor substrate 1 is raised.
In the method of the embodiment of the invention, the semiconductor substrate 1 is a silicon substrate.
As shown in fig. 3B, a first epitaxial layer 2, a second epitaxial layer 3a of silicon, and a third cap layer 201 of silicon nitride are sequentially formed on the semiconductor substrate 1.
In the method according to the embodiment of the present invention, the first epitaxial layer 2, that is, the subsequent epitaxial layer 2 embedded therein, is made of silicon carbide.
Preferably, the above-mentionedThe molecular formula of the internally embedded epitaxial layer 2 is Si1-xCxAnd x is between 0.20 and 0.45.
The thickness of the inner embedded epitaxial layer 2 is
The thickness of the third silicon nitride cap layer 201 is
Step two, as shown in fig. 3C, an initial fin body protruding on the surface of the semiconductor substrate 1 is formed, where the initial fin body includes a stacked structure of the first epitaxial layer 2, the second silicon epitaxial layer 3a, and the third silicon nitride capping layer 201.
Shallow trench field oxide is formed in the semiconductor substrate 1 between the initial fins.
Step three, as shown in fig. 3D, selective silicon epitaxial growth is performed to form a fourth silicon epitaxial layer 3b on the side surface of the first epitaxial layer 2 of the initial fin body.
Step four, as shown in fig. 3E, removing the third silicon nitride cap layer 201 and forming the fin body 4, where the fin body 4 includes an inner embedded epitaxial layer 2 composed of the first epitaxial layer 2 and an outer silicon epitaxial layer 3 composed of the second silicon epitaxial layer 3a and the fourth silicon epitaxial layer 3b, the outer silicon epitaxial layer 3 covers the top surface and the side surface of the inner embedded epitaxial layer 2, and the inner embedded epitaxial layer 2 makes the outer silicon epitaxial layer 3 in all regions generate complete strain favorable for improving electron mobility.
And step five, forming a grid structure, wherein the grid structure covers the top surface or the side surface of the selected area of the fin body 4.
In the method of the embodiment of the invention, the gate dielectric layer is a gate oxide layer, and the gate conductive material layer is a polysilicon gate; in other embodiments can also be: the gate dielectric layer is a high dielectric constant layer; the grid conductive material layer is a metal grid.
Sixthly, performing source-drain injection to form a source region and a drain region in a self-alignment manner in the fin body 4 on two sides of the grid structure; the fin body 4 between the source region and the drain region is used as a channel region, and the external silicon epitaxial layer 3 of the channel region is of a completely strained structure, so that the channel region is a fully strained channel region.
The method provided by the embodiment of the invention is suitable for the process with the technical node of 14nm or below 7 nm.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. An N-type fin-type transistor, comprising:
the fin body comprises an internal embedded epitaxial layer and external silicon epitaxial layers coated on the top surface and the side surfaces of the internal embedded epitaxial layer, and the internal embedded epitaxial layer enables the external silicon epitaxial layers in all regions to generate complete strain beneficial to improving electron mobility;
the grid structure covers the top surface or the side surface of the selected region of the fin body, and a source region and a drain region are formed in the fin body on two sides of the grid structure;
the fin body between the source region and the drain region is used as a channel region, and the external silicon epitaxial layer of the channel region is of a completely strained structure, so that the channel region is a fully strained channel region.
2. The N-type fin-type transistor of claim 1, wherein: the semiconductor substrate is a silicon substrate;
shallow trench field oxide is formed in the semiconductor substrate on two sides of the fin body.
3. The N-type fin-type transistor of claim 1, wherein: the material of the embedded epitaxial layer is silicon carbide.
4. The N-type fin-type transistor of claim 3, wherein: the molecular formula of the embedded epitaxial layer is Si1-xCxAnd x is between 0.20 and 0.45.
5. The N-type fin-type transistor of claim 4, wherein: the thickness of the embedded epitaxial layer is
6. The N-type fin-type transistor of claim 1, wherein: the grid structure comprises a grid dielectric layer and a grid conductive material layer;
the gate dielectric layer comprises a gate oxide layer or a high dielectric constant layer; the grid electrode conducting material layer is a polysilicon grid or a metal grid.
7. The N-type fin-type transistor of claim 1, wherein: the technology node of the N-type fin transistor is 14nm or below 7 nm.
8. A method of fabricating an N-type fin transistor, comprising:
step one, forming a first epitaxial layer, a second silicon epitaxial layer and a third silicon nitride cap layer on a semiconductor substrate in sequence;
step two, forming an initial fin body protruding on the surface of the semiconductor substrate, wherein the initial fin body comprises a superposed structure of the first epitaxial layer, the second silicon epitaxial layer and the third silicon nitride capping layer;
shallow trench field oxide is formed in the semiconductor substrate between the initial fin bodies;
step three, performing selective silicon epitaxial growth on the side face of the first epitaxial layer of the initial fin body to form a fourth silicon epitaxial layer;
removing the third silicon nitride cap layer and forming the fin body, wherein the fin body comprises an inner embedded epitaxial layer formed by the first epitaxial layer and an outer silicon epitaxial layer formed by the second silicon epitaxial layer and the fourth silicon epitaxial layer, the outer silicon epitaxial layer is coated on the top surface and the side surface of the inner embedded epitaxial layer, and the inner embedded epitaxial layer enables the outer silicon epitaxial layer in all regions to generate complete strain beneficial to improving the electron mobility;
fifthly, forming a grid structure, wherein the grid structure covers the top surface or the side surface of the selected region of the fin body;
sixthly, performing source-drain injection to form a source region and a drain region in a self-alignment manner in the fin bodies on two sides of the grid structure; the fin body between the source region and the drain region is used as a channel region, and the external silicon epitaxial layer of the channel region is of a completely strained structure, so that the channel region is a fully strained channel region.
9. The method of manufacturing an N-type fin-type transistor of claim 8, wherein: the semiconductor substrate is a silicon substrate.
10. The method of manufacturing an N-type fin-type transistor of claim 8, wherein: the material of the embedded epitaxial layer is silicon carbide.
11. The method of manufacturing an N-type fin-type transistor of claim 10, wherein: the molecular formula of the embedded epitaxial layer is Si1-xCxAnd x is between 0.20 and 0.45.
12. The method of manufacturing an N-type fin-type transistor of claim 11, wherein: the thickness of the embedded epitaxial layer is
13. The method of manufacturing an N-type fin-type transistor of claim 8, wherein: the grid structure comprises a grid dielectric layer and a grid conductive material layer;
the gate dielectric layer comprises a gate oxide layer or a high dielectric constant layer; the grid electrode conducting material layer is a polysilicon grid or a metal grid.
14. The method of manufacturing an N-type fin-type transistor of claim 8, wherein: the technology node of the N-type fin transistor is 14nm or below 7 nm.
15. The method of manufacturing an N-type fin-type transistor of claim 8, wherein: the thickness of the third silicon nitride cap layer is
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| CN113284954A (en) * | 2021-07-22 | 2021-08-20 | 成都蓉矽半导体有限公司 | Silicon carbide MOSFET with high channel density and preparation method thereof |
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| CN113284954A (en) * | 2021-07-22 | 2021-08-20 | 成都蓉矽半导体有限公司 | Silicon carbide MOSFET with high channel density and preparation method thereof |
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