CN111475113A - Large-capacity storage blade based on FPGA and RAID technology and access method - Google Patents
Large-capacity storage blade based on FPGA and RAID technology and access method Download PDFInfo
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- CN111475113A CN111475113A CN202010258980.0A CN202010258980A CN111475113A CN 111475113 A CN111475113 A CN 111475113A CN 202010258980 A CN202010258980 A CN 202010258980A CN 111475113 A CN111475113 A CN 111475113A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7803—System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0689—Disk arrays, e.g. RAID, JBOD
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a high-capacity storage blade based on FPGA and RAID technology and an access method, the storage blade comprises an FPGA module, an RAID module, an onboard SPI F L ASH, a DDR3 memory, an RJ45 connector and a VPX connector which are connected with the FPGA module, the FPGA module comprises a P L end and a PS end, the RAID module comprises a plurality of mSATA solid state hard disks, the P L end and the PS end are communicated through an AXI bus, the P L end is interconnected with the mSATA solid state hard disks through an SATA IP core, and the onboard SPI F L ASH is used for storing logic of the P L end and L inux of the PS end.
Description
Technical Field
The invention relates to the technical field of storage equipment, in particular to a large-capacity storage blade based on FPGA and RAID technology and an access method.
Background
With the increase of the bandwidth of the high-resolution radar and the development of the ultra-high speed acquisition technology, the digital radar system requires the storage device to have the continuous and high-speed storage performance for a long time in the real-time data storage process.
In order to meet the requirement of large capacity, the technology of Redundant Array of Independent Disks (RAID) can fully exert the advantages of multiple hard disks, increase the speed of the hard disks, increase the capacity, provide a fault-tolerant function to ensure data security, and be easy to manage, and can continue to work without being affected by a damaged hard disk when any hard disk fails.
At present, 2U storage servers are common, and are usually realized by adopting a mode that an x86 processor plug-in RAID array card is matched with a corresponding number of hard disks, while a high benefit ratio of performance to power consumption cannot be realized by taking an x86 processor as a manager.
Disclosure of Invention
Aiming at the problem that the performance and power consumption benefits of the existing storage server adopting an x86 processor as a manager are poor, the invention provides a large-capacity storage blade based on FPGA and RAID technology, which has low power consumption and high-speed large-capacity storage performance.
The invention provides a high-capacity storage blade based on FPGA and RAID technology, which comprises an FPGA module, an RAID module, an onboard SPI F L ASH, a DDR3 memory, an RJ45 connector and a VPX connector, wherein the onboard SPI F L ASH, the DDR3 memory, the RJ45 connector and the VPX connector are connected with the FPGA module;
the FPGA module comprises a P L end and a PS end, the RAID module comprises a plurality of mSATA solid state hard disks, the P L end and the PS end are communicated through an AXI bus, the P L end is interconnected with the mSATA solid state hard disks through a SATA IP core, and the onboard SPI F L ASH is used for storing logic of the P L end and L inux of the PS end.
Furthermore, the PS end is externally connected with an onboard EMMC particle through an SDIO interface.
Further, the P L end is connected to the VPX connector through two SRIO x4 interfaces, and is interconnected with a third-party device through the VPX connector.
Further, the FPGA module is further interconnected with a first 88E1512 chip through a first RGMII interface, the first 88E1512 chip is connected to the VPX connector, and a SerDes network is provided to the outside through the VPX connector; and the second chip 88E1512 is interconnected with the second RGMII interface, the second chip 88E1512 is connected with the RJ45 connector, and an MDI network is provided for the outside through the RJ45 connector.
Further, the storage blade further comprises:
and the board-level health management controller is used for acquiring the power consumption and the temperature of the storage blade in real time.
Further, the board-level health management controller adopts a GD32 single chip microcomputer.
Further, the FPGA module adopts an XC7Z045 chip.
Furthermore, the storage blade further comprises a power supply module, the power supply module is connected with the VPX connector and is connected with a direct current 12V voltage through the VPX connector, and the power supply module comprises a direct current step-down power supply and an L DO module and is used for outputting voltages required by the modules.
The invention also provides a data storage method based on the large-capacity storage blade, which comprises the following steps:
step 1, user data enters a P L end of an FPGA module through a VPX connector via an SRIO interface;
step 2: temporarily storing the user data into a DDR3 memory by adopting a DMA mode;
and step 3: and taking the user data out of the DDR3 storage, and writing the user data into a mSATA solid state hard disk of a RAID module by adopting a RAID0 mode.
The invention also provides a data reading method based on the large-capacity storage blade, which comprises the following steps:
step 1: user data is taken out from the mSATA solid state disk of the RAID module in a RAID0 mode;
step 2: temporarily storing the user data into a DDR3 memory by adopting a DMA mode;
and 3, taking the user data out of the DDR3 memory, entering a P L end of the FPGA module, and reading the user data through the SRIO interface and the VPX connector.
The invention has the beneficial effects that:
according to the large-capacity storage blade and the access method based on the FPGA and the RAID technology, the FPGA is used as the RAID controller and the application management processor to replace a traditional mode of externally hanging a RAID array card and an SRIO controller of an x86 processor, the RAID module adopts a mSATA solid state disk mode, and compared with a common 2.5-inch SSD, a large amount of space can be saved, so that a single board can integrate more storage disks, the PCB layout space is effectively saved, and the PCB design difficulty is reduced. Moreover, the single FPGA solution has lower power consumption (less than 10 watts, and power consumption does not include a storage disk), and compared with the traditional method, the single FPGA solution generates power consumption of tens of watts (generally, power consumption is more than 25 watts, and power consumption does not include a storage disk), so that the large-capacity storage blade can operate in a fanless environment.
Drawings
Fig. 1 is a logic structure block diagram of a large-capacity storage blade based on FPGA and RAID technology according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a large-capacity storage blade based on FPGA and RAID technology according to an embodiment of the present invention;
fig. 3 is a schematic diagram of power distribution and timing of a power supply module in a large-capacity storage blade based on FPGA and RAID technologies according to an embodiment of the present invention;
fig. 4 is a data flow diagram illustrating a data access method for a large-capacity storage blade based on FPGA and RAID technologies according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a large-capacity storage blade based on FPGA and RAID technology, which includes an FPGA module, a RAID module, and an onboard SPI F L ASH, DDR3 memory, RJ45 connector, and VPX connector all connected to the FPGA module;
the FPGA module comprises a P L end and a PS end, the RAID module comprises a plurality of mSATA solid state hard disks, the P L end and the PS end are communicated through an AXI bus, the P L end is interconnected with the mSATA solid state hard disks through a SATA IP core, and the onboard SPI F L ASH is used for storing logic of the P L end and L inux of the PS end.
Specifically, in this embodiment, an SRIO interface is used for external data storage, an SRIO IP core is used at the P L end of the FPGA, and a 2-way x4 SRIO interface is communicated with the outside via a VPX connector, so that the bus speed can reach 50Gbps (2 × 4 × 6.25Gbps — 50 Gbps).
As an implementation mode, the FPGA selects XC7Z045 chips of Xilinx company, P L and PS both comprise DDR controllers, in order to obtain the maximum buffer space, a DDR of 2 chip pasters is adopted at a P L end and has a total capacity of 1GB, a DDR of 4 chip pasters is adopted at a PS end and has a total capacity of 2G, an onboard SPI F L ASH has a capacity and specification of 32MB QSPI F L ASH.RATD module and consists of 8 mSATA disks, an mSATA IP core is adopted at an mSATA P L end and is interconnected with mSATA 3.0 protocol, and a storage space of 8TB (1TBx8 ═ 8TB) can be provided when a RAID0 mode is used.
According to the large-capacity storage blade based on the FPGA and the RAID technology, the FPGA is used as the RAID controller and the application management processor to replace a traditional mode of externally hanging a RAID array card and an SRIO controller of an x86 processor, the RAID module is in a mSATA solid state disk mode, compared with a common 2.5-inch SSD, a large amount of space can be saved, the single board can integrate more storage disks, the PCB layout space is effectively saved, and the PCB design difficulty is reduced. Moreover, a single FPGA solution has lower power consumption (less than 10 watts), which may enable the mass storage blade to operate in a fanless environment compared to the traditional approach, which generates tens of watts of power consumption (typically more than 25 watts).
On the basis of the embodiment, the PS end is externally connected with on-board EMMC particles through an SDIO interface for conveniently storing log files and other user files, the P L end is connected with the VPX connector through two SRIO x4 interfaces and is interconnected with third-party equipment through the VPX connector, the FPGA module is also interconnected with a first 88E1512 chip through a first RGMII interface, the first 88E1512 chip is connected with the VPX connector and provides a SerDes network through the VPX connector, and is interconnected with a second 88E1512 chip through a second RGMII interface, the second 88E1512 chip is connected with an RJ45 connector and provides an MDI network through the RJ45 connector.
Specifically, the mass storage blade in this embodiment may externally provide a remote gigabit configuration management network, and a route FGPA is interconnected with 88E1522 through RGMII to externally provide a 1-way gigabit SerDes network through a VPX connector; a routing FPGA is interconnected through RGMII and 88E1522 to provide a gigabit MDI network (1000BASE-T) through RJ4 connectors. The capacity size of the on-board EMMC particles was 64G.
On the basis of the above embodiments, the mass storage blade further includes: and the board-level health management controller is used for acquiring the power consumption and the temperature of the storage blade in real time.
Specifically, the board-level health management controller adopts a GD32 single chip microcomputer, and health information such as power consumption and temperature can be acquired through a hundred-mega Ethernet provided by an RJ45 connector of a front panel.
On the basis of the above embodiments, the mass storage blade further comprises a power supply module, wherein the power supply module is connected with the VPX connector and is connected with a direct current 12V voltage through the VPX connector, and the power supply module comprises a direct current step-down power supply and an L DO module and is used for outputting voltages required by the modules.
Specifically, as shown in fig. 3, after the VPX connector receives a dc 12V voltage, the VPX connector sequentially generates +3.3V _ SB, +1.0V, +1.8V, +1.2V, +3.3V, +2.0V, +1.5V, +0.75V through the dc buck power supply and the L DO module, and the dc buck power supply and the L DO module include a T396232V 130 chip, a L MZ31520 power supply module, a TPS53319 chip, and an IS L80103 voltage regulator chip.
As shown in fig. 4, based on the mass storage blade provided in the foregoing embodiments, an embodiment of the present invention further provides a data storage method, where the method includes the following steps:
step 1, user data enters a P L end of an FPGA module through a VPX connector via an SRIO interface;
step 2: temporarily storing the user data into a DDR3 memory by adopting a DMA mode;
and step 3: and taking the user data out of the DDR3 storage, and writing the user data into a mSATA solid state hard disk of a RAID module by adopting a RAID0 mode.
Specifically, the stored data flow direction is VPX connector-FPGA (P L) -DDR3-FPGA (P L) -mSATA, user data enters a P L part of the FPGA through a VPX connector via an SRIO bus, the data is directly and temporarily stored on a DDR3 memory in a DMA mode, then the data is taken out from the DDR3 by RAID control and written into 8 mSATA in a RAID0 mode, each step in the data storage is controlled through a PS end of the FPGA, a file system is deployed at the PS end of the FPGA, and a user can directly manage and index the stored data through a gigabit Ethernet (1000BASE-T of a front panel or SerDes of the VPX after the PS end of the FPGA).
Corresponding to the data storage method in the foregoing embodiment, an embodiment of the present invention further provides a data reading method, including the following steps:
step 1: user data is taken out from the mSATA solid state disk of the RAID module in a RAID0 mode;
step 2: temporarily storing the user data into a DDR3 memory by adopting a DMA mode;
and 3, taking the user data out of the DDR3 memory, entering a P L end of the FPGA module, and reading the user data through the SRIO interface and the VPX connector.
Specifically, the data reading method provided by the embodiment of the present invention is substantially the inverse process of the storage method. The steps in data reading are controlled through the PS end of the FPGA, the file system is deployed at the PS end of the FPGA, and a user can directly manage and index the stored data through a gigabit Ethernet (1000BASE-T of a front panel or SerDes of a back-out VPX).
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. The high-capacity storage blade based on the FPGA and RAID technology is characterized by comprising an FPGA module, an RAID module, an onboard SPI F L ASH, a DDR3 memory, an RJ45 connector and a VPX connector, wherein the onboard SPI F L ASH, the DDR3 memory, the RJ45 connector and the VPX connector are connected with the FPGA module;
the FPGA module comprises a P L end and a PS end, the RAID module comprises a plurality of mSATA solid state hard disks, the P L end and the PS end are communicated through an AXI bus, the P L end is interconnected with the mSATA solid state hard disks through a SATA IP core, and the onboard SPI F L ASH is used for storing logic of the P L end and L inux of the PS end.
2. The mass storage blade of claim 1, wherein the PS end is circumscribed with an onboard EMMC particle by an SDIO interface.
3. The mass storage blade of claim 1, wherein the P L port is connected to the VPX connector by a two-way SRIO x4 interface, via which to interconnect with third party devices.
4. The mass storage blade of claim 1, wherein the FPGA module is further interconnected with a first 88E1512 chip through a first RGMII interface, the first 88E1512 chip is connected to the VPX connector, and a SerDes network is provided to the outside via the VPX connector; and the second chip 88E1512 is interconnected with the second RGMII interface, the second chip 88E1512 is connected with the RJ45 connector, and an MDI network is provided for the outside through the RJ45 connector.
5. The mass storage blade of claim 1, further comprising:
and the board-level health management controller is used for acquiring the power consumption and the temperature of the storage blade in real time.
6. The mass storage blade as recited in claim 5, wherein the board level health management controller employs a GD32 single chip microcomputer.
7. The mass storage blade of claim 1, wherein the FPGA module employs XC7Z045 chips.
8. The mass storage blade of claim 1, further comprising a power supply module, wherein the power supply module is connected to the VPX connector and is connected to a DC 12V voltage through the VPX connector, and the power supply module comprises a DC step-down power supply and L DO module for outputting voltages required by the modules.
9. The data storage method of the mass storage blade according to any of claims 1 to 8, comprising:
step 1, user data enters a P L end of an FPGA module through a VPX connector via an SRIO interface;
step 2: temporarily storing the user data into a DDR3 memory by adopting a DMA mode;
and step 3: and taking the user data out of the DDR3 storage, and writing the user data into a mSATA solid state hard disk of a RAID module by adopting a RAID0 mode.
10. The data reading method of the mass storage blade according to any of claims 1 to 8, comprising:
step 1: user data is taken out from the mSATA solid state disk of the RAID module in a RAID0 mode;
step 2: temporarily storing the user data into a DDR3 memory by adopting a DMA mode;
and 3, taking the user data out of the DDR3 memory, entering a P L end of the FPGA module, and reading the user data through the SRIO interface and the VPX connector.
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| CN202010258980.0A CN111475113A (en) | 2020-04-03 | 2020-04-03 | Large-capacity storage blade based on FPGA and RAID technology and access method |
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| CN202010258980.0A CN111475113A (en) | 2020-04-03 | 2020-04-03 | Large-capacity storage blade based on FPGA and RAID technology and access method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112685342A (en) * | 2020-12-30 | 2021-04-20 | 湖南博匠信息科技有限公司 | VPX storage control module with pluggable storage disk |
| CN113176850A (en) * | 2021-03-12 | 2021-07-27 | 湖南艾科诺维科技有限公司 | Shared storage disk based on SRIO interface and access method thereof |
-
2020
- 2020-04-03 CN CN202010258980.0A patent/CN111475113A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112685342A (en) * | 2020-12-30 | 2021-04-20 | 湖南博匠信息科技有限公司 | VPX storage control module with pluggable storage disk |
| CN113176850A (en) * | 2021-03-12 | 2021-07-27 | 湖南艾科诺维科技有限公司 | Shared storage disk based on SRIO interface and access method thereof |
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