CN111459713B - Memory detection method and device - Google Patents
Memory detection method and device Download PDFInfo
- Publication number
- CN111459713B CN111459713B CN202010551093.2A CN202010551093A CN111459713B CN 111459713 B CN111459713 B CN 111459713B CN 202010551093 A CN202010551093 A CN 202010551093A CN 111459713 B CN111459713 B CN 111459713B
- Authority
- CN
- China
- Prior art keywords
- data
- memory
- area
- tail
- head
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention relates to a memory detection method and a memory detection device, belongs to the technical field of memory detection, and solves the problem that the integrity check of a data packet cannot be met in the prior art. The memory detection method comprises the following steps: respectively packaging the data to be tested in each memory area according to the one-to-one correspondence relationship between the area label and the data head and the data tail in the database; sequencing the data to be tested according to the area label; when a missing memory area is detected, adding an empty memory block, wherein the empty memory block comprises empty data, a data head and a data tail; comparing the adjacent data tail with the data head; and when the adjacent data tail is the same as the data head, determining that the data to be detected is complete data. The data to be detected can be determined to be complete data by comparing the adjacent data tail with the data head, so that the dependence on a hardware platform is reduced, and the integrity of data access is ensured.
Description
Technical Field
The present invention relates to the field of memory detection technologies, and in particular, to a memory detection method and apparatus.
Background
For users with high stability requirements, memory errors may cause fatal problems, and the memory errors hinder the normal operation of the system. Memory errors are mainly the read and write problems of memory cells, or a series of errors occurring when executing related memory operations, which is the root cause of most software disorders. Therefore, a memory detection technology is needed to detect memory errors, and especially in the embedded field, the safety and reliability are very important.
The realization of common parity check and ECC check is an improvement from the aspect of memory hardware, and the method is really simple, convenient and reliable, but has higher requirements on hardware; meanwhile, the fault tolerance requirements on the memory are different, the hardware structure is different, and the cost is improved. Generally, for some memory errors, a professional memory test tool is used, and generally, dynamic tests are performed by compiling, debugging and running programs in a test tool environment, and the test tool can automatically give a test result of memory leakage and even can locate a code position generating the memory leakage. In addition, a performance monitor of the operating system can be used for monitoring the use condition of the memory in real time, and the problem of the memory can be judged by checking the use data of the memory. When the data is accessed, if a preliminary detection mode exists for the integrity of the data in the memory, the situation that the memory is wrong can be avoided to a certain extent in the application process.
In the field of aerospace, the reliability of an embedded system needs to be supported by a memory detection technology, and for integrity verification of a data packet, the traditional general technology cannot meet the requirement for differentiation of memories.
Disclosure of Invention
In view of the foregoing analysis, embodiments of the present invention provide a method and an apparatus for detecting a memory, so as to solve the problem that the prior art cannot satisfy the integrity check of a data packet.
In one aspect, an embodiment of the present invention provides a memory detection method, including: respectively packaging the data to be tested in each memory area according to the one-to-one correspondence relationship between the area label and the data head and the data tail in the database; sequencing the data to be tested according to the area labels; when a missing memory area is detected, adding an empty memory block, wherein the empty memory block comprises empty data, a data head and a data tail; comparing the adjacent data tail with the data head; and when the adjacent data tail is the same as the data head, determining that the data to be detected is complete data.
The beneficial effects of the above technical scheme are as follows: by comparing the adjacent data tails with the data heads, the data to be detected can be determined to be complete data. Therefore, the dependency on a hardware platform can be reduced, the integrity of data access is ensured, and the stability and reliability of a program are ensured.
Based on the further improvement of the method, before the data to be tested in each memory area is respectively packaged, the memory space is partitioned and partitioned, wherein the partitioning and partitioning include: dividing the memory space into a plurality of memory areas; and dividing each of the plurality of memory regions into one or more memory blocks.
Based on the further improvement of the method, respectively encapsulating the data to be tested in each memory area according to the one-to-one correspondence relationship between the area label and the data head and the data tail in the database further comprises: labeling the memory areas in sequence to enable the memory block data in each memory area to have corresponding area labels; and adding a data head and a data tail corresponding to the area label to the memory block data according to the one-to-one correspondence relationship between the area label and the data head and the data tail in the database.
Based on the further improvement of the above method, sorting the data to be tested according to the region label further includes: and sequencing the data to be tested according to the area label of the packaged data to be tested from small to large.
Based on the further improvement of the above method, when the missing memory region is detected, adding the empty memory block further includes: checking the area label of the sequenced data to be detected to determine whether a missing memory area exists; and when the missing memory area exists, adding a blank memory block corresponding to the missing memory area.
Based on a further improvement of the above method, comparing the adjacent data tails with the data header further comprises: and comparing the data tail of any memory block in the nth memory area with the data head of any memory block in the (n + 1) th memory area, wherein n is greater than or equal to 1.
Based on the further improvement of the above method, when the adjacent data tail is the same as the data head, the step of taking the data to be detected as complete data further includes: when the data tail of any memory block in the nth memory area is the same as the data head of any memory block in the (n + 1) th memory area, determining to form a complete data chain without losing data; otherwise, a complete data chain is not formed, and the missing data is determined.
In another aspect, an embodiment of the present invention provides a memory detection apparatus, including: the packaging module is used for respectively packaging the data to be tested in each memory area according to the one-to-one correspondence relationship between the area label and the data head and the data tail in the database; the sorting module is used for sorting the data to be tested according to the area label; the device comprises a detection and increase module, a data updating module and a data updating module, wherein the detection and increase module is used for increasing an empty memory block when a missing memory area is detected, wherein the empty memory block comprises empty data, a data head and a data tail; the comparison module compares the adjacent data tail with the data head; and the integrity determining module is used for determining that the data to be detected is complete data when the adjacent data tail is the same as the data head.
Based on the further improvement of the above device, the encapsulation module is further configured to: labeling the memory areas in sequence to enable the memory block data in each memory area to have corresponding area labels; and adding a data head and a data tail corresponding to the area label to the memory block data according to the one-to-one correspondence relationship between the area label and the data head and the data tail in the database.
Based on the further improvement of the device, the sorting module is also used for sorting the data to be tested according to the area labels of the packaged data from small to large; the detection and addition module is also used for checking the area label of the sequenced data to be detected so as to determine whether a missing memory area exists; and when the missing memory area exists, adding a blank memory block corresponding to the missing memory area.
Compared with the prior art, the invention can realize at least one of the following beneficial effects:
1. the data to be detected can be determined to be complete data by comparing the adjacent data tail with the data head;
2. the complete reliability of data access in the memory is realized based on the operating system, and the memory detection module is added in the operating system, so that the requirements of high reliability and high real-time performance of the real-time operating system are better met;
3. the method is irrelevant to application program developers, and the data access integrity does not need to be considered by the developers, so that the development efficiency is improved; and
4. neglecting the hardware structure of the memory, a proper method is provided for the memory detection completely from the software level, and the stable and reliable operation of the program can be ensured to a certain extent.
In the invention, the technical schemes can be combined with each other to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
FIG. 1 is a flow chart of a memory detection method according to an embodiment of the invention;
FIG. 2 is a component diagram of an exemplary embodiment of a runtime platform;
FIG. 3 is a diagram illustrating partitioning of memory regions according to an embodiment of the invention;
FIG. 4 is a schematic diagram illustrating memory block partitioning for each memory region according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a data format from the perspective of an operating system according to an embodiment of the present invention;
FIG. 6 is a flowchart illustrating a memory detection method according to an embodiment of the invention; and
fig. 7 is a block diagram of a memory detection apparatus according to an embodiment of the invention.
Reference numerals:
202-embedded operating system; 204-embedded hardware platform; 206-a CPU; 208-a memory; 210-external storage; 702-a package module; 704-a sorting module; 706-detect and add module; 708-a comparison module; and 710-integrity determination module
Detailed Description
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate preferred embodiments of the invention and together with the description, serve to explain the principles of the invention and not to limit the scope of the invention.
A specific embodiment of the present invention discloses a memory detection method, as shown in fig. 1. The memory detection method comprises the following steps: step S102, respectively packaging the data to be tested in each memory area according to the one-to-one correspondence relationship between the area labels and the data heads and data tails in the database; s104, sequencing the data to be tested according to the area labels; step S106, when a missing memory area is detected, adding an empty memory block, wherein the empty memory block comprises empty data, a data head and a data tail; step S108, comparing the adjacent data tail with the data head; and step S110, when the adjacent data tail is the same as the data head, determining that the data to be detected is complete data.
Compared with the prior art, the memory detection method provided by the embodiment can determine that the data to be detected is complete data by comparing the adjacent data tail with the data head. Therefore, the dependency on a hardware platform can be reduced, the integrity of data access is ensured, and the stability and reliability of a program are ensured.
Hereinafter, the memory detection method will be described in detail with reference to fig. 1 to 5.
The memory detection method includes step S102, respectively encapsulating data to be detected in each memory region according to a one-to-one correspondence relationship between the region label and the data header and data trailer in the database. Specifically, according to the one-to-one correspondence relationship between the area label and the data header and the data trailer in the database, respectively encapsulating the data to be tested in each memory area further includes: labeling the memory areas in sequence to enable the memory block data in each memory area to have corresponding area labels; and adding the data head and the data tail corresponding to the area label to the memory block data according to the one-to-one correspondence relationship between the area label and the data head and the data tail in the database. Before packaging the data to be tested in each memory area, partitioning and blocking the memory space, wherein the partitioning and blocking comprises the following steps: dividing a memory space into a plurality of memory areas, wherein the memory areas are adjacent and ordered, and referring to fig. 3, the plurality of memory areas may exemplarily include an area 1, an area 2, and an area 3; dividing each memory area in the plurality of memory areas into one or more memory blocks, wherein the size of each memory block in the same memory area is the same, and the sizes of the memory blocks in different memory areas are different; for example, region 1 includes 6 equal-sized memory chunks, region 2 includes 8 equal-sized memory chunks, and region 3 includes 6 equal-sized memory chunks.
After the data to be tested in each memory area is respectively packaged, step S104 is performed, and the data to be tested is sorted according to the area label. Specifically, the sorting the data to be tested according to the area labels further includes: and sequencing the data to be tested according to the small-to-large area label of the packaged data to be tested.
After the data to be tested is sequenced, step S106 is performed, and when a missing memory area is detected, a blank memory block is added, where the blank memory block includes blank data, a data header, and a data trailer. Specifically, when a missing memory area is detected, adding the empty memory block further includes: checking the area label of the sequenced data to be detected to determine whether a missing memory area exists; and when the missing memory area exists, adding a blank memory block corresponding to the missing memory area, and packaging blank data in the memory block by using a data head and a data tail corresponding to the label of the missing memory area.
After the empty memory block is added, the process proceeds to step S108, where the data end and the data head that are adjacent to each other are compared. Specifically, comparing the adjacent data tails with the data header further comprises: and comparing the data tail of any memory block in the nth memory area with the data head of any memory block in the (n + 1) th memory area respectively, wherein n is greater than or equal to 1.
After comparing the adjacent data tail with the data head, step S110 is performed, and when the adjacent data tail is the same as the data head, it is determined that the data to be measured is complete data. Specifically, when the adjacent data tail is the same as the data head, the step of taking the data to be detected as complete data further includes: when the data tail of any memory block in the nth memory area is the same as the data head of any memory block in the (n + 1) th memory area, determining to form a complete data chain without losing data; otherwise, a complete data chain is not formed, the data loss is determined, and at the moment, data access needs to be carried out again.
Hereinafter, the memory detection method is described in detail with reference to fig. 2 and fig. 4 to 6 by way of specific examples.
The present embodiment is a memory detection method based on an operating system (e.g., hawk-wing operating system), which checks the integrity of data packet access under the mechanism of operating system memory management. The method is implemented based on the embedded platform shown in fig. 2, which includes an embedded operating system 202 (software platform) and an embedded hardware platform 204, where the embedded hardware platform 204 includes a CPU 206, a memory 208, and an external memory 210.
The implementation flow of the memory detection method is shown in fig. 6, and includes the following steps:
step S1: and packaging the data according to the memory area.
And (3) sequentially marking each memory area divided by the memory space from 1 to the last block of area, so that the data corresponding to each memory block area has a corresponding mark as one of the check options.
And packaging the data, packaging all the data according to the one-to-one correspondence relationship between the region labels and the data heads and the data tails in the database, and adding the corresponding data heads and the data tails. The schematic diagram after data encapsulation is shown in fig. 4. Specifically, to ensure the maximum reliability of the verification, the data header and the data trailer must be different two by two.
The database contains the one-to-one correspondence between the labels of the regions and the heads and tails of the data, and specifically, the labels and the corresponding heads and tails of the data do not have any logical relationship and are completely independent. And the data head and tail are added through table look-up operation. The specific correspondence table is shown in table 1 below, where the tail of the data in the nth memory area is the head of the data in the (n + 1) th memory area, and further, in order to ensure the correctness of the data content, the data parity bits may add data error correction bits in addition to the data head and the data tail, which are determined according to hardware or coding rules. The database is embedded into an operating system in advance, and calling is facilitated.
Table 1 table of correspondence
| Region number | Data head | Data tail |
| 1 | 0x0001 | 0x0002 |
| 2 | 0x0002 | 0x0003 |
| 3 | 0x0003 | 0x0004 |
| … | … |
Step S2: and (6) data checking.
Data checking refers to the process of accessing data and integrity checking.
Specifically, the implementation of step S2 specifically includes the following steps:
step S2-1: sorting the accessed data;
the accessed data is sorted in the sequence from small to large according to the area labels after the data is packaged. When data is written into the memory, the operating system will be packaged. When data is read from the memory, the data is taken out first, then the operating system sorts the data according to the size of the data bit of the label of the identification area, the specific sorting mode is not limited, processor resources occupied by different sorting algorithms are different, and bubble sorting is selected in the embodiment according to actual conditions. In particular, some of these data are labeled the same, i.e., from the same region, considered as a whole and then sorted with other data.
Step S2-2: detecting a missing memory area, and adding corresponding data heads and tails;
the missing memory region is detected as the memory region represented by the missing number in the sorted data with the small-to-large label. By searching the table for the corresponding index, the corresponding data head and tail are inserted into the sorted array, which is effectively a "null data".
Step S2-3: and comparing the data head and the tail of the adjacent areas. Specifically, referring to fig. 5, the data end of the 1 st area is compared with the data head of the 2 nd area, and the data end of the 2 nd area is compared with the data head of the 3 rd area; and comparing the data end of the 3 rd region with the data head of the 4 th region.
Specifically, the whole composed of data with the same label is compared, and the data head and the data tail of the data are respectively compared with the corresponding data head and tail with the labels in table 1; then, the head and the tail of the data which are sequenced and added with missing bits, namely the data of the adjacent areas are compared, if a chain can be formed, namely the head and the tail are the same, the data is judged to have no missing packet and to be complete, and the memory controller releases correct data; if a chain cannot be formed, the data is lost, and the step 2 is returned to for access operation again.
The application discloses an operating system-based memory detection technology, under the mechanism of memory management of a Haiying Aihui operating system, each memory area is provided with a corresponding data head and a data tail, and the data format of the memory block can be encapsulated when the data in the memory block is accessed; sequencing the accessed data in the memory according to the sequence of the areas where the data are located; detecting a missing data area, and adding a check data head and a check data tail corresponding to the corresponding area; and comparing every two data heads and the tail of the adjacent areas, if the two data heads and the tail of the adjacent areas are the same, proving that the data access is successful, and otherwise, re-accessing.
The memory management of the operating system mainly divides the memory into a plurality of areas, the areas are adjacent and ordered, each area is divided into a plurality of memory blocks, and the sizes of the memory blocks are the same; the sizes of the memory blocks in different memory areas are different; by utilizing the partition and block mechanism, the time of memory application/release is fixed; when applying for space, memory blocks with different sizes can be obtained in different areas, and when a specific memory block is released, the memory block must be returned to the memory area to which the specific memory block belongs.
Specifically, the memory is divided into a plurality of areas, which are expressed by LW _ MEM structures, and the data structure is as follows:
typedef struct {
PVOID LW _ StartADDRESS// the starting address of the memory partition
PVOID LW _ MemFreeList// the starting address of the free memory block in the memory partition
UINT32 LW _ MemBlkSize// size of memory Block
UINT32 LW _ MemBlkCounter// number of memory blocks
UINT32 LW _ MemFreeCount// the number of free memory blocks
CHAR LW _ MemName [ LW _ CFG _ OBJECT _ NAME _ SIZE ]// NAME of memory block
}LW_MEM；
The specific function is implemented as follows:
memory manager initialization
LW _ MemInit () function initializes a plurality of memory area management structures LW _ MEM
Initializing memory control blocks in a memory partition
The LW _ MemCryate () function connects the memory blocks in the memory area by using a single direction linked list;
the function establishes and initializes a region for dynamic memory allocation, the memory region containing a specified number of memory blocks of a defined size. The application may dynamically apply for these memory blocks and release them back to this memory region after they have been used up. The return value of this function is the pointer to this memory area control block and is the parameter of the relevant call, LW _ MemGet (), LW _ MemPut (), LW _ MemQuery (), etc.
Application memory block
The LW _ MemGet () function acquires a memory block from a specified memory area;
the function is used to allocate a block of memory from the memory region. The user program must know the established size of the block of memory and must release the block of memory after it has been used. This function may be called multiple times, with the return being a pointer to the allocated block of memory and being a parameter of the LW _ MemPut () function.
Releasing memory blocks
The LW _ MemPut function releases the specified memory block to the memory area to which the LW _ MemPut function belongs;
this function is used to release a block of memory that must be released back into the memory region in which it was originally located, otherwise system errors may result.
Under the mechanism of memory management, when applying for a memory, a corresponding memory block is found according to the size of the memory required, and then a corresponding memory area is found.
Specifically, when data in the memory block is accessed, encapsulating the data format of the data refers to adding a data header and a data trailer corresponding to an area where the data is located at the beginning and the end of the data. The memory space is divided into n memory areas, the areas are continuously and sequentially labeled, each memory area is provided with different memory blocks, and each data is provided with an area label n of the position of the data. The data in each memory block has the same data head and data tail, and a "relation chain" can be formed between adjacent n memory blocks, that is, the tail of the data in the nth memory block is the head of the data in the (n + 1) th memory block, and the head and the tail cannot be the same. Different memory blocks have different data heads and data tails, and are different pairwise. Specifically, one n corresponds to one data header and one data trailer, and the one-to-one correspondence relationship can be stored in the database in advance.
Specifically, the accessed data are sorted according to the sequence of the area where the data are located: it means that the data are sorted from small to large according to the zone numbers of the data. If the labels are the same, that is, there is data in the same memory block, the data with the same abscissa are combined into an overall "half-same memory block", and the overall "half-same memory block" is sorted with other data.
Specifically, the detecting of missing data regions: refers to all the data participating in the sorting, the number of the digits is not covered from small to large. Further, the data head and the data tail corresponding to the missing label are combined into null data to be added.
Specifically, the data head and tail are compared: the method is characterized in that the head and the tail of the adjacent data are compared pairwise, and if the pairwise comparison is consistent, the splicing is successful. If the comparison shows inconsistency, the data access is not complete, and the data access is carried out again.
The above operations are all completed by an embedded operating system, which is equivalent to adding a memory detection module in the operating system. 1. Under the memory management mechanism of the operating system, a memory detection module is added, and a more appropriate method is provided for memory detection from a software level. 2. The 'partition and block' of the memory space provides the basis for data encapsulation, and the data head and the data tail between adjacent areas are consistent, so that the data integrity check is realized.
Another embodiment of the present invention discloses a memory detection apparatus, as shown in fig. 7. The memory detection device includes: the encapsulation module 702 is configured to encapsulate the to-be-detected data in each memory area according to the one-to-one correspondence between the area labels in the database and the data headers and data trailers; a sorting module 704, configured to sort the data to be tested according to the area label; a detecting and adding module 706, configured to add an empty memory block when a missing memory area is detected, where the empty memory block includes empty data, a data header, and a data tail; a comparison module 708 that compares the data tail with the data head; and an integrity determination module 710, configured to determine that the data to be detected is complete data when the adjacent data tail is the same as the data head.
The encapsulation module 702 is further configured to label the plurality of memory areas sequentially, so that the memory block data in each memory area has a corresponding area label; and adding the data head and the data tail corresponding to the area label to the memory block data according to the one-to-one correspondence relationship between the area label and the data head and the data tail in the database. The sorting module 704 is further configured to sort the data to be tested according to the area labels of the packaged data from small to large; the detection and addition module is also used for checking the area label of the sequenced data to be detected so as to determine whether a missing memory area exists; and when the missing memory area exists, adding the empty memory block corresponding to the missing memory area.
The memory detection device also comprises a plurality of other modules. The memory detection device corresponds to the memory detection method, and detailed descriptions of a plurality of other modules are omitted to avoid redundancy.
Compared with the prior art, the invention can realize at least one of the following beneficial effects:
1. the data to be detected can be determined to be complete data by comparing the adjacent data tail with the data head;
2. the complete reliability of data access in the memory is realized based on the operating system, and the memory detection module is added in the operating system, so that the requirements of high reliability and high real-time performance of the real-time operating system are better met;
3. the method is irrelevant to application program developers, and the data access integrity does not need to be considered by the developers, so that the development efficiency is improved; and
4. neglecting the hardware structure of the memory, a proper method is provided for the memory detection completely from the software level, and the stable and reliable operation of the program can be ensured to a certain extent.
Those skilled in the art will appreciate that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program, which is stored in a computer readable storage medium, to instruct related hardware. The computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (10)
1. A memory detection method is characterized by comprising the following steps:
respectively packaging the data to be tested in each memory area according to the one-to-one correspondence relationship between the area label and the data head and the data tail in the database;
sequencing the data to be tested according to the area labels;
when a missing memory area is detected, adding an empty memory block, wherein the empty memory block comprises empty data, a data head and a data tail;
comparing the adjacent data tail with the data head; and
and when the adjacent data tail is the same as the data head, determining that the data to be detected is complete data.
2. The memory detection method according to claim 1, wherein before the data to be detected in each memory region is encapsulated, the memory space is partitioned and partitioned, wherein the partitioning and partitioning include:
dividing the memory space into a plurality of memory areas; and
and dividing each memory area in the plurality of memory areas into one or more memory blocks.
3. The memory detection method of claim 2, wherein respectively encapsulating the data to be detected in each memory region according to the one-to-one correspondence between the region label and the data header and the data trailer in the database further comprises:
labeling the memory areas in sequence to enable the memory block data in each memory area to have corresponding area labels; and
and adding a data head and a data tail corresponding to the area label to the memory block data according to the one-to-one correspondence relationship between the area label and the data head and the data tail in the database.
4. The memory detection method of claim 3, wherein sorting the data to be detected according to the region label further comprises: and sequencing the data to be tested according to the area label of the packaged data to be tested from small to large.
5. The memory detection method according to claim 1, wherein when the missing memory region is detected, adding the empty memory block further comprises:
checking the area label of the sequenced data to be detected to determine whether a missing memory area exists; and
and when the missing memory area exists, adding a blank memory block corresponding to the missing memory area.
6. The memory detection method of claim 2, wherein comparing the adjacent data tails with the data header further comprises:
and comparing the data tail of any memory block in the nth memory area with the data head of any memory block in the (n + 1) th memory area, wherein n is greater than or equal to 1.
7. The method according to claim 6, wherein when the adjacent data tail and the data head are the same, the step of determining that the data to be tested is complete further comprises:
when the data tail of any memory block in the nth memory area is the same as the data head of any memory block in the (n + 1) th memory area, determining to form a complete data chain without losing data;
otherwise, a complete data chain is not formed, and the missing data is determined.
8. A memory sensing apparatus, comprising:
the packaging module is used for respectively packaging the data to be tested in each memory area according to the one-to-one correspondence relationship between the area label and the data head and the data tail in the database;
the sorting module is used for sorting the data to be tested according to the area label;
the device comprises a detection and increase module, a data updating module and a data updating module, wherein the detection and increase module is used for increasing an empty memory block when a missing memory area is detected, wherein the empty memory block comprises empty data, a data head and a data tail;
the comparison module compares the adjacent data tail with the data head; and
and the integrity determining module is used for determining that the data to be detected is complete data when the adjacent data tail is the same as the data head.
9. The memory sensing apparatus of claim 8, wherein the encapsulation module is further configured to:
labeling each memory area in sequence, so that the memory block data in each memory area has a corresponding area label; and
and adding a data head and a data tail corresponding to the area label to the memory block data according to the one-to-one correspondence relationship between the area label and the data head and the data tail in the database.
10. The memory test device of claim 9,
the sorting module is also used for sorting the data to be tested according to the size of the area label of the packaged data; and
the detection and addition module is also used for checking the area label of the sequenced data to be detected so as to determine whether a missing memory area exists; and when the missing memory area exists, adding a blank memory block corresponding to the missing memory area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010551093.2A CN111459713B (en) | 2020-06-17 | 2020-06-17 | Memory detection method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010551093.2A CN111459713B (en) | 2020-06-17 | 2020-06-17 | Memory detection method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111459713A CN111459713A (en) | 2020-07-28 |
| CN111459713B true CN111459713B (en) | 2020-09-25 |
Family
ID=71685537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010551093.2A Active CN111459713B (en) | 2020-06-17 | 2020-06-17 | Memory detection method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111459713B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113138874B (en) * | 2021-03-19 | 2023-04-25 | 中国电子科技集团公司第二十九研究所 | Method for detecting memory overflow of embedded software of airborne electronic warfare |
| CN112849376A (en) * | 2021-03-30 | 2021-05-28 | 北京机电工程研究所 | Buoyancy adjusting device and diving equipment with same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6408406B1 (en) * | 1999-08-31 | 2002-06-18 | Western Digital Technologies, Inc. | Hard disk drive infant mortality test |
| CN103095835A (en) * | 2013-01-17 | 2013-05-08 | 成都理想科技开发有限公司 | Realization method for reasonable construction and correct parse of communication data package based on alarm system |
| CN104572530A (en) * | 2013-10-09 | 2015-04-29 | 上海市计算技术研究所 | Lower computer, upper computer and data transmission method |
| CN105468542A (en) * | 2014-09-03 | 2016-04-06 | 杭州华为数字技术有限公司 | Address distribution method and device |
| CN110244604A (en) * | 2019-05-29 | 2019-09-17 | 北京大豪科技股份有限公司 | Data transmission method, device, electronic equipment and storage medium |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7925938B2 (en) * | 2001-10-12 | 2011-04-12 | Geneticware Co. Ltd. | Structure and method of repairing SDRAM by generating slicing table of fault distribution |
-
2020
- 2020-06-17 CN CN202010551093.2A patent/CN111459713B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6408406B1 (en) * | 1999-08-31 | 2002-06-18 | Western Digital Technologies, Inc. | Hard disk drive infant mortality test |
| CN103095835A (en) * | 2013-01-17 | 2013-05-08 | 成都理想科技开发有限公司 | Realization method for reasonable construction and correct parse of communication data package based on alarm system |
| CN104572530A (en) * | 2013-10-09 | 2015-04-29 | 上海市计算技术研究所 | Lower computer, upper computer and data transmission method |
| CN105468542A (en) * | 2014-09-03 | 2016-04-06 | 杭州华为数字技术有限公司 | Address distribution method and device |
| CN110244604A (en) * | 2019-05-29 | 2019-09-17 | 北京大豪科技股份有限公司 | Data transmission method, device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111459713A (en) | 2020-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101369246B (en) | System and method for using a memory mapping function to map memory defects | |
| US7900100B2 (en) | Uncorrectable error detection utilizing complementary test patterns | |
| CN111459713B (en) | Memory detection method and device | |
| CN106919454B (en) | Memory pool problem positioning method and system based on LTE protocol stack | |
| US6523141B1 (en) | Method and apparatus for post-mortem kernel memory leak detection | |
| US20060107130A1 (en) | System and method of reading non-volatile computer memory | |
| CN101369240A (en) | System and method for managing memory errors in an information handling system | |
| CN109189405A (en) | A kind of method and system of proving program Flash data consistency | |
| CN110059068B (en) | Data verification method and data verification system in distributed storage system | |
| US11782609B2 (en) | Method and apparatus for auditing abnormality of block device in cloud platform, device, and storage medium | |
| US4912710A (en) | Self-checking random access memory | |
| US20040088614A1 (en) | Management system for defective memory | |
| US20020104045A1 (en) | System and method for identifying memory modules having a failing or defective address | |
| US20040015864A1 (en) | Method and system for testing memory operations of computer program | |
| US7124336B2 (en) | Method for the defect analysis of memory modules | |
| CN114203252A (en) | Bad block detection method, device, equipment and storage medium of nonvolatile memory | |
| CN109426546A (en) | Using starting method and device, computer storage medium and equipment | |
| US10922023B2 (en) | Method for accessing code SRAM and electronic device | |
| CN1194299C (en) | Dynamic memory function test method | |
| CN116913364B (en) | Flash memory read interference test method and system, electronic equipment and storage medium | |
| CN114267402B (en) | Bad storage unit testing method, device, equipment and storage medium of flash memory | |
| CN102541668A (en) | Method for analyzing reliability of flash file system | |
| US5961656A (en) | Method and apparatus for testing memory devices under load | |
| CN117421162A (en) | Memory fault detection method and device, computer equipment and storage medium | |
| CN117591030A (en) | Reconstruction method and device of virtual disk array |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |