CN111447436A - Video signal stability detection method and device - Google Patents
Video signal stability detection method and device Download PDFInfo
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- CN111447436A CN111447436A CN202010394785.0A CN202010394785A CN111447436A CN 111447436 A CN111447436 A CN 111447436A CN 202010394785 A CN202010394785 A CN 202010394785A CN 111447436 A CN111447436 A CN 111447436A
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
- H04N21/44008—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving operations for analysing video streams, e.g. detecting features or characteristics in the video stream
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Abstract
The application provides a video signal stability detection method and a video signal stability detection device, wherein the video signal stability detection method comprises the following steps: acquiring a video signal to be detected; and carrying out stability detection on the video signal to be detected according to the basic clock signal. In the scheme, the stability of the video signal to be detected can be automatically detected according to the basic clock signal, so that manual detection is not needed, the accuracy of a detection result is improved, the video can be detected in batches, and the detection efficiency is improved.
Description
Technical Field
The present application relates to the field of video processing, and in particular, to a method and an apparatus for detecting video signal stability.
Background
With the development of video technology, the output resolution of video is larger and higher, and the output frame rate is higher and higher, so that the transmission and acquisition stability of video is more and more important. This is because video can cause bad effects if it is not stable, such as: the situation of video flickering suddenly appears while live broadcasting. At present, two methods for detecting the stability of video signals exist, one method is to observe by human eyes, and the other method is to observe and detect by recording videos and then playing the videos at high multiples, but both the two detection methods have subjectivity, and the detection result is not accurate enough.
Disclosure of Invention
An object of the embodiments of the present application is to provide a method and an apparatus for detecting stability of a video signal, so as to solve the technical problem of low accuracy of a detection result.
In order to achieve the above purpose, the technical solutions provided in the embodiments of the present application are as follows:
in a first aspect, an embodiment of the present application provides a method for detecting stability of a video signal, including: acquiring a video signal to be detected; and carrying out stability detection on the video signal to be detected according to the basic clock signal. In the scheme, the stability of the video signal to be detected can be automatically detected according to the basic clock signal, so that manual detection is not needed, and the accuracy of a detection result is improved.
In an optional embodiment of the present application, the performing stability detection on the video signal to be detected according to a basic clock signal includes: and carrying out stability detection on the clock signal, the field synchronous signal, the line synchronous signal and the enabling signal of the video signal to be detected by utilizing the basic clock signal. In the scheme, the clock signal, the field synchronizing signal, the line synchronizing signal and the enabling signal of the video signal to be detected can be automatically and stably detected according to the basic clock signal, so that the accuracy of a detection result is ensured, and manual detection is not needed.
In an optional embodiment of the present application, the performing stability detection on the clock signal of the video signal to be detected by using the basic clock signal includes: performing stability detection on the clock signal by judging whether the counting times of the clock signal in the same time are the same or not; performing stability detection on the field synchronization signal by judging whether the number of the field synchronization signals in the same time is the same; performing stability detection on the line synchronization signal by judging whether the number of line synchronizations between two adjacent field synchronizations is the same; and detecting the stability of the enable signal by judging whether the number of enables between two adjacent line syncs is the same; and if the frequency of a counter generated by the basic clock signal is f and the zero clearing time is t, the counting times in the zero clearing time are ft and the basic counting value is 0 to ft-1. In the above scheme, when the number of times of counting of the clock signal is the same in the same time, the clock signal may be considered to be stable, when the number of field syncs is the same in the same time, the field sync signal may be considered to be stable, when the number of line syncs is the same between two adjacent field syncs, the line sync signal may be considered to be stable, and when the number of enable signals is the same between two adjacent line syncs, the enable signal may be considered to be stable. Therefore, whether the video signal to be detected is stable or not is judged according to the respective properties of the clock signal, the field synchronizing signal, the line synchronizing signal and the enabling signal of the video signal to be detected, so that the accuracy of a detection result is ensured, and manual detection is not needed.
In an optional embodiment of the present application, the determining whether the number of times of counting of the clock signal in the same time is the same to perform stability detection on the clock signal includes: acquiring a plurality of detection count values of a counter generated by the clock signal when the basic count value is ft-1; judging whether the difference value of two adjacent detection count values is within a preset range or not; and if the difference value of the two adjacent detection count values is within the preset range, the clock signal is stable. In the scheme, the stability of the clock signal is detected according to the property of the clock signal of the video signal to be detected and the basic clock signal, so that the accuracy of the detection result is ensured, and manual detection is not needed.
In an alternative embodiment of the present application, the base clock signal generates a detection pulse when the base count value is ft-1, and the clock signal counts when the field sync signal is high; the determining whether the number of the field syncs is the same in the same time to perform the stability detection on the field sync signal includes: acquiring a plurality of detection count values of a counter generated by the clock signal when the detection pulse is high; judging whether the difference value of two adjacent detection count values is within a preset range or not; and if the difference value of the two adjacent detection count values is within the preset range, the field synchronization signal is stable. In the scheme, the stability of the field synchronous signal is detected according to the property of the field synchronous signal of the video signal to be detected and the basic clock signal, so that the accuracy of the detection result is ensured, and manual detection is not needed.
In an alternative embodiment of the present application, the base clock signal generates a detection pulse when the field sync signal is high, and the clock signal counts when the line sync signal is high; the detecting the stability of the horizontal synchronization signal by judging whether the number of the horizontal synchronization between two adjacent field synchronizations is the same includes: acquiring a plurality of detection count values of a counter generated by the clock signal when the detection pulse is high; judging whether the difference value of two adjacent detection count values is within a preset range or not; and if the difference value of the two adjacent detection count values is within the preset range, the line synchronization signal is stable. In the scheme, the stability of the line synchronizing signal is detected according to the property of the line synchronizing signal of the video signal to be detected and the basic clock signal, so that the accuracy of a detection result is ensured, and manual detection is not needed.
In an alternative embodiment of the present application, the base clock signal generates a detection pulse when the line synchronization signal is high, and the clock signal counts when the enable signal is high; the performing stability detection on the enable signal by judging whether the number of enables between two adjacent line syncs is the same includes: acquiring a plurality of detection count values of a counter generated by the clock signal when the detection pulse is high; judging whether the difference value of two adjacent detection count values is within a preset range or not; and if the difference value of the two adjacent detection count values is within the preset range, the enabling signal is stable. In the scheme, the stability of the enable signal is detected according to the property of the enable signal of the video signal to be detected and the basic clock signal, so that the accuracy of the detection result is ensured, and manual detection is not needed.
In a second aspect, an embodiment of the present application provides an apparatus for detecting stability of a video signal, including: the acquisition module is used for acquiring a video signal to be detected; and the detection module is used for carrying out stability detection on the video signal to be detected according to the basic clock signal. In the scheme, the stability of the video signal to be detected can be automatically detected according to the basic clock signal, so that manual detection is not needed, and the accuracy of a detection result is improved.
In an optional embodiment of the present application, the detection module is further configured to: and carrying out stability detection on the clock signal, the field synchronous signal, the line synchronous signal and the enabling signal of the video signal to be detected by utilizing the basic clock signal. In the scheme, the clock signal, the field synchronizing signal, the line synchronizing signal and the enabling signal of the video signal to be detected can be automatically and stably detected according to the basic clock signal, so that the accuracy of a detection result is ensured, and manual detection is not needed.
In an optional embodiment of the present application, the detection module is further configured to: performing stability detection on the clock signal by judging whether the counting times of the clock signal in the same time are the same or not; performing stability detection on the field synchronization signal by judging whether the number of the field synchronization signals in the same time is the same; performing stability detection on the line synchronization signal by judging whether the number of line synchronizations between two adjacent field synchronizations is the same; and detecting the stability of the enable signal by judging whether the number of enables between two adjacent line syncs is the same; and if the frequency of a counter generated by the basic clock signal is f and the zero clearing time is t, the counting times in the zero clearing time are ft and the basic counting value is 0 to ft-1. In the above scheme, when the number of times of counting of the clock signal is the same in the same time, the clock signal may be considered to be stable, when the number of field syncs is the same in the same time, the field sync signal may be considered to be stable, when the number of line syncs is the same between two adjacent field syncs, the line sync signal may be considered to be stable, and when the number of enable signals is the same between two adjacent line syncs, the enable signal may be considered to be stable. Therefore, whether the video signal to be detected is stable or not is judged according to the respective properties of the clock signal, the field synchronizing signal, the line synchronizing signal and the enabling signal of the video signal to be detected, so that the accuracy of a detection result is ensured, and manual detection is not needed.
In an optional embodiment of the present application, the detection module is further configured to: acquiring a plurality of detection count values of a counter generated by the clock signal when the basic count value is ft-1; judging whether the difference value of two adjacent detection count values is within a preset range or not; and if the difference value of the two adjacent detection count values is within the preset range, the clock signal is stable. In the scheme, the stability of the clock signal is detected according to the property of the clock signal sent by the video signal to be detected and the basic clock signal, so that the accuracy of the detection result is ensured, and manual detection is not needed.
In an alternative embodiment of the present application, the base clock signal generates a detection pulse when the base count value is ft-1, and the clock signal counts when the field sync signal is high; the detection module is further configured to: acquiring a plurality of detection count values of a counter generated by the clock signal when the detection pulse is high; judging whether the difference value of two adjacent detection count values is within a preset range or not; and if the difference value of the two adjacent detection count values is within the preset range, the field synchronization signal is stable. In the scheme, the stability of the field synchronous signal is detected according to the property of the field synchronous signal of the video signal to be detected and the basic clock signal, so that the accuracy of the detection result is ensured, and manual detection is not needed.
In an alternative embodiment of the present application, the base clock signal generates a detection pulse when the field sync signal is high, and the clock signal counts when the line sync signal is high; the detection module is further configured to: acquiring a plurality of detection count values of a counter generated by the clock signal when the detection pulse is high; judging whether the difference value of two adjacent detection count values is within a preset range or not; and if the difference value of the two adjacent detection count values is within the preset range, the line synchronization signal is stable. In the scheme, the stability of the line synchronizing signal is detected according to the property of the line synchronizing signal of the video signal to be detected and the basic clock signal, so that the accuracy of a detection result is ensured, and manual detection is not needed.
In an alternative embodiment of the present application, the base clock signal generates a detection pulse when the line synchronization signal is high, and the clock signal counts when the enable signal is high; the detection module is further configured to: acquiring a plurality of detection count values of a counter generated by the clock signal when the detection pulse is high; judging whether the difference value of two adjacent detection count values is within a preset range or not; and if the difference value of the two adjacent detection count values is within the preset range, the enabling signal is stable. In the scheme, the stability of the enable signal is detected according to the property of the enable signal of the video signal to be detected and the basic clock signal, so that the accuracy of the detection result is ensured, and manual detection is not needed.
In a third aspect, an embodiment of the present application provides an electronic device, including: a processor, a memory, and a bus; the processor and the memory are communicated with each other through the bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions capable of performing the video signal stability detection method as in the first aspect.
In a fourth aspect, embodiments of the present application provide a non-transitory computer-readable storage medium storing computer instructions that cause the computer to perform the video signal stability detection method as in the first aspect.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a block diagram illustrating a video signal stability detection system according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a method for detecting video signal stability according to an embodiment of the present disclosure;
fig. 3 is a flowchart illustrating a stability detection of a clock signal according to an embodiment of the present disclosure;
fig. 4 is a flowchart of stability detection on a field sync signal according to an embodiment of the present application;
fig. 5 is a schematic diagram of field sync signal detection provided in an embodiment of the present application;
fig. 6 is a flowchart of performing stability detection on a line synchronization signal according to an embodiment of the present application;
FIG. 7 is a schematic diagram illustrating detection of a horizontal synchronization signal according to an embodiment of the present application;
fig. 8 is a flowchart of stability detection on an enable signal according to an embodiment of the present disclosure;
fig. 9 is a block diagram of a video signal stability detection apparatus according to an embodiment of the present application;
fig. 10 is a block diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
In order to improve the accuracy of video signal stability detection and realize batch detection of multiple paths of video signals, thereby improving the detection efficiency, the embodiment of the application provides a video signal stability detection system. Referring to fig. 1, fig. 1 is a block diagram of a video signal stability detection system according to an embodiment of the present disclosure, where the video signal stability detection system 100 may include a plurality of signal sources 101 and a plurality of detection devices 102. The signal source 101 may be any device capable of outputting a video signal, such as: a computer, a mobile phone, etc., the video signal output by the signal source 101 is the video signal to be detected in the embodiment of the present application. The detection device 102 may be a device with a Field Programmable Gate Array (FPGA) chip, and the detection device 102 may be connected to the signal source 101 through a communication interface such as a network or a serial port, and is configured to receive a video signal to be detected sent by the signal source 101, and perform stability detection on the video signal to be detected. Therefore, after receiving the video signal to be detected sent by the signal source 101, the detection device 102 can automatically detect the stability of the video signal to be detected, so that manual detection is not needed, and the accuracy of detecting the stability of the video signal is improved.
As an implementation manner, a plurality of FPGA chips may be placed in one detection device 102, and each FPGA chip may detect thirty-two channels of video signals to be detected simultaneously, so that the video signal stability detection system provided in the embodiment of the present application may implement batch detection of video signals to be detected, thereby improving efficiency of video signal stability detection.
Based on the video signal stability detection system, an embodiment of the present application further provides a video signal stability detection method, which can be applied to the detection device 102. The following describes a detailed implementation process of the video signal stability detection method provided in the embodiment of the present application.
Referring to fig. 2, fig. 2 is a flowchart of a video signal stability detection method according to an embodiment of the present disclosure, where the video signal stability detection method includes the following steps:
step S201: and acquiring a video signal to be detected.
Step S202: and carrying out stability detection on the video signal to be detected according to the basic clock signal.
Specifically, the detection device may receive the video signals to be detected sent by the plurality of signal sources through a communication interface such as a network or a serial port, and for convenience of description, the detection device is described as an example of detecting one path of the video signals to be detected.
An independent basic clock signal can be set inside an FPGA chip in the detection equipment, and the FPGA chip can be named refclk. By using the basic clock signal refclk, a counter with frequency f and clear time t can be realized, the counting number of the counter in the clear time is ft, and the basic count value is 0 to ft-1.
It should be noted that, in the embodiment of the present application, neither the frequency nor the clear time of the counter generated by the base clock signal refclk is limited, and those skilled in the art may make appropriate adjustments according to actual situations. For example, an independent basic clock signal with a frequency of 100M may be set inside the FPGA chip, and a 1s clear counter cnt _1s may be implemented by using the basic clock signal refclk, where the count number of the counter cnt _1s in the clear time is 107The base count value is 0 to 9999999.
The step S202 may specifically include the following steps:
and carrying out stability detection on a clock signal, a field synchronization signal, a line synchronization signal and an enable signal of the video signal to be detected by utilizing the basic clock signal.
In order to determine the stability of the video signal to be detected, at least the stability of the clock signal clk, the field synchronization signal vsync, the line synchronization signal hsync, and the enable signal de of the video signal to be detected needs to be determined.
The clock signal clk in the video signal to be detected has a fixed clock frequency, is the basis of sequential logic, and is used to determine when the state in the logic unit is updated, and is a semaphore with a fixed period and independent of operation. In order to synchronize the line scanning rule and the field scanning rule of the receiving end with the line scanning rule or the field scanning rule, the sending end of the signal source sends a pulse signal to the receiver after the line scanning rule or the field scanning rule is normally finished, and the pulse signal indicates that the line scanning rule or the field scanning rule is finished, and the pulse signal is a line synchronization signal hsync or a field synchronization signal vsync. The enable signal de is responsible for input and output of the control signal.
As an embodiment, the step of performing stability detection on the clock signal clk, the field synchronization signal vsync, the line synchronization signal hsync, and the enable signal de of the video signal to be detected by using the base clock signal refclk may further include the following steps:
firstly, the stability of the clock signal is detected by judging whether the counting times of the clock signal in the same time are the same or not.
And secondly, detecting the stability of the field synchronization signals by judging whether the number of the field synchronization signals in the same time is the same or not.
And thirdly, detecting the stability of the line synchronization signal by judging whether the number of the line synchronization between two adjacent field synchronization is the same or not.
And fourthly, detecting the stability of the enabling signals by judging whether the enabling quantity between two adjacent line synchronizations is the same or not.
The detailed implementation of the above four steps will be described in the following examples, which will not be described here.
It should be noted that, there is no time sequence in the actual execution process of the above four steps, and after receiving the video signal to be detected sent by the signal source, the detection device may execute the above four steps at the same time, that is, perform stability detection on the clock signal clk, the field synchronization signal vsync, the line synchronization signal hsync, and the enable signal de of the video signal to be detected at the same time. Of course, it is understood that the detection device may also perform stability detection on the clock signal clk, the field synchronization signal vsync, the line synchronization signal hsync, and the enable signal de of the video signal to be detected sequentially according to different orders, which is not specifically limited in this embodiment of the application.
In the above scheme, the stability detection may be performed according to the basic clock signal refclk, respectively, for the clock signal clk, the field synchronization signal vsync, the line synchronization signal hsync, and the enable signal de of the video signal to be detected, where the clock signal clk may be considered stable when the count times of the clock signal clk are the same in the same time, the field synchronization signal vsync may be considered stable when the number of field synchronizations is the same in the same time, the line synchronization signal hsync may be considered stable when the number of line synchronizations is the same between two adjacent field synchronizations, and the enable signal de may be considered stable when the number of enable signals is the same between two adjacent line synchronizations. Therefore, whether the video signal to be detected is stable or not is judged according to the respective properties of the clock signal clk, the field synchronization signal vsync, the line synchronization signal hsync and the enable signal de of the video signal to be detected, so that the accuracy of a detection result is ensured, manual detection is not needed, the video can be detected in batches on the basis of improving the accuracy of the detection result, and the detection efficiency is improved.
Taking the counter cnt _1s generated by the basic clock signal refclk as an example, the following describes the steps of the detection device automatically detecting the stability of the clock signal clk, the field sync signal vsync, the line sync signal hsync, and the enable signal de of the video signal to be detected, respectively.
First, a step of performing stability detection on a clock signal clk of a video signal to be detected by a detection device is introduced, please refer to fig. 3, where fig. 3 is a flowchart of performing stability detection on a clock signal according to an embodiment of the present application, and the step of performing stability detection on a clock signal by determining whether the number of times of counting the clock signal in the same time is the same may include the following steps:
step S301: a plurality of detection count values of a counter generated by a clock signal at a base count value of ft-1 are acquired.
Step S302: and judging whether the difference value of the two adjacent detection count values is within a preset range.
Step S303: and if the difference value of the two adjacent detection count values is within a preset range, the clock signal is stable.
Specifically, a counter count is generated by using the clock signal clk of the video signal to be detected, the counter count is set to be cleared when cnt _1s is equal to 0, count the count value of the counter count when cnt _1s is equal to 9999999 n times (hereinafter, n is described as an example of 10) as a detection count value, and a plurality of detection count values are named count1, count2, count … …, and count 10.
Since the counter generated by the stable clock signal should count the same number of times in the same time, the difference between count1 and count2, between count2 and count3, between count … …, and between count9 and count10 can be determined, and if the difference is within a preset range, the clock signal clk of the video signal to be detected can be considered to be stable. Wherein, the preset range can be adjusted properly according to the actual situation, such as: 50, i.e. the difference exceeds 50, the clock signal clk of the video signal to be detected is considered unstable.
It will be appreciated that if the difference is negative, the absolute value of the difference is compared to a predetermined range.
In the above scheme, the stability of the clock signal clk is detected according to the property of the clock signal clk of the video signal to be detected and the basic clock signal refclk, so that the accuracy of the detection result is ensured, manual detection is not required, the video can be detected in batches on the basis of improving the accuracy of the detection result, and the detection efficiency is improved.
Next, a step of performing stability detection on a field synchronization signal vsync of a video signal to be detected by a detection device is introduced, please refer to fig. 4, where fig. 4 is a flowchart of performing stability detection on a field synchronization signal provided in this embodiment of the present application, and the step of performing stability detection on a field synchronization signal by determining whether the number of field synchronizations is the same within the same time may include the following steps:
step S401: a plurality of detection count values of a counter generated by a clock signal when a detection pulse is high are acquired.
Step S402: and judging whether the difference value of the two adjacent detection count values is within a preset range.
Step S403: and if the difference value of the two adjacent detection count values is within a preset range, the field synchronization signal is stable.
Specifically, similarly, a counter count is generated by the clock signal clk of the video signal to be detected, and the counter count is set to be cleared when cnt _1s is equal to 0. It may be set that the base clock signal refclk generates the detection pulse flag _1s when cnt _1s is 9999999, and the clock signal clk of the video signal to be detected counts when the field synchronization signal vsync is high. The count value of the counter when the detection pulse flag _1s is high is taken as a detection count value, n (hereinafter, n is 10 as an example) detection count values are counted, and a plurality of detection count values are named count1, count2, … …, and count 10.
Since the number of the stable field sync signals in the same time is the same, the difference between count1 and count2, between count2 and count3, between … …, between count9 and count10 can be determined, and if the difference is within a preset range, the field sync signal vsync of the video signal to be detected can be considered to be stable. Wherein, the preset range can be adjusted properly according to the actual situation, such as: 1, i.e. the difference magnitude exceeds 1, the field sync signal vsync of the video signal to be detected is deemed to be unstable.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating the detection of the field sync signals according to the embodiment of the present application, as shown in fig. 5, the number of field syncs between count1 and count2 is 3, the number of field syncs between count2 and count is 3, and the difference is less than 1, so that the field sync signal vsync shown in fig. 5 is stable.
In the scheme, the stability of the field synchronous signal vsync is detected according to the property of the field synchronous signal vsync of the video signal to be detected and the basic clock signal refclk, so that the accuracy of a detection result is ensured, manual detection is not needed, the video can be detected in batches on the basis of improving the accuracy of the detection result, and the detection efficiency is improved.
Then, a step of performing stability detection on the line synchronization signal hsync of the video signal to be detected by the detection device is introduced, please refer to fig. 6, where fig. 6 is a flowchart of performing stability detection on the line synchronization signal according to an embodiment of the present application, and the step of performing stability detection on the line synchronization signal by determining whether the number of line synchronizations between two adjacent field synchronizations is the same may include the following steps:
step S601: a plurality of detection count values of a counter generated by a clock signal when a detection pulse is high are acquired.
Step S602: and judging whether the difference value of the two adjacent detection count values is within a preset range.
Step S603: and if the difference value of two adjacent detection count values is within a preset range, the horizontal synchronizing signal is stable.
Specifically, the process of performing stability detection on the line synchronization signal hsync is similar to the process of performing stability detection on the field synchronization signal vsync. Firstly, a counter count is generated by using a clock signal clk of a video signal to be detected, the counter count is set to be cleared when cnt _1s is equal to 0, a detection pulse flag _1s is generated by a basic clock signal refclk when a field synchronization signal is high, and the counter count counts when a row synchronization signal hsync is high. The count value of the counter when the detection pulse is high is taken as a detection count value, n (hereinafter, n is 10 as an example) detection count values are counted, and a plurality of detection count values are named as count1, count2, … … and count 10.
Since the number of line syncs of the stable line sync signals within the two field syncs is the same, the difference between count1 and count2, between count2 and count3, between count … …, and between count9 and count10 can be determined, and if the difference is within a preset range, the line sync signal hsync of the video signal to be detected can be considered to be stable. Wherein, the preset range can be adjusted properly according to the actual situation, such as: 1, i.e. the difference exceeds 1, the line synchronization signal hsync of the video signal to be detected is considered to be unstable.
Referring to fig. 7, fig. 7 is a schematic diagram illustrating detection of a row synchronization signal according to an embodiment of the present disclosure, as shown in fig. 7, a count value of count0 is 4, a count value of count1 is also 4, and a difference value is smaller than 1, so that the row synchronization signal hsync shown in fig. 5 is stable.
In the above scheme, the stability of the line synchronization signal hsync of the video signal to be detected is detected according to the property of the line synchronization signal hsync and the basic clock signal refclk, so that the accuracy of the detection result is ensured, manual detection is not needed, the video can be detected in batches on the basis of improving the accuracy of the detection result, and the detection efficiency is improved.
Finally, a step of performing stability detection on the enable signal de of the video signal to be detected by the detection device is introduced, please refer to fig. 8, where fig. 8 is a flowchart of performing stability detection on the enable signal according to an embodiment of the present application, and the step of performing stability detection on the enable signal by determining whether the number of enabled signals between two adjacent line syncs is the same may include the following steps:
step S801: a plurality of detection count values of a counter generated by a clock signal when a detection pulse is high are acquired.
Step S802: and judging whether the difference value of the two adjacent detection count values is within a preset range.
Step S803: and if the difference value of two adjacent detection count values is within a preset range, enabling the signals to be stable.
Specifically, the process of performing stability detection on the enable signal de is similar to the process of performing stability detection on the field synchronization signal vsync and the line synchronization signal hsync. Firstly, a counter count is generated by using a clock signal clk of a video signal to be detected, the counter count is set to be cleared when cnt _1s is equal to 0, a detection pulse flag _1s is generated by a basic clock signal refclk when a line synchronization signal hsync is high, and the counter count counts when an enable signal de is high. The count value of the counter when the detection pulse is high is taken as a detection count value, n (hereinafter, n is 10 as an example) detection count values are counted, and a plurality of detection count values are named as count1, count2, … … and count 10.
Since the number of enabled signals (i.e., the number of valid data) of the stable enable signals within the two line syncs is the same, the difference between count1 and count2, between count2 and count3, … …, between count9 and count10 can be determined, and if the difference is within a preset range, the enable signal de of the video signal to be detected can be considered to be stable. Wherein, the preset range can be adjusted properly according to the actual situation, such as: 1, i.e. the difference value exceeds 1, the enable signal de of the video signal to be detected is considered to be unstable.
In the above scheme, the stability of the enable signal de is detected according to the property of the enable signal de of the video signal to be detected and the basic clock signal refclk, so that the accuracy of the detection result is ensured, manual detection is not needed, the video can be detected in batches on the basis of improving the accuracy of the detection result, and the detection efficiency is improved.
Referring to fig. 9, fig. 9 is a block diagram of a video signal stability detection apparatus according to an embodiment of the present disclosure, where the video signal stability detection apparatus 900 may include: an obtaining module 901, configured to obtain a video signal to be detected; the detecting module 902 is configured to perform stability detection on the video signal to be detected according to the basic clock signal.
In the embodiment of the application, the stability of the video signal to be detected can be automatically detected according to the basic clock signal, so that manual detection is not needed, the accuracy of the detection result is improved, the video can be detected in batches, and the detection efficiency is improved.
Further, the detecting module 902 is further configured to: and carrying out stability detection on the clock signal, the field synchronous signal, the line synchronous signal and the enabling signal of the video signal to be detected by utilizing the basic clock signal.
In the embodiment of the application, the clock signal, the field synchronizing signal, the line synchronizing signal and the enabling signal of the video signal to be detected can be automatically and stably detected according to the basic clock signal, so that the accuracy of the detection result is ensured, manual detection is not needed, the video can be detected in batches on the basis of improving the accuracy of the detection result, and the detection efficiency is improved.
Further, the detecting module 902 is further configured to: performing stability detection on the clock signal by judging whether the counting times of the clock signal in the same time are the same or not; performing stability detection on the field synchronization signal by judging whether the number of the field synchronization signals in the same time is the same; performing stability detection on the line synchronization signal by judging whether the number of line synchronizations between two adjacent field synchronizations is the same; and detecting the stability of the enable signal by judging whether the number of enables between two adjacent line syncs is the same; and if the frequency of a counter generated by the basic clock signal is f and the zero clearing time is t, the counting times in the zero clearing time are ft and the basic counting value is 0 to ft-1.
In the embodiment of the present application, the clock signal may be considered to be stable when the number of times of counting of the clock signal is the same in the same time, the field sync number may be considered to be stable when the field sync number is the same in the same time, the line sync signal may be considered to be stable when the line sync number is the same between two adjacent field syncs, and the enable signal may be considered to be stable when the enable number is the same between two adjacent line syncs. Therefore, whether the video signal to be detected is stable or not is judged according to the respective properties of the clock signal, the field synchronizing signal, the line synchronizing signal and the enabling signal of the video signal to be detected, so that the accuracy of a detection result is ensured, manual detection is not needed, the video can be detected in batches on the basis of improving the accuracy of the detection result, and the detection efficiency is improved.
Further, the detecting module 902 is further configured to: acquiring a plurality of detection count values of a counter generated by the clock signal when the basic count value is ft-1; judging whether the difference value of two adjacent detection count values is within a preset range or not; and if the difference value of the two adjacent detection count values is within the preset range, the clock signal is stable.
In the embodiment of the application, the stability of the clock signal is detected according to the property of the clock signal of the video signal to be detected and the basic clock signal, so that the accuracy of the detection result is ensured, manual detection is not needed, the video can be detected in batches on the basis of improving the accuracy of the detection result, and the detection efficiency is improved.
Further, the basic clock signal generates a detection pulse when the basic count value is ft-1, and the clock signal counts when the field synchronization signal is high; the detection module 902 is further configured to: acquiring a plurality of detection count values of a counter generated by the clock signal when the detection pulse is high; judging whether the difference value of two adjacent detection count values is within a preset range or not; and if the difference value of the two adjacent detection count values is within the preset range, the field synchronization signal is stable.
In the embodiment of the application, the stability of the field synchronous signal is detected according to the property of the field synchronous signal of the video signal to be detected and the basic clock signal, so that the accuracy of the detection result is ensured, manual detection is not needed, the video can be detected in batches on the basis of improving the accuracy of the detection result, and the detection efficiency is improved.
Further, the basic clock signal generates a detection pulse when the field synchronization signal is high, and the clock signal counts when the line synchronization signal is high; the detection module 902 is further configured to: acquiring a plurality of detection count values of a counter generated by the clock signal when the detection pulse is high; judging whether the difference value of two adjacent detection count values is within a preset range or not; and if the difference value of the two adjacent detection count values is within the preset range, the line synchronization signal is stable.
In the embodiment of the application, the stability of the line synchronizing signal is detected according to the property of the line synchronizing signal of the video signal to be detected and the basic clock signal, so that the accuracy of the detection result is ensured, manual detection is not needed, the video can be detected in batches on the basis of improving the accuracy of the detection result, and the detection efficiency is improved.
Further, the basic clock signal generates a detection pulse when the horizontal synchronizing signal is high, and the clock signal counts when the enable signal is high; the detection module 902 is further configured to: acquiring a plurality of detection count values of a counter generated by the clock signal when the detection pulse is high; judging whether the difference value of two adjacent detection count values is within a preset range or not; and if the difference value of the two adjacent detection count values is within the preset range, the enabling signal is stable.
In the embodiment of the application, the stability of the enable signal is detected according to the property of the enable signal of the video signal to be detected and the basic clock signal, so that the accuracy of the detection result is ensured, manual detection is not needed, the video can be detected in batches on the basis of improving the accuracy of the detection result, and the detection efficiency is improved.
Referring to fig. 10, fig. 10 is a block diagram of an electronic device according to an embodiment of the present disclosure, where the electronic device 1000 includes: at least one processor 1001, at least one communication interface 1002, at least one memory 1003 and at least one communication bus 1004. Wherein, the communication bus 1004 is used for implementing direct connection communication of these components, the communication interface 1002 is used for communicating signaling or data with other node devices, and the memory 1003 stores machine readable instructions executable by the processor 1001. When the electronic device 1000 is running, the processor 1001 communicates with the memory 1003 via the communication bus 1004, and the machine-readable instructions, when called by the processor 1001, perform the video signal stability detection method described above.
For example, the processor 1001 of the embodiment of the present application may read the computer program from the memory 1003 through the communication bus 1004 and execute the computer program to implement the following method: step S301: a plurality of detection count values of a counter generated by a clock signal at a base count value of ft-1 are acquired. Step S302: and judging whether the difference value of the two adjacent detection count values is within a preset range. Step S303: and if the difference value of the two adjacent detection count values is within a preset range, the clock signal is stable.
The processor 1001 may be an integrated circuit chip having signal processing capabilities. The processor 1001 may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. Which may implement or perform the various methods, steps, and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The Memory 1003 may include, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read Only Memory (PROM), Erasable Read Only Memory (EPROM), electrically Erasable Read Only Memory (EEPROM), and the like.
It will be appreciated that the configuration shown in FIG. 10 is merely illustrative and that the electronic device 1000 may include more or fewer components than shown in FIG. 10 or have a different configuration than shown in FIG. 10. The components shown in fig. 10 may be implemented in hardware, software, or a combination thereof. In this embodiment, the electronic device 1000 may be, but is not limited to, an entity device such as a desktop, a laptop, a smart phone, an intelligent wearable device, and a vehicle-mounted device, and may also be a virtual device such as a virtual machine. In addition, the electronic device 1000 is not necessarily a single device, and may also be a combination of multiple devices, such as a server cluster, and the like.
Embodiments of the present application further provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions, when the program instructions are executed by a computer, the computer being capable of executing the steps of the video signal stability detection method in the foregoing embodiments, for example, including: acquiring a video signal to be detected; and carrying out stability detection on the video signal to be detected according to the basic clock signal.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for video signal stability detection, comprising:
acquiring a video signal to be detected;
and carrying out stability detection on the video signal to be detected according to the basic clock signal.
2. The method for detecting the stability of the video signal according to claim 1, wherein the detecting the stability of the video signal to be detected according to the basic clock signal comprises:
and carrying out stability detection on the clock signal, the field synchronous signal, the line synchronous signal and the enabling signal of the video signal to be detected by utilizing the basic clock signal.
3. The method according to claim 2, wherein the detecting the stability of the clock signal of the video signal to be detected by using the base clock signal comprises:
performing stability detection on the clock signal by judging whether the counting times of the clock signal in the same time are the same or not;
performing stability detection on the field synchronization signal by judging whether the number of the field synchronization signals in the same time is the same;
performing stability detection on the line synchronization signal by judging whether the number of line synchronizations between two adjacent field synchronizations is the same; and the number of the first and second groups,
performing stability detection on the enabling signals by judging whether the enabling quantity between two adjacent line synchronizations is the same or not;
and if the frequency of a counter generated by the basic clock signal is f and the zero clearing time is t, the counting times in the zero clearing time are ft and the basic counting value is 0 to ft-1.
4. The method for detecting the stability of the video signal according to claim 3, wherein the detecting the stability of the clock signal by determining whether the number of times of counting the clock signal in the same time is the same comprises:
acquiring a plurality of detection count values of a counter generated by the clock signal when the basic count value is ft-1;
judging whether the difference value of two adjacent detection count values is within a preset range or not;
and if the difference value of the two adjacent detection count values is within the preset range, the clock signal is stable.
5. The method of claim 3, wherein the base clock signal generates a detection pulse when the base count value is ft-1, and the clock signal counts when the field sync signal is high;
the determining whether the number of the field syncs is the same in the same time to perform the stability detection on the field sync signal includes:
acquiring a plurality of detection count values of a counter generated by the clock signal when the detection pulse is high;
judging whether the difference value of two adjacent detection count values is within a preset range or not;
and if the difference value of the two adjacent detection count values is within the preset range, the field synchronization signal is stable.
6. The method of claim 3, wherein the base clock signal generates a detection pulse when the field sync signal is high, and the clock signal counts when the line sync signal is high;
the detecting the stability of the horizontal synchronization signal by judging whether the number of the horizontal synchronization between two adjacent field synchronizations is the same includes:
acquiring a plurality of detection count values of a counter generated by the clock signal when the detection pulse is high;
judging whether the difference value of two adjacent detection count values is within a preset range or not;
and if the difference value of the two adjacent detection count values is within the preset range, the line synchronization signal is stable.
7. The method of claim 3, wherein the base clock signal generates a detection pulse when the horizontal synchronization signal is high, and the clock signal counts when the enable signal is high;
the performing stability detection on the enable signal by judging whether the number of enables between two adjacent line syncs is the same includes:
acquiring a plurality of detection count values of a counter generated by the clock signal when the detection pulse is high;
judging whether the difference value of two adjacent detection count values is within a preset range or not;
and if the difference value of the two adjacent detection count values is within the preset range, the enabling signal is stable.
8. A video signal stability detection apparatus, comprising:
the acquisition module is used for acquiring a video signal to be detected;
and the detection module is used for carrying out stability detection on the video signal to be detected according to the basic clock signal.
9. An electronic device, comprising: a processor, a memory, and a bus; the processor and the memory are communicated with each other through the bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the video signal stability detection method of any of claims 1-7.
10. A non-transitory computer-readable storage medium storing computer instructions which, when executed by a computer, cause the computer to perform the video signal stability detection method according to any one of claims 1 to 7.
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