CN111445842B - Driving circuit and driving method of display array - Google Patents

Driving circuit and driving method of display array Download PDF

Info

Publication number
CN111445842B
CN111445842B CN202010453158.XA CN202010453158A CN111445842B CN 111445842 B CN111445842 B CN 111445842B CN 202010453158 A CN202010453158 A CN 202010453158A CN 111445842 B CN111445842 B CN 111445842B
Authority
CN
China
Prior art keywords
driving
transistor
electrode
control
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010453158.XA
Other languages
Chinese (zh)
Other versions
CN111445842A (en
Inventor
耿玓
苏悦
李泠
卢年端
刘明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN202010453158.XA priority Critical patent/CN111445842B/en
Publication of CN111445842A publication Critical patent/CN111445842A/en
Application granted granted Critical
Publication of CN111445842B publication Critical patent/CN111445842B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

The invention discloses a driving circuit and a driving method of a display array, relates to the technical field of display and aims to meet the display requirement of high resolution. The driving circuit of the display array comprises m rows by n columns of pixel driving units. Each pixel driving unit includes a plurality of gray-scale control periods within one driving cycle. The pixel driving unit includes: the driving circuit comprises a gating transistor, a first driving transistor, a storage capacitor and a light-emitting circuit. Wherein: the gate transistor is electrically connected to the control terminal of the first driving transistor and the storage capacitor, respectively. Each gating transistor is used for writing m data signals into each storage capacitor in a one-to-one correspondence mode under the control of m row scanning signals in each gray scale control period. The first electrode of the first driving transistor is electrically connected to the light emitting circuit. The second electrode of the first drive transistor is grounded. Each of the first driving transistors is for controlling each of the light emitting circuits to operate under the control of m data signals in each of the gray scale control periods.

Description

Driving circuit and driving method of display array
Technical Field
The invention relates to the technical field of display, in particular to a driving circuit and a driving method of a display array.
Background
The existing driving circuit of the display array adopts a mode of respectively controlling pixel points of each row to emit light at different time intervals after a scanning gating stage, so as to realize the control of the pixel array. However, the manner of controlling light emission at different periods of time results in low scanning efficiency and failure to achieve high-resolution display driving.
Disclosure of Invention
The invention aims to provide a driving circuit and a driving method of a display array, which adopt a driving mode that each row of light-emitting circuits simultaneously emit light and meet the display requirement of high resolution.
In order to achieve the above object, the present invention provides a driving circuit of a display array including m rows × n columns of pixel driving units, each of the pixel driving units including a plurality of gray scale control periods within one driving cycle, the pixel driving unit including: gate transistor, first drive transistor, storage capacitor and luminescent circuit, wherein:
the gating transistors are respectively and electrically connected with the control end of the first driving transistor and the storage capacitor, and each gating transistor is used for writing m data signals into each storage capacitor in a one-to-one correspondence manner under the control of m rows of scanning signals in each gray scale control period;
a first electrode of the first driving transistor is electrically connected with the light-emitting circuit, and a second electrode of the first driving transistor is grounded; each of the first driving transistors is for controlling each of the light emitting circuits to operate under the control of m data signals in each of the gray scale control periods.
Compared with the prior art, in the driving circuit of the display array provided by the invention, each gating transistor can write m data signals into each storage capacitor in a one-to-one correspondence manner under the control of m rows of scanning signals in each gray scale control period, and the storage capacitors store the corresponding data signals. Thereafter, each of the first driving transistors may control each of the light emitting circuits to operate under the control of m data signals in each of the gray scale control periods. That is to say, in each gray scale control period, after the m rows of pixels are all scan gated, each first driving transistor controls all the light emitting circuits to work under the control of m data signals, so that the time sequence separation of the scan gating stage and the light emitting control stage is realized, and the light emitting time can be saved. Under the same driving period, the driving circuit of the display array provided by the invention can scan more rows of pixels, and meets the display requirement of high resolution. And the pixel driving unit corresponding to each row of pixels controls the switching state of the gating transistor of the corresponding row under the control of different scanning signals, so that the condition that multiple rows are simultaneously started is avoided, and the working reliability of the driving circuit of the display array is improved.
The invention also provides a driving method of the display array, which is used for driving the driving circuit of the display array provided by the technical scheme;
the driving method of the display array comprises the following steps:
each gating transistor writes m data signals into each storage capacitor in a one-to-one correspondence mode under the control of m row scanning signals in each gray scale control period;
each of the first driving transistors controls each of the light emitting circuits to operate under the control of m data signals in each of the gray scale control periods.
Compared with the prior art, the beneficial effects of the driving method of the display array provided by the invention are the same as those of the driving circuit of the display array provided by the technical scheme, and the description is omitted here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a graph of a prior art voltage waveform at the control terminal of a PWM drive transistor;
FIG. 2 is a schematic structural diagram of a first pixel driving unit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a second pixel driving unit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a third pixel driving unit according to an embodiment of the present invention;
FIG. 5 is a voltage waveform diagram of scan signals and power signals in an embodiment of the present invention;
FIG. 6 is a voltage waveform diagram of the scan signal and the driving signal in an embodiment of the present invention;
fig. 7 is a flowchart of a driving method of a display array according to an embodiment of the invention.
Reference numerals:
1 is a gating transistor, 2 is a first driving transistor, 3 is a storage capacitor, 4 is a light emitting diode, and 5 is a second driving transistor.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Light-Emitting Diode (LED) displays have been widely studied in recent years and rapidly applied to new-generation displays due to their advantages of high brightness, high Light-Emitting efficiency, wide viewing angle, and low power consumption. In recent years, the field of high-resolution display is vigorously developed, but the conventional Organic Light Emitting Diode (OLED) display cannot meet the requirements of near-eye display high-resolution and large-size tiled display panels due to the limitations of size and luminous efficiency. Thus, micro-scale light emitting diode (μ LED) technology based on Thin Film Transistors (TFTs) has been developed. Due to the advantages of small size (10-100um), high luminous efficiency and the like, the mu LED is the first choice for manufacturing high-resolution micro-size display and engineering large-size display.
However, the current change rate after the μ LED is turned on is extremely high, and it is difficult to control the display gray-scale brightness by using the conventional analog voltage modulation method, so that a digital modulation method, i.e., Pulse Width Modulation (PWM) is required to control the display, i.e., different light-emitting time in one frame is equivalent to different light-emitting brightness. In the conventional PWM modulation (taking 6 bits as an example), the gate voltage of the driving transistor is controlled to adjust the on-off state of the pixel circuit, and the input data (0 or 1) is used to modulate different gray-scale brightness. As shown in fig. 1, a voltage waveform diagram of a control terminal of a conventional PWM modulation driving transistor is given. In fig. 1, TA is the gating period of the driving transistor, and the pixels of each row are turned on 6 times in a frame time. TL 1-TL 6 correspond to 6bit light emitting period respectively. When the input data is 1 in the TA stage, the pixel point emits light in the TL stage. When the input data is 0 in the TA stage, the pixel point does not emit light in the TL stage. And finally, integrating the total light-emitting time in one frame to obtain the total brightness of the pixel point in one frame.
The traditional PWM mode is only suitable for low-resolution and low-gray scale display and is difficult to meet the market demand of high resolution. Because when the resolution is increased, the number of gating rows is increased, and under the condition that any two rows are not opened simultaneously and the gating pulse width is not less than 2us, for the display application with the refresh frequency of more than 60Hz, the traditional PWM can only scan 30 rows under the condition of meeting 8bit gray scale which can be distinguished by human eyes, and the technical requirement is far lower than the high resolution.
In order to solve the above technical problem, embodiments of the present invention provide a driving circuit and a driving method for a display array. Each gating transistor in the driving circuit of the display array provided by the embodiment of the invention can pre-store m data signals into corresponding storage capacitors in a one-to-one correspondence manner. After the pixel driving units in m rows complete the scanning gating work, each first driving transistor controls each light-emitting circuit to work under the control of m data signals, so that the time sequence separation of the scanning gating stage and the light-emitting control stage is realized, and the light-emitting time can be saved. Under the same driving period, the driving circuit of the display array provided by the embodiment of the invention can scan more rows of pixels, and meets the display requirement of high resolution.
The embodiment of the invention provides a driving circuit of a display array, which comprises m rows by n columns of pixel driving units. Specifically, m and n are positive integers greater than or equal to 1. Specific values of m and n may be designed according to an arrangement manner of each pixel in an actual application scene, and are not specifically limited herein. For example: m equals 480 and n equals 640. Another example is: m equals 720 and n equals 1280.
As shown in fig. 5 and 6, each of the above-described pixel driving units includes a plurality of gray-scale control periods within one driving cycle. As shown in fig. 2 to 4, the pixel driving unit includes: a gate transistor 1, a first driving transistor 2, a storage capacitor 3, and a light emitting circuit (not shown). It is to be understood that the number of gray-scale control periods included per one driving cycle may be set with reference to the target gray-scale number a. Specifically, in order to ensure that the corresponding color effect is satisfied, the number of gray scale control periods included in each driving cycle should be greater than or equal to the target gray scale number a. For example: when the target gradation number a is 8 bits, the number of gradation control periods included in each driving cycle is 8. Another example is: when the target gradation number a is 12 bits, the number of gradation control periods included in each driving cycle is 12.
It should be noted that the number of gray scale control periods included in each driving cycle may affect how many rows of pixels can be scanned by the driving circuit of the display array. Specifically, in the case where the refresh frequency is the same, the drive period (refresh time of one frame) is a fixed value, and the smaller the gray-scale control period included in each drive period (the smaller the number of light-emitting times corresponding to each pixel), the larger the number of rows of pixels that can be scanned by the drive circuit of the display array at that time. When the number of gray scale control periods included in each driving period is larger (the number of light-emitting times corresponding to each pixel is larger), the number of rows of pixels that can be scanned by the driving circuit of the display array is smaller.
As shown in fig. 2 to 4, the gate transistor 1 is electrically connected to the control terminal of the first driving transistor 2 and the storage capacitor 3, respectively. Each gate transistor 1 is used to write m data signals into each storage capacitor 3 in a one-to-one correspondence under the control of m row scanning signals in each gray scale control period. It will be appreciated that each row of scanning signals is used to control the switching state of the gating transistor 1 comprised by the corresponding pixel drive circuit. And each data signal is used to control the operation (light emission or non-light emission) of a light emitting circuit included in the corresponding pixel driving circuit. At each gray scale control stage, according to the arrangement mode of the display array, m rows of scanning signals sequentially control the corresponding gating transistors 1, m data signals are written into the corresponding storage capacitors 3 in a one-to-one correspondence mode, and the storage capacitors 3 temporarily store one data signal for controlling whether the corresponding row of light-emitting circuits are started or not.
As shown in fig. 2 to 4, the first electrode of the first driving transistor 2 is electrically connected to a light emitting circuit. The second electrode of the first drive transistor 2 is grounded. Each of the first driving transistors 2 is for controlling each of the light emitting circuits to operate under the control of m data signals in each of the gray scale control periods.
Specifically, the gate transistor 1 and the first driving transistor 2 may be both N-type transistors, or both P-type transistors. The light emitting circuit may be an Organic Light Emitting Diode (OLED) or a Micro-LED (u-LED). The specific types of the gate transistor 1, the first driving transistor 2 and the light emitting circuit may be designed according to practical application scenarios, and are not limited herein.
In practical applications, the resolution that can be satisfied by the driving circuit of the display array provided by the embodiment of the present invention is shown in table 1.
Table 1 embodiments of the present invention may satisfy the resolution list
Scanning pulse width Gray scale Can satisfy the resolution
2us 8bit 720p(1280*720)
2us 12bit VGA(640*480)
1us 8bit QHD(2560*1440)
1us 12bit WXGA(1280*800)
Taking VGA mode with 640 × 480 resolution as an example, the technical parameters include 60Hz refresh frequency, 16.7ms refresh time of one frame, 2us scan pulse width of scan signal, and 12bit target gray level number a. In the above case, the drive circuit of the display array comprises 480 rows by 640 columns of pixel-driven cells. And each pixel driving unit includes 12 gray-scale control periods within one driving cycle.
In the driving circuit of the display array provided in the embodiment of the present invention, each gating transistor 1 may write m data signals into each storage capacitor 3 in a one-to-one correspondence manner under the control of m rows of scanning signals in each gray scale control period, and the storage capacitors 3 store the corresponding data signals. Thereafter, each of the first driving transistors 2 may control each of the light emitting circuits to operate under the control of m data signals in each of the gray scale control periods. That is to say, in each gray scale control period, after the m rows of pixels are all scan gated, each first driving transistor 2 will control all the light emitting circuits to work under the control of m data signals, so that the time sequence separation of the scan gating stage and the light emitting control stage is realized, and the light emitting time can be saved. Under the same driving period, the driving circuit of the display array provided by the embodiment of the invention can scan more rows of pixels, and meets the display driving requirement of high resolution. And the pixel driving unit corresponding to each row of pixels controls the switching state of the gating transistor 1 of the corresponding row under the control of different scanning signals, so that the condition that multiple rows are simultaneously started is avoided, and the working reliability of the driving circuit of the display array is improved. In addition, the driving circuit of the display array provided by the embodiment of the invention only comprises four parts, namely the gating transistor 1, the first driving transistor 2, the storage capacitor 3 and the light-emitting circuit, has a simpler structure, can be compatible with the existing driving framework, does not need additional control signals, and is a related signal power supply of the original traditional pixel circuit for scanning signals and data signals. Furthermore, the design of a drive circuit (GOA) integrated on the array is possible, the integration of the GOA can greatly reduce the design cost of the chip, and narrow-frame application is realized.
In one possible implementation, as shown in fig. 5 and 6, the gray-scale control period includes a scan sub-period and a light-emission control sub-period that are chronologically contiguous. Each gate transistor 1 is used to write m data signals into each storage capacitor 3 in a one-to-one correspondence under the control of m row scan signals in each scan sub-period. Each of the first driving transistors 2 is for controlling each of the light emitting circuits to operate under the control of m data signals in each of the light emission control sub-periods.
The duration of each scanning sub-period and each emission control sub-period may be designed according to an actual application scenario, and is not specifically limited herein. Illustratively, each of the scan subintervals described above has the same length and is further divided into m scan strobe pulses. Each emission control sub-period is 2 of unit duration(B-1)And have different B values from each other. B is a positive integer from 1 to A.
It should be noted that, taking the example of each driving cycle including 12 gray-scale control periods, when each emission control sub-period is 2 of the unit duration(B-1)When the light-emitting sub-periods have different B values, the positions of the light-emitting sub-periods TE 1-TE 12 can be freely exchanged, as long as the light-emitting time ratio corresponding to the 12 light-emitting sub-periods is ensured to be 1: 2: … …: 2048 and (4) making.
In a possible implementation, the light emitting circuit is a light emitting diode 4. The control terminal of the gating transistor 1 is connected to the scanning signal. The first electrode of the gating transistor 1 is switched in the data signal. The second electrode of the gate transistor 1 is electrically connected to the control terminal of the first drive transistor 2 and the first terminal of the storage capacitor 3, respectively. The first electrode of the first drive transistor 2 and the first electrode of the light emitting diode 4 are electrically connected. The second terminal of the storage capacitor 3 is electrically connected to the first electrode of the light emitting diode 4, or the second terminal of the storage capacitor 3 is grounded. The second electrode of the light emitting diode 4 is connected to a power signal.
Each of the first driving transistors 2 is for controlling each of the light emitting diodes 4 to operate under the control of the m data signals and the power signal in each of the gray scale control periods.
Illustratively, when the gating transistor 1 and the first driving transistor 2 are both N-type transistors or both P-type transistors, the control terminal of the gating transistor 1 is the gate of the gating transistor 1, the first electrode of the gating transistor 1 is the source of the gating transistor 1, and the second electrode of the gating transistor 1 is the drain of the gating transistor 1. Further, the control terminal, the first electrode, and the second electrode of the first driving transistor 2 correspond to the gate, the source, and the drain of the first driving transistor 2, respectively.
In practical application, as shown in fig. 5, TS1 to TS12 correspond to 12 scan sub-periods, and the progressive scan gating operation is performed in each scan sub-period. TE1 to TE12 correspond to 12 emission sub-periods in each of which each of the first driving transistors 2 controls the operation of the light emitting circuit under the control of m data signals. Sn (n is 1, 2, … …, 480) is a scan signal, and controls the switching state of the gate transistor 1 in the pixel driving unit circuit. DATA is the input DATA signal. VDD is a power supply signal. Specifically, when the gate transistor 1 is an N-type transistor, the gate transistor 1 is turned on when the scan signal is at a high level. In the case where the gate transistor 1 is a P-type transistor, the gate transistor 1 is turned on when the scanning signal is at a low level. When the driving circuit of the display array is in operation, after each gate transistor 1 is turned on, each data signal is input to the control terminal of the corresponding first driving transistor 2 and stored in the storage capacitor 3. Each data signal is divided into two states according to the gray scale of the displayed image: the state "0" corresponds to a low level, and the state "1" corresponds to a high level. In the emission control sub-period, each of the first driving transistors 2 controls the light emitting circuit to operate according to the state of the corresponding data signal stored on the corresponding storage capacitor 3. The timing sequence flow when the pixel driving is specifically realized is as follows:
in the TS1 phase, the gate transistors 1 of 480 rows are turned on in sequence. The on-time of the pass transistor 1 for each row is 2 us. At this time, 480 data signals are input to the control terminals of the respective first driving transistors 2 in a one-to-one correspondence. Since the power supply signal VDD is at a low level in the stages TS1 to TS12, the first driving transistor 2 is in an off state, and all the light emitting circuits do not emit light.
In the phase TE1, all scan signals Sn are put low and all gate transistors 1 are turned off. The power supply signal VDD becomes high level. If the DATA signal DATA input at the stage TS1 is low level DATA, the light emitting circuit corresponding thereto does not emit light at the stage TE 1. If the DATA signal DATA inputted at the stage TS1 is at a high level, the corresponding light emitting circuit emits light at the stage TE1, and the light emitting time lasts for T _ TE 1.
During the TS2 phase, the 480 row pass transistors 1 are again turned on in sequence. The gating transistor 1 of each row is on for 2 us. The DATA signal DATA is input to the control terminal of the corresponding first driving transistor 2. At this time, the power supply signal VDD is at a low level, and all the light emitting circuits do not emit light.
In the phase TE2, all scan signals Sn are put low and all gate transistors 1 are turned off. The power supply signal VDD becomes high level. If the DATA signal DATA input at the stage TS2 is at a low level, the light-emitting circuit corresponding thereto does not emit light at the stage TE 2. If the DATA signal DATA inputted at the stage TS2 is at a high level, the corresponding light emitting circuit emits light at the stage TE2, and the light emitting time lasts for T _ TE 2.
Similarly, the TS 3-TS 12 phases are the same as the TS1 and TS2 phases, the TE 3-TE 12 voltage states are the same as the TE1 and TE2 voltage states, and the light-emitting duration is T _ TE 3-T _ TE12 respectively. Wherein, T _ TE 1: t _ TE 2: … …: t _ TE 11: t _ TE12 ═ 1: 2: … …: 2048, the time duration of the latter light-emitting photon period is 2 times that of the former light-emitting photon period.
When the pass transistor 1 is a P-type transistor, the data signal, the scan signal, and the power signal may be switched between high and low levels. Specifically, in the stages TS1 to TS12, the on state of the gate transistor 1 corresponds to the low level of the scan signal Sn. The off state of the gate transistor 1 corresponds to a high level of the scan signal Sn. At the stages TE1 to TE12, the power signal VDD is low. At the stages TS1 to TS12, the power signal VDD is at a high level. The DATA signal DATA state "0" corresponds to a high level, and the DATA signal DATA state "1" corresponds to a low level.
In one possible implementation, as shown in fig. 3, the pixel driving unit further comprises a second driving transistor 5. The light emitting circuit is a light emitting diode 4.
The control terminal of the gating transistor 1 is connected to a scanning signal. The first electrode of the gating transistor 1 is switched in the data signal. The second electrode of the gate transistor 1 is electrically connected to the control terminal of the first drive transistor 2 and the first terminal of the storage capacitor 3, respectively. A second terminal of the storage capacitor 3 is electrically connected to the second electrode of the first driving transistor 2, or a second terminal of the storage capacitor 3 is electrically connected to the first electrode of the second driving transistor 5. The first electrode of the first drive transistor 2 is electrically connected to the first electrode of the second drive transistor 5. The control terminal of the second driving transistor 5 is connected to the driving signal. The second electrode of the second drive transistor 5 is electrically connected to the first electrode of the light emitting diode 4. The second electrode of the light emitting diode 4 is connected to a power signal.
Each first driving transistor 2 and each second driving transistor 5 are used to control each light emitting diode 4 to operate under the control of m data signals and driving signals in each gray scale control period.
It should be noted that, when the structure of the pixel driving unit is as shown in fig. 3, and the gating transistor 1, the first driving transistor 2, and the second driving transistor 5 are all N-type transistors, the specific driving manner corresponding to the pixel driving unit is as shown in fig. 6. The power supply signal VDD is always at a high level, and EM is a driving signal received by the control terminal of the second driving transistor 5. When the transistors are P-type transistors, the data signal, the scan signal, the power signal and the driving signal may be switched between high and low levels.
In one possible implementation, as shown in fig. 4, the pixel driving unit further comprises a second driving transistor 5. The light emitting circuit is a light emitting diode 4.
The control terminal of the gating transistor 1 is connected to a scanning signal. The first electrode of the gating transistor 1 is switched in the data signal. The second electrode of the gate transistor 1 is electrically connected to the control terminal of the first drive transistor 2 and the first terminal of the storage capacitor 3, respectively. A second terminal of the storage capacitor 3 is electrically connected to the second electrode of the first driving transistor 2, or a second terminal of the storage capacitor 3 is electrically connected to the first electrode of the light emitting diode 4. The first electrode of the first drive transistor 2 is electrically connected to the first electrode of the light emitting diode 4. The second electrode of the light emitting diode 4 is electrically connected to the first electrode of the second driving transistor 5. The control terminal of the second driving transistor 5 is connected to the driving signal. The second electrode of the second driving transistor 5 is connected to a power supply signal.
Each of the first driving transistors 2 and each of the second driving transistors 5 is for controlling each of the light emitting diodes 4 to operate under the control of the m data signals and the driving signals in each of the gray scale control periods.
It should be noted that, when the structure of the pixel driving unit is as shown in fig. 4, and the gating transistor 1, the first driving transistor 2, and the second driving transistor 5 are all N-type transistors, the specific driving manner corresponding to the pixel driving unit is as shown in fig. 6. The power supply signal VDD is always at a high level, and EM is a driving signal received by the control terminal of the second driving transistor 5. When the transistors are P-type transistors, the data signal, the scan signal, the power signal and the driving signal may be switched between high and low levels.
The embodiment of the invention also provides a driving method of the display array, which is used for driving the driving circuit of the display array provided by the embodiment.
As shown in fig. 7, the driving method of the display array includes:
step S101: each gate transistor 1 writes m data signals into each storage capacitor 3 in one-to-one correspondence under the control of m row scanning signals in each gray scale control period.
Step S102: each of the first driving transistors 2 controls each of the light emitting circuits to operate under the control of m data signals in each of the gray scale control periods.
The beneficial effects of the driving method of the display array provided by the embodiment of the invention are the same as those of the driving circuit of the display array provided by the above embodiment, and are not repeated herein.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (7)

1. A driving circuit of a display array comprising m rows by n columns of pixel driving units, each of the pixel driving units comprising a plurality of gray scale control periods within one driving cycle, the pixel driving unit comprising: gate transistor, first drive transistor, storage capacitor and luminescent circuit, wherein:
the gating transistors are respectively and electrically connected with the control end of the first driving transistor and the storage capacitors, and each gating transistor is used for writing m data signals into each storage capacitor in a one-to-one correspondence manner under the control of m rows of scanning signals in each gray scale control period;
a first electrode of the first driving transistor is electrically connected with the light-emitting circuit, and a second electrode of the first driving transistor is grounded; each of the first driving transistors is for controlling each of the light emitting circuits to operate under control of m of the data signals in each of the gray scale control periods; wherein the content of the first and second substances,
the gray scale control time interval comprises a scanning sub-time interval and a light-emitting control sub-time interval which are connected in time sequence;
each gating transistor is used for writing m data signals into each storage capacitor in a one-to-one correspondence mode under the control of m rows of scanning signals in each scanning sub-period; each of the first driving transistors is for controlling each of the light emitting circuits to operate under control of m of the data signals in each of the light emission control sub-periods.
2. The driving circuit of claim 1, wherein the number of the gray scale control periods included in each of the driving cycles is equal to a target gray scale number a, a being a positive integer greater than or equal to 1;
each scanning sub-period has the same length and is further divided into m scanning strobe pulses; each of the light-emitting control devicesSegment is 2 of unit duration(B-1) times and have different values of B from each other, B being a positive integer from 1 to a.
3. The driving circuit of claim 1, wherein the light emitting circuit is a light emitting diode, the control terminal of the gate transistor is connected to the scan signal, the first electrode of the gate transistor is connected to the data signal, the second electrode of the gate transistor is electrically connected to the control terminal of the first driving transistor and the first terminal of the storage capacitor, respectively, and the first electrode of the first driving transistor is electrically connected to the first electrode of the light emitting diode; the second end of the storage capacitor is electrically connected with the first electrode of the light emitting diode, or the second end of the storage capacitor is grounded; a second electrode of the light emitting diode is connected with a power supply signal;
each of the first driving transistors is used for controlling each of the light emitting diodes to work under the control of the power supply signal and the m data signals in each of the gray scale control periods.
4. The driving circuit of a display array according to claim 1, wherein the pixel driving unit further comprises a second driving transistor, and the light emitting circuit is a light emitting diode;
the control end of the gating transistor is connected with the scanning signal, the first electrode of the gating transistor is connected with the data signal, and the second electrode of the gating transistor is electrically connected with the control end of the first driving transistor and the first end of the storage capacitor respectively; the second end of the storage capacitor is electrically connected with the second electrode of the first driving transistor, or the second end of the storage capacitor is electrically connected with the first electrode of the second driving transistor; a first electrode of the first driving transistor is electrically connected with a first electrode of the second driving transistor, a control end of the second driving transistor is connected with a driving signal, a second electrode of the second driving transistor is electrically connected with a first electrode of the light emitting diode, and a second electrode of the light emitting diode is connected with a power supply signal;
each of the first driving transistors and each of the second driving transistors are used for controlling each of the light emitting diodes to operate under the control of m of the data signals and the driving signals in each of the gray scale control periods.
5. The driving circuit of a display array according to claim 1, wherein the pixel driving unit further comprises a second driving transistor, and the light emitting circuit is a light emitting diode;
the control end of the gating transistor is connected with the scanning signal, the first electrode of the gating transistor is connected with the data signal, and the second electrode of the gating transistor is electrically connected with the control end of the first driving transistor and the first end of the storage capacitor respectively; the second end of the storage capacitor is electrically connected with the second electrode of the first driving transistor, or the second end of the storage capacitor is electrically connected with the first electrode of the light emitting diode; a first electrode of the first driving transistor is electrically connected with a first electrode of the light emitting diode, a second electrode of the light emitting diode is electrically connected with a first electrode of the second driving transistor, a control end of the second driving transistor is connected with a driving signal, and a second electrode of the second driving transistor is connected with a power supply signal;
each of the first driving transistors and each of the second driving transistors are used for controlling each of the light emitting diodes to operate under the control of m of the data signals and the driving signals in each of the gray scale control periods.
6. A drive circuit for a display array according to any of claims 1 to 5, wherein the gate transistor and the first drive transistor are both N-type transistors or P-type transistors.
7. A driving method of a display array, characterized by driving a driving circuit of the display array according to any one of claims 1 to 6;
the driving method of the display array comprises the following steps:
each gating transistor writes data signals into each storage capacitor in a one-to-one correspondence mode under the control of m rows of scanning signals in scanning sub-periods included in each gray scale control period;
each of the first driving transistors controls each of the light emitting circuits to operate under control of m of the data signals in a light emission control sub-period included in each of the gray scale control periods.
CN202010453158.XA 2020-05-25 2020-05-25 Driving circuit and driving method of display array Active CN111445842B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010453158.XA CN111445842B (en) 2020-05-25 2020-05-25 Driving circuit and driving method of display array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010453158.XA CN111445842B (en) 2020-05-25 2020-05-25 Driving circuit and driving method of display array

Publications (2)

Publication Number Publication Date
CN111445842A CN111445842A (en) 2020-07-24
CN111445842B true CN111445842B (en) 2021-08-31

Family

ID=71652252

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010453158.XA Active CN111445842B (en) 2020-05-25 2020-05-25 Driving circuit and driving method of display array

Country Status (1)

Country Link
CN (1) CN111445842B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111968566B (en) 2020-08-27 2021-11-19 上海天马微电子有限公司 Light-emitting panel, driving method and manufacturing method thereof and display device
CN113012634A (en) * 2021-03-05 2021-06-22 京东方科技集团股份有限公司 Pixel circuit, driving method thereof and display device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103594059B (en) * 2013-11-29 2017-01-11 中国科学院上海高等研究院 AMOLED (Active Matrix/Organic Light-Emitting Diode) pixel driving circuit and method
CN104700778B (en) * 2015-03-27 2017-06-27 深圳市华星光电技术有限公司 AMOLED pixel-driving circuits and image element driving method
CN106097957A (en) * 2016-08-19 2016-11-09 京东方科技集团股份有限公司 Image element circuit and driving method, array base palte, display device
CN107369412B (en) * 2017-09-05 2023-05-23 京东方科技集团股份有限公司 Pixel circuit, driving method thereof and display device
CN110853576B (en) * 2019-11-20 2021-03-23 京东方科技集团股份有限公司 Display substrate and display device

Also Published As

Publication number Publication date
CN111445842A (en) 2020-07-24

Similar Documents

Publication Publication Date Title
CN109036279B (en) Array substrate, driving method, organic light emitting display panel and display device
US20210201760A1 (en) Pixel circuit and driving method thereof, display panel and driving method thereof, and display device
CN113707077B (en) Pixel driving circuit, driving method thereof and display substrate
CN106652908B (en) Organic light emitting display panel and its driving method, organic light-emitting display device
EP3916711B1 (en) Pixel driving circuit and driving method thereof, and display panel
KR20180002786A (en) Emission control devices and methods for display panel
US10204544B2 (en) Display panel driver and display apparatus having the same
US11183102B2 (en) Sub-pixel unit, display panel, and display apparatus and drive method therefor
US11100849B1 (en) Display device and driving method thereof
CN105074808A (en) Display device and method for driving display device
CN106991975B (en) A kind of pixel circuit and its driving method
CN110706653A (en) Drive circuit, display panel, drive method and display device
CN104575380A (en) Pixel circuit and active matrix organic light-emitting display
CN111445842B (en) Driving circuit and driving method of display array
WO2020228062A1 (en) Pixel drive circuit and display panel
US11978408B2 (en) Backlight unit, control method thereof, and liquid crystal display device
CN108538253B (en) The pixel driver system and driving method of displayer
CN111028766A (en) Pixel and display device
CN113724640B (en) Pixel driving circuit, driving method thereof, display panel and display device
CN111951731B (en) Pixel unit array, driving method thereof, display panel and display device
CN103971643A (en) Organic light emitting diode pixel circuit and display device
KR20140075040A (en) Organic light emitting display device and method for driving theteof
CN113990243A (en) Pixel circuit and driving method thereof, display device and display driving method
KR20220022526A (en) Gate driver and display apparatus having the same
US11380252B2 (en) Addressing for emissive displays

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant